asix-sigma: rework outer sample download loop (DRAM lines iteration)

[libsigrok.git] / src / hardware / asix-sigma / protocol.h

diff --git a/src/hardware/asix-sigma/protocol.h b/src/hardware/asix-sigma/protocol.h
index 0f8a242ff875011185fea819dae6ab6dba7b1e55..9fcbdd30f75f21a603a7ffdcf83f5a53570d45ed 100644 (file)
--- a/src/hardware/asix-sigma/protocol.h
+++ b/src/hardware/asix-sigma/protocol.h
@@ -367,8 +367,13 @@ struct dev_context {
                        uint16_t ts;
                        uint16_t sample;
                } last;
+               struct sigma_location {
+                       size_t raw, line, cluster, event;
+               } start, stop, trig, iter;
                struct {
+                       size_t lines_total, lines_done;
                        size_t lines_per_read; /* USB transfer limit */
+                       size_t lines_rcvd;
                        struct sigma_dram_line *rcvd_lines;
                        struct sigma_dram_line *curr_line;
                } fetch;