SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates);
-static const char sigma_firmware_files[][24] = {
- /* 50 MHz, supports 8 bit fractions */
- "asix-sigma-50.fw",
- /* 100 MHz */
- "asix-sigma-100.fw",
- /* 200 MHz */
- "asix-sigma-200.fw",
- /* Synchronous clock from pin */
- "asix-sigma-50sync.fw",
- /* Frequency counter */
- "asix-sigma-phasor.fw",
+static const char *firmware_files[] = {
+ "asix-sigma-50.fw", /* Up to 50MHz sample rate, 8bit divider. */
+ "asix-sigma-100.fw", /* 100MHz sample rate, fixed. */
+ "asix-sigma-200.fw", /* 200MHz sample rate, fixed. */
+ "asix-sigma-50sync.fw", /* Synchronous clock from external pin. */
+ "asix-sigma-phasor.fw", /* Frequency counter. */
};
+#define SIGMA_FIRMWARE_SIZE_LIMIT (256 * 1024)
+
static int sigma_read(void *buf, size_t size, struct dev_context *devc)
{
int ret;
int ret;
ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
- if (ret < 0) {
+ if (ret < 0)
sr_err("ftdi_write_data failed: %s",
ftdi_get_error_string(&devc->ftdic));
- } else if ((size_t) ret != size) {
+ else if ((size_t) ret != size)
sr_err("ftdi_write_data did not complete write.");
- }
return ret;
}
return sigma_read(data, len, devc);
}
-static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
-{
- uint8_t value;
-
- if (1 != sigma_read_register(reg, &value, 1, devc)) {
- sr_err("sigma_get_register: 1 byte expected");
- return 0;
- }
-
- return value;
-}
-
static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
struct dev_context *devc)
{
*triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
*stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
- /* Not really sure why this must be done, but according to spec. */
+ /*
+ * These "position" values point to after the event (end of
+ * capture data, trigger condition matched). This is why they
+ * get decremented here. Sample memory consists of 512-byte
+ * chunks with meta data in the upper 64 bytes. Thus when the
+ * decrements takes us into this upper part of the chunk, then
+ * further move backwards to the end of the chunk's data part.
+ */
if ((--*stoppos & 0x1ff) == 0x1ff)
*stoppos -= 64;
-
- if ((*--triggerpos & 0x1ff) == 0x1ff)
+ if ((--*triggerpos & 0x1ff) == 0x1ff)
*triggerpos -= 64;
return 1;
{
size_t i;
uint8_t buf[4096];
- int idx = 0;
+ int idx;
/* Send the startchunk. Index start with 1. */
- buf[0] = startchunk >> 8;
- buf[1] = startchunk & 0xff;
- sigma_write_register(WRITE_MEMROW, buf, 2, devc);
+ idx = 0;
+ buf[idx++] = startchunk >> 8;
+ buf[idx++] = startchunk & 0xff;
+ sigma_write_register(WRITE_MEMROW, buf, idx, devc);
/* Read the DRAM. */
+ idx = 0;
buf[idx++] = REG_DRAM_BLOCK;
buf[idx++] = REG_DRAM_WAIT_ACK;
return SR_OK;
}
-SR_PRIV void sigma_clear_helper(void *priv)
-{
- struct dev_context *devc;
-
- devc = priv;
-
- ftdi_deinit(&devc->ftdic);
-}
+/*
+ * See Xilinx UG332 for Spartan-3 FPGA configuration. The SIGMA device
+ * uses FTDI bitbang mode for netlist download in slave serial mode.
+ * (LATER: The OMEGA device's cable contains a more capable FTDI chip
+ * and uses MPSSE mode for bitbang. -- Can we also use FT232H in FT245
+ * compatible bitbang mode? For maximum code re-use and reduced libftdi
+ * dependency? See section 3.5.5 of FT232H: D0 clk, D1 data (out), D2
+ * data (in), D3 select, D4-7 GPIOL. See section 3.5.7 for MCU FIFO.)
+ *
+ * 750kbps rate (four times the speed of sigmalogan) works well for
+ * netlist download. All pins except INIT_B are output pins during
+ * configuration download.
+ *
+ * Some pins are inverted as a byproduct of level shifting circuitry.
+ * That's why high CCLK level (from the cable's point of view) is idle
+ * from the FPGA's perspective.
+ *
+ * The vendor's literature discusses a "suicide sequence" which ends
+ * regular FPGA execution and should be sent before entering bitbang
+ * mode and sending configuration data. Set D7 and toggle D2, D3, D4
+ * a few times.
+ */
+#define BB_PIN_CCLK (1 << 0) /* D0, CCLK */
+#define BB_PIN_PROG (1 << 1) /* D1, PROG */
+#define BB_PIN_D2 (1 << 2) /* D2, (part of) SUICIDE */
+#define BB_PIN_D3 (1 << 3) /* D3, (part of) SUICIDE */
+#define BB_PIN_D4 (1 << 4) /* D4, (part of) SUICIDE (unused?) */
+#define BB_PIN_INIT (1 << 5) /* D5, INIT, input pin */
+#define BB_PIN_DIN (1 << 6) /* D6, DIN */
+#define BB_PIN_D7 (1 << 7) /* D7, (part of) SUICIDE */
+
+#define BB_BITRATE (750 * 1000)
+#define BB_PINMASK (0xff & ~BB_PIN_INIT)
/*
- * Configure the FPGA for bitbang mode.
- * This sequence is documented in section 2. of the ASIX Sigma programming
- * manual. This sequence is necessary to configure the FPGA in the Sigma
- * into Bitbang mode, in which it can be programmed with the firmware.
+ * Initiate slave serial mode for configuration download. Which is done
+ * by pulsing PROG_B and sensing INIT_B. Make sure CCLK is idle before
+ * initiating the configuration download. Run a "suicide sequence" first
+ * to terminate the regular FPGA operation before reconfiguration.
*/
static int sigma_fpga_init_bitbang(struct dev_context *devc)
{
uint8_t suicide[] = {
- 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
+ BB_PIN_D7 | BB_PIN_D2,
+ BB_PIN_D7 | BB_PIN_D2,
+ BB_PIN_D7 | BB_PIN_D3,
+ BB_PIN_D7 | BB_PIN_D2,
+ BB_PIN_D7 | BB_PIN_D3,
+ BB_PIN_D7 | BB_PIN_D2,
+ BB_PIN_D7 | BB_PIN_D3,
+ BB_PIN_D7 | BB_PIN_D2,
};
uint8_t init_array[] = {
- 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01,
+ BB_PIN_CCLK,
+ BB_PIN_CCLK | BB_PIN_PROG,
+ BB_PIN_CCLK | BB_PIN_PROG,
+ BB_PIN_CCLK,
+ BB_PIN_CCLK,
+ BB_PIN_CCLK,
+ BB_PIN_CCLK,
+ BB_PIN_CCLK,
+ BB_PIN_CCLK,
+ BB_PIN_CCLK,
};
- int i, ret, timeout = (10 * 1000);
+ int retries, ret;
uint8_t data;
/* Section 2. part 1), do the FPGA suicide. */
sigma_write(suicide, sizeof(suicide), devc);
sigma_write(suicide, sizeof(suicide), devc);
- /* Section 2. part 2), do pulse on D1. */
+ /* Section 2. part 2), pulse PROG. */
sigma_write(init_array, sizeof(init_array), devc);
ftdi_usb_purge_buffers(&devc->ftdic);
- /* Wait until the FPGA asserts D6/INIT_B. */
- for (i = 0; i < timeout; i++) {
+ /* Wait until the FPGA asserts INIT_B. */
+ retries = 10;
+ while (retries--) {
ret = sigma_read(&data, 1, devc);
if (ret < 0)
return ret;
- /* Test if pin D6 got asserted. */
- if (data & (1 << 5))
- return 0;
- /* The D6 was not asserted yet, wait a bit. */
+ if (data & BB_PIN_INIT)
+ return SR_OK;
g_usleep(10 * 1000);
}
*/
static int sigma_fpga_init_la(struct dev_context *devc)
{
- /* Initialize the logic analyzer mode. */
+ /*
+ * TODO Construct the sequence at runtime? Such that request data
+ * and response check values will match more apparently?
+ */
+ uint8_t mode_regval = WMR_SDRAMINIT;
uint8_t logic_mode_start[] = {
+ /* Read ID register. */
REG_ADDR_LOW | (READ_ID & 0xf),
- REG_ADDR_HIGH | (READ_ID >> 8),
- REG_READ_ADDR, /* Read ID register. */
+ REG_ADDR_HIGH | (READ_ID >> 4),
+ REG_READ_ADDR,
+ /* Write 0x55 to scratch register, read back. */
REG_ADDR_LOW | (WRITE_TEST & 0xf),
REG_DATA_LOW | 0x5,
REG_DATA_HIGH_WRITE | 0x5,
- REG_READ_ADDR, /* Read scratch register. */
+ REG_READ_ADDR,
+ /* Write 0xaa to scratch register, read back. */
REG_DATA_LOW | 0xa,
REG_DATA_HIGH_WRITE | 0xa,
- REG_READ_ADDR, /* Read scratch register. */
+ REG_READ_ADDR,
+ /* Initiate SDRAM initialization in mode register. */
REG_ADDR_LOW | (WRITE_MODE & 0xf),
- REG_DATA_LOW | 0x0,
- REG_DATA_HIGH_WRITE | 0x8,
+ REG_DATA_LOW | (mode_regval & 0xf),
+ REG_DATA_HIGH_WRITE | (mode_regval >> 4),
};
-
uint8_t result[3];
int ret;
- /* Initialize the logic analyzer mode. */
+ /*
+ * Send the command sequence which contains 3 READ requests.
+ * Expect to see the corresponding 3 response bytes.
+ */
sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
-
- /* Expect a 3 byte reply since we issued three READ requests. */
- ret = sigma_read(result, 3, devc);
- if (ret != 3)
+ ret = sigma_read(result, ARRAY_SIZE(result), devc);
+ if (ret != ARRAY_SIZE(result))
goto err;
-
if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
goto err;
return SR_OK;
+
err:
sr_err("Configuration failed. Invalid reply received.");
return SR_ERR;
static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name,
uint8_t **bb_cmd, gsize *bb_cmd_size)
{
- size_t i, file_size, bb_size;
- char *firmware;
- uint8_t *bb_stream, *bbs;
+ uint8_t *firmware;
+ size_t file_size;
+ uint8_t *p;
+ size_t l;
uint32_t imm;
- int bit, v;
- int ret = SR_OK;
+ size_t bb_size;
+ uint8_t *bb_stream, *bbs, byte, mask, v;
/* Retrieve the on-disk firmware file content. */
- firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE,
- name, &file_size, 256 * 1024);
+ firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE, name,
+ &file_size, SIGMA_FIRMWARE_SIZE_LIMIT);
if (!firmware)
- return SR_ERR;
+ return SR_ERR_IO;
/* Unscramble the file content (XOR with "random" sequence). */
+ p = firmware;
+ l = file_size;
imm = 0x3f6df2ab;
- for (i = 0; i < file_size; i++) {
+ while (l--) {
imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
- firmware[i] ^= imm & 0xff;
+ *p++ ^= imm & 0xff;
}
/*
* the bitbang samples, and release the allocated memory.
*/
bb_size = file_size * 8 * 2;
- bb_stream = (uint8_t *)g_try_malloc(bb_size);
+ bb_stream = g_try_malloc(bb_size);
if (!bb_stream) {
sr_err("%s: Failed to allocate bitbang stream", __func__);
- ret = SR_ERR_MALLOC;
- goto exit;
+ g_free(firmware);
+ return SR_ERR_MALLOC;
}
bbs = bb_stream;
- for (i = 0; i < file_size; i++) {
- for (bit = 7; bit >= 0; bit--) {
- v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
- *bbs++ = v | 0x01;
+ p = firmware;
+ l = file_size;
+ while (l--) {
+ byte = *p++;
+ mask = 0x80;
+ while (mask) {
+ v = (byte & mask) ? BB_PIN_DIN : 0;
+ mask >>= 1;
+ *bbs++ = v | BB_PIN_CCLK;
*bbs++ = v;
}
}
+ g_free(firmware);
/* The transformation completed successfully, return the result. */
*bb_cmd = bb_stream;
*bb_cmd_size = bb_size;
-exit:
- g_free(firmware);
- return ret;
+ return SR_OK;
}
static int upload_firmware(struct sr_context *ctx,
unsigned char pins;
size_t buf_size;
const char *firmware;
- struct ftdi_context *ftdic;
/* Avoid downloading the same firmware multiple times. */
- firmware = sigma_firmware_files[firmware_idx];
+ firmware = firmware_files[firmware_idx];
if (devc->cur_firmware == firmware_idx) {
sr_info("Not uploading firmware file '%s' again.", firmware);
return SR_OK;
}
- /* Make sure it's an ASIX SIGMA. */
- ftdic = &devc->ftdic;
- ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
- USB_DESCRIPTION, NULL);
- if (ret < 0) {
- sr_err("ftdi_usb_open failed: %s",
- ftdi_get_error_string(ftdic));
- return 0;
- }
-
- ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
+ /* Set the cable to bitbang mode. */
+ ret = ftdi_set_bitmode(&devc->ftdic, BB_PINMASK, BITMODE_BITBANG);
if (ret < 0) {
sr_err("ftdi_set_bitmode failed: %s",
- ftdi_get_error_string(ftdic));
- return 0;
+ ftdi_get_error_string(&devc->ftdic));
+ return SR_ERR;
}
-
- /* Four times the speed of sigmalogan - Works well. */
- ret = ftdi_set_baudrate(ftdic, 750 * 1000);
+ ret = ftdi_set_baudrate(&devc->ftdic, BB_BITRATE);
if (ret < 0) {
sr_err("ftdi_set_baudrate failed: %s",
- ftdi_get_error_string(ftdic));
- return 0;
+ ftdi_get_error_string(&devc->ftdic));
+ return SR_ERR;
}
- /* Initialize the FPGA for firmware upload. */
+ /* Initiate FPGA configuration mode. */
ret = sigma_fpga_init_bitbang(devc);
if (ret)
return ret;
- /* Prepare firmware. */
+ /* Prepare wire format of the firmware image. */
ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size);
if (ret != SR_OK) {
sr_err("An error occurred while reading the firmware: %s",
return ret;
}
- /* Upload firmware. */
+ /* Write the FPGA netlist to the cable. */
sr_info("Uploading firmware file '%s'.", firmware);
sigma_write(buf, buf_size, devc);
g_free(buf);
- ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
+ /* Leave bitbang mode and discard pending input data. */
+ ret = ftdi_set_bitmode(&devc->ftdic, 0, BITMODE_RESET);
if (ret < 0) {
sr_err("ftdi_set_bitmode failed: %s",
- ftdi_get_error_string(ftdic));
+ ftdi_get_error_string(&devc->ftdic));
return SR_ERR;
}
-
- ftdi_usb_purge_buffers(ftdic);
-
- /* Discard garbage. */
+ ftdi_usb_purge_buffers(&devc->ftdic);
while (sigma_read(&pins, 1, devc) == 1)
;
if (ret != SR_OK)
return ret;
+ /* Keep track of successful firmware download completion. */
devc->cur_firmware = firmware_idx;
-
sr_info("Firmware uploaded.");
return SR_OK;
struct drv_context *drvc;
size_t i;
int ret;
+ int num_channels;
devc = sdi->priv;
drvc = sdi->driver->context;
* firmware is required and higher rates might limit the set
* of available channels.
*/
+ num_channels = devc->num_channels;
if (samplerate <= SR_MHZ(50)) {
ret = upload_firmware(drvc->sr_ctx, 0, devc);
- devc->num_channels = 16;
+ num_channels = 16;
} else if (samplerate == SR_MHZ(100)) {
ret = upload_firmware(drvc->sr_ctx, 1, devc);
- devc->num_channels = 8;
+ num_channels = 8;
} else if (samplerate == SR_MHZ(200)) {
ret = upload_firmware(drvc->sr_ctx, 2, devc);
- devc->num_channels = 4;
+ num_channels = 4;
}
/*
* an "event" (memory organization internal to the device).
*/
if (ret == SR_OK) {
+ devc->num_channels = num_channels;
devc->cur_samplerate = samplerate;
- devc->period_ps = 1000000000000ULL / samplerate;
devc->samples_per_event = 16 / devc->num_channels;
devc->state.state = SIGMA_IDLE;
}
if (match->match == SR_TRIGGER_ONE) {
devc->trigger.simplevalue |= channelbit;
devc->trigger.simplemask |= channelbit;
- }
- else if (match->match == SR_TRIGGER_ZERO) {
+ } else if (match->match == SR_TRIGGER_ZERO) {
devc->trigger.simplevalue &= ~channelbit;
devc->trigger.simplemask |= channelbit;
- }
- else if (match->match == SR_TRIGGER_FALLING) {
+ } else if (match->match == SR_TRIGGER_FALLING) {
devc->trigger.fallingmask |= channelbit;
trigger_set++;
- }
- else if (match->match == SR_TRIGGER_RISING) {
+ } else if (match->match == SR_TRIGGER_RISING) {
devc->trigger.risingmask |= channelbit;
trigger_set++;
}
return SR_OK;
}
-
/* Software trigger to determine exact trigger position. */
static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
struct sigma_trigger *t)
samples[2 * idx + 1] = (data >> 8) & 0xff;
}
+/*
+ * Local wrapper around sr_session_send() calls. Make sure to not send
+ * more samples to the session's datafeed than what was requested by a
+ * previously configured (optional) sample count.
+ */
+static void sigma_session_send(struct sr_dev_inst *sdi,
+ struct sr_datafeed_packet *packet)
+{
+ struct dev_context *devc;
+ struct sr_datafeed_logic *logic;
+ uint64_t send_now;
+
+ devc = sdi->priv;
+ if (devc->limit_samples) {
+ logic = (void *)packet->payload;
+ send_now = logic->length / logic->unitsize;
+ if (devc->sent_samples + send_now > devc->limit_samples) {
+ send_now = devc->limit_samples - devc->sent_samples;
+ logic->length = send_now * logic->unitsize;
+ }
+ if (!send_now)
+ return;
+ devc->sent_samples += send_now;
+ }
+
+ sr_session_send(sdi, packet);
+}
+
/*
* This size translates to: event count (1K events per cluster), times
* the sample width (unitsize, 16bits per event), times the maximum
logic.data = samples;
/*
- * First of all, send Sigrok a copy of the last sample from
- * previous cluster as many times as needed to make up for
- * the differential characteristics of data we get from the
- * Sigma. Sigrok needs one sample of data per period.
- *
- * One DRAM cluster contains a timestamp and seven samples,
- * the units of timestamp are "devc->period_ps" , the first
- * sample in the cluster happens at the time of the timestamp
- * and the remaining samples happen at timestamp +1...+6 .
+ * If this cluster is not adjacent to the previously received
+ * cluster, then send the appropriate number of samples with the
+ * previous values to the sigrok session. This "decodes RLE".
*/
for (ts = 0; ts < tsdiff; ts++) {
i = ts % 1024;
if ((i == 1023) || (ts == tsdiff - 1)) {
logic.length = (i + 1) * logic.unitsize;
for (j = 0; j < devc->samples_per_event; j++)
- sr_session_send(sdi, &packet);
+ sigma_session_send(sdi, &packet);
}
}
trig_count = trigger_offset * devc->samples_per_event;
packet.type = SR_DF_LOGIC;
logic.length = trig_count * logic.unitsize;
- sr_session_send(sdi, &packet);
+ sigma_session_send(sdi, &packet);
send_ptr += trig_count * logic.unitsize;
send_count -= trig_count;
}
/* Only send trigger if explicitly enabled. */
- if (devc->use_triggers) {
- packet.type = SR_DF_TRIGGER;
- sr_session_send(sdi, &packet);
- }
+ if (devc->use_triggers)
+ std_session_send_df_trigger(sdi);
}
/*
packet.type = SR_DF_LOGIC;
logic.length = send_count * logic.unitsize;
logic.data = send_ptr;
- sr_session_send(sdi, &packet);
+ sigma_session_send(sdi, &packet);
}
ss->lastsample = sample;
struct sr_dev_inst *sdi)
{
struct sigma_dram_cluster *dram_cluster;
- struct dev_context *devc = sdi->priv;
- unsigned int clusters_in_line =
- (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER;
+ struct dev_context *devc;
+ unsigned int clusters_in_line;
unsigned int events_in_cluster;
unsigned int i;
- uint32_t trigger_cluster = ~0, triggered = 0;
+ uint32_t trigger_cluster, triggered;
+
+ devc = sdi->priv;
+ clusters_in_line = events_in_line;
+ clusters_in_line += EVENTS_PER_CLUSTER - 1;
+ clusters_in_line /= EVENTS_PER_CLUSTER;
+ trigger_cluster = ~0;
+ triggered = 0;
/* Check if trigger is in this chunk. */
if (trigger_event < (64 * 7)) {
static int download_capture(struct sr_dev_inst *sdi)
{
- struct dev_context *devc = sdi->priv;
const uint32_t chunks_per_read = 32;
+
+ struct dev_context *devc;
struct sigma_dram_line *dram_line;
int bufsz;
uint32_t stoppos, triggerpos;
uint8_t modestatus;
-
uint32_t i;
uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
- uint32_t dl_events_in_line = 64 * 7;
- uint32_t trg_line = ~0, trg_event = ~0;
+ uint32_t dl_first_line, dl_line;
+ uint32_t dl_events_in_line;
+ uint32_t trg_line, trg_event;
- dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
- if (!dram_line)
- return FALSE;
+ devc = sdi->priv;
+ dl_events_in_line = 64 * 7;
sr_info("Downloading sample data.");
+ devc->state.state = SIGMA_DOWNLOAD;
- /* Stop acquisition. */
- sigma_set_register(WRITE_MODE, 0x11, devc);
+ /*
+ * Ask the hardware to stop data acquisition. Reception of the
+ * FORCESTOP request makes the hardware "disable RLE" (store
+ * clusters to DRAM regardless of whether pin state changes) and
+ * raise the POSTTRIGGERED flag.
+ */
+ sigma_set_register(WRITE_MODE, WMR_FORCESTOP | WMR_SDRAMWRITEEN, devc);
+ do {
+ if (sigma_read_register(READ_MODE, &modestatus, 1, devc) != 1) {
+ sr_err("failed while waiting for RMR_POSTTRIGGERED bit");
+ return FALSE;
+ }
+ } while (!(modestatus & RMR_POSTTRIGGERED));
/* Set SDRAM Read Enable. */
- sigma_set_register(WRITE_MODE, 0x02, devc);
+ sigma_set_register(WRITE_MODE, WMR_SDRAMREADEN, devc);
/* Get the current position. */
sigma_read_pos(&stoppos, &triggerpos, devc);
/* Check if trigger has fired. */
- modestatus = sigma_get_register(READ_MODE, devc);
- if (modestatus & 0x20) {
+ if (sigma_read_register(READ_MODE, &modestatus, 1, devc) != 1) {
+ sr_err("failed to read READ_MODE register");
+ return FALSE;
+ }
+ trg_line = ~0;
+ trg_event = ~0;
+ if (modestatus & RMR_TRIGGERED) {
trg_line = triggerpos >> 9;
trg_event = triggerpos & 0x1ff;
}
+ devc->sent_samples = 0;
+
/*
- * Determine how many 1024b "DRAM lines" do we need to read from the
- * Sigma so we have a complete set of samples. Note that the last
- * line can be only partial, containing less than 64 clusters.
+ * Determine how many "DRAM lines" of 1024 bytes each we need to
+ * retrieve from the Sigma hardware, so that we have a complete
+ * set of samples. Note that the last line need not contain 64
+ * clusters, it might be partially filled only.
+ *
+ * When RMR_ROUND is set, the circular buffer in DRAM has wrapped
+ * around. Since the status of the very next line is uncertain in
+ * that case, we skip it and start reading from the next line. The
+ * circular buffer has 32K lines (0x8000).
*/
dl_lines_total = (stoppos >> 9) + 1;
-
+ if (modestatus & RMR_ROUND) {
+ dl_first_line = dl_lines_total + 1;
+ dl_lines_total = 0x8000 - 2;
+ } else {
+ dl_first_line = 0;
+ }
+ dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
+ if (!dram_line)
+ return FALSE;
dl_lines_done = 0;
-
while (dl_lines_total > dl_lines_done) {
/* We can download only up-to 32 DRAM lines in one go! */
- dl_lines_curr = MIN(chunks_per_read, dl_lines_total);
+ dl_lines_curr = MIN(chunks_per_read, dl_lines_total - dl_lines_done);
- bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr,
+ dl_line = dl_first_line + dl_lines_done;
+ dl_line %= 0x8000;
+ bufsz = sigma_read_dram(dl_line, dl_lines_curr,
(uint8_t *)dram_line, devc);
/* TODO: Check bufsz. For now, just avoid compiler warnings. */
(void)bufsz;
dl_lines_done += dl_lines_curr;
}
+ g_free(dram_line);
std_session_send_df_end(sdi);
- sdi->driver->dev_acquisition_stop(sdi);
-
- g_free(dram_line);
+ devc->state.state = SIGMA_IDLE;
+ sr_dev_acquisition_stop(sdi);
return TRUE;
}
/*
- * Handle the Sigma when in CAPTURE mode. This function checks:
- * - Sampling time ended
- * - DRAM capacity overflow
- * This function triggers download of the samples from Sigma
- * in case either of the above conditions is true.
+ * Periodically check the Sigma status when in CAPTURE mode. This routine
+ * checks whether the configured sample count or sample time have passed,
+ * and will stop acquisition and download the acquired samples.
*/
static int sigma_capture_mode(struct sr_dev_inst *sdi)
{
- struct dev_context *devc = sdi->priv;
-
+ struct dev_context *devc;
uint64_t running_msec;
- struct timeval tv;
+ uint64_t current_time;
- uint32_t stoppos, triggerpos;
+ devc = sdi->priv;
- /* Check if the selected sampling duration passed. */
- gettimeofday(&tv, 0);
- running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
- (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
+ /*
+ * Check if the selected sampling duration passed. Sample count
+ * limits are covered by this enforced timeout as well.
+ */
+ current_time = g_get_monotonic_time();
+ running_msec = (current_time - devc->start_time) / 1000;
if (running_msec >= devc->limit_msec)
return download_capture(sdi);
- /* Get the position in DRAM to which the FPGA is writing now. */
- sigma_read_pos(&stoppos, &triggerpos, devc);
- /* Test if DRAM is full and if so, download the data. */
- if ((stoppos >> 9) == 32767)
- return download_capture(sdi);
-
return TRUE;
}
if (devc->state.state == SIGMA_IDLE)
return TRUE;
+ /*
+ * When the application has requested to stop the acquisition,
+ * then immediately start downloading sample data. Otherwise
+ * keep checking configured limits which will terminate the
+ * acquisition and initiate download.
+ */
+ if (devc->state.state == SIGMA_STOPPING)
+ return download_capture(sdi);
if (devc->state.state == SIGMA_CAPTURE)
return sigma_capture_mode(sdi);
projects / libsigrok.git / blobdiff