* Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
* Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
* Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
+ * Copyright (C) 2020 Gerhard Sittig <gerhard.sittig@gmx.net>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* few discrete values, while setter routines accept any user specified
* rate that is supported by the hardware.
*/
-SR_PRIV const uint64_t samplerates[] = {
+static const uint64_t samplerates[] = {
/* 50MHz and integer divider. 1/2/5 steps (where possible). */
SR_KHZ(200), SR_KHZ(500),
SR_MHZ(1), SR_MHZ(2), SR_MHZ(5),
SR_MHZ(100), SR_MHZ(200),
};
-SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates);
+SR_PRIV GVariant *sigma_get_samplerates_list(void)
+{
+ return std_gvar_samplerates(samplerates, ARRAY_SIZE(samplerates));
+}
static const char *firmware_files[] = {
[SIGMA_FW_50MHZ] = "asix-sigma-50.fw", /* 50MHz, 8bit divider. */
#define SIGMA_FIRMWARE_SIZE_LIMIT (256 * 1024)
-static int sigma_read(struct dev_context *devc, void *buf, size_t size)
+static int sigma_ftdi_open(const struct sr_dev_inst *sdi)
{
+ struct dev_context *devc;
+ int vid, pid;
+ const char *serno;
int ret;
- ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
+ devc = sdi->priv;
+ if (!devc)
+ return SR_ERR_ARG;
+
+ if (devc->ftdi.is_open)
+ return SR_OK;
+
+ vid = devc->id.vid;
+ pid = devc->id.pid;
+ serno = sdi->serial_num;
+ if (!vid || !pid || !serno || !*serno)
+ return SR_ERR_ARG;
+
+ ret = ftdi_init(&devc->ftdi.ctx);
+ if (ret < 0) {
+ sr_err("Cannot initialize FTDI context (%d): %s.",
+ ret, ftdi_get_error_string(&devc->ftdi.ctx));
+ return SR_ERR_IO;
+ }
+ ret = ftdi_usb_open_desc_index(&devc->ftdi.ctx,
+ vid, pid, NULL, serno, 0);
if (ret < 0) {
- sr_err("ftdi_read_data failed: %s",
- ftdi_get_error_string(&devc->ftdic));
+ sr_err("Cannot open device (%d): %s.",
+ ret, ftdi_get_error_string(&devc->ftdi.ctx));
+ return SR_ERR_IO;
}
+ devc->ftdi.is_open = TRUE;
+
+ return SR_OK;
+}
+
+static int sigma_ftdi_close(struct dev_context *devc)
+{
+ int ret;
+
+ ret = ftdi_usb_close(&devc->ftdi.ctx);
+ devc->ftdi.is_open = FALSE;
+ devc->ftdi.must_close = FALSE;
+ ftdi_deinit(&devc->ftdi.ctx);
+
+ return ret == 0 ? SR_OK : SR_ERR_IO;
+}
+
+SR_PRIV int sigma_check_open(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc;
+ int ret;
+
+ if (!sdi)
+ return SR_ERR_ARG;
+ devc = sdi->priv;
+ if (!devc)
+ return SR_ERR_ARG;
+
+ if (devc->ftdi.is_open)
+ return SR_OK;
+
+ ret = sigma_ftdi_open(sdi);
+ if (ret != SR_OK)
+ return ret;
+ devc->ftdi.must_close = TRUE;
return ret;
}
-static int sigma_write(struct dev_context *devc, const void *buf, size_t size)
+SR_PRIV int sigma_check_close(struct dev_context *devc)
{
int ret;
- ret = ftdi_write_data(&devc->ftdic, buf, size);
- if (ret < 0)
- sr_err("ftdi_write_data failed: %s",
- ftdi_get_error_string(&devc->ftdic));
- else if ((size_t) ret != size)
- sr_err("ftdi_write_data did not complete write.");
+ if (!devc)
+ return SR_ERR_ARG;
+
+ if (devc->ftdi.must_close) {
+ ret = sigma_ftdi_close(devc);
+ if (ret != SR_OK)
+ return ret;
+ devc->ftdi.must_close = FALSE;
+ }
+
+ return SR_OK;
+}
+
+SR_PRIV int sigma_force_open(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc;
+ int ret;
+
+ if (!sdi)
+ return SR_ERR_ARG;
+ devc = sdi->priv;
+ if (!devc)
+ return SR_ERR_ARG;
+
+ ret = sigma_ftdi_open(sdi);
+ if (ret != SR_OK)
+ return ret;
+ devc->ftdi.must_close = FALSE;
+
+ return SR_OK;
+}
+
+SR_PRIV int sigma_force_close(struct dev_context *devc)
+{
+ return sigma_ftdi_close(devc);
+}
+
+/*
+ * BEWARE! Error propagation is important, as are kinds of return values.
+ *
+ * - Raw USB tranport communicates the number of sent or received bytes,
+ * or negative error codes in the external library's(!) range of codes.
+ * - Internal routines at the "sigrok driver level" communicate success
+ * or failure in terms of SR_OK et al error codes.
+ * - Main loop style receive callbacks communicate booleans which arrange
+ * for repeated calls to drive progress during acquisition.
+ *
+ * Careful consideration by maintainers is essential, because all of the
+ * above kinds of values are assignment compatbile from the compiler's
+ * point of view. Implementation errors will go unnoticed at build time.
+ */
+
+static int sigma_read_raw(struct dev_context *devc, void *buf, size_t size)
+{
+ int ret;
+
+ ret = ftdi_read_data(&devc->ftdi.ctx, (unsigned char *)buf, size);
+ if (ret < 0) {
+ sr_err("USB data read failed: %s",
+ ftdi_get_error_string(&devc->ftdi.ctx));
+ }
return ret;
}
+static int sigma_write_raw(struct dev_context *devc, const void *buf, size_t size)
+{
+ int ret;
+
+ ret = ftdi_write_data(&devc->ftdi.ctx, buf, size);
+ if (ret < 0) {
+ sr_err("USB data write failed: %s",
+ ftdi_get_error_string(&devc->ftdi.ctx));
+ } else if ((size_t)ret != size) {
+ sr_err("USB data write length mismatch.");
+ }
+
+ return ret;
+}
+
+static int sigma_read_sr(struct dev_context *devc, void *buf, size_t size)
+{
+ int ret;
+
+ ret = sigma_read_raw(devc, buf, size);
+ if (ret < 0 || (size_t)ret != size)
+ return SR_ERR_IO;
+
+ return SR_OK;
+}
+
+static int sigma_write_sr(struct dev_context *devc, const void *buf, size_t size)
+{
+ int ret;
+
+ ret = sigma_write_raw(devc, buf, size);
+ if (ret < 0 || (size_t)ret != size)
+ return SR_ERR_IO;
+
+ return SR_OK;
+}
+
+/*
+ * Implementor's note: The local write buffer's size shall suffice for
+ * any know FPGA register transaction that is involved in the supported
+ * feature set of this sigrok device driver. If the length check trips,
+ * that's a programmer's error and needs adjustment in the complete call
+ * stack of the respective code path.
+ */
+#define SIGMA_MAX_REG_DEPTH 32
+
/*
- * NOTE: We chose the buffer size to be large enough to hold any write to the
- * device. We still print a message just in case.
+ * Implementor's note: The FPGA command set supports register access
+ * with automatic address adjustment. This operation is documented to
+ * wrap within a 16-address range, it cannot cross boundaries where the
+ * register address' nibble overflows. An internal helper assumes that
+ * callers remain within this auto-adjustment range, and thus multi
+ * register access requests can never exceed that count.
*/
+#define SIGMA_MAX_REG_COUNT 16
+
SR_PRIV int sigma_write_register(struct dev_context *devc,
uint8_t reg, uint8_t *data, size_t len)
{
- uint8_t buf[80], *wrptr;
- size_t idx, count;
- int ret;
+ uint8_t buf[2 + SIGMA_MAX_REG_DEPTH * 2], *wrptr;
+ size_t idx;
- if (2 + 2 * len > sizeof(buf)) {
- sr_err("Write buffer too small to write %zu bytes.", len);
+ if (len > SIGMA_MAX_REG_DEPTH) {
+ sr_err("Short write buffer for %zu bytes to reg %u.", len, reg);
return SR_ERR_BUG;
}
wrptr = buf;
- write_u8_inc(&wrptr, REG_ADDR_LOW | (reg & 0xf));
- write_u8_inc(&wrptr, REG_ADDR_HIGH | (reg >> 4));
+ write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(reg));
+ write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(reg));
for (idx = 0; idx < len; idx++) {
- write_u8_inc(&wrptr, REG_DATA_LOW | (data[idx] & 0xf));
- write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | (data[idx] >> 4));
+ write_u8_inc(&wrptr, REG_DATA_LOW | LO4(data[idx]));
+ write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | HI4(data[idx]));
}
- count = wrptr - buf;
- ret = sigma_write(devc, buf, count);
- if (ret != SR_OK)
- return ret;
- return SR_OK;
+ return sigma_write_sr(devc, buf, wrptr - buf);
}
SR_PRIV int sigma_set_register(struct dev_context *devc,
uint8_t reg, uint8_t *data, size_t len)
{
uint8_t buf[3], *wrptr;
+ int ret;
wrptr = buf;
- write_u8_inc(&wrptr, REG_ADDR_LOW | (reg & 0xf));
- write_u8_inc(&wrptr, REG_ADDR_HIGH | (reg >> 4));
+ write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(reg));
+ write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(reg));
write_u8_inc(&wrptr, REG_READ_ADDR);
- sigma_write(devc, buf, wrptr - buf);
+ ret = sigma_write_sr(devc, buf, wrptr - buf);
+ if (ret != SR_OK)
+ return ret;
+
+ return sigma_read_sr(devc, data, len);
+}
- return sigma_read(devc, data, len);
+static int sigma_get_register(struct dev_context *devc,
+ uint8_t reg, uint8_t *data)
+{
+ return sigma_read_register(devc, reg, data, sizeof(*data));
+}
+
+static int sigma_get_registers(struct dev_context *devc,
+ uint8_t reg, uint8_t *data, size_t count)
+{
+ uint8_t buf[2 + SIGMA_MAX_REG_COUNT], *wrptr;
+ size_t idx;
+ int ret;
+
+ if (count > SIGMA_MAX_REG_COUNT) {
+ sr_err("Short command buffer for %zu reg reads at %u.", count, reg);
+ return SR_ERR_BUG;
+ }
+
+ wrptr = buf;
+ write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(reg));
+ write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(reg));
+ for (idx = 0; idx < count; idx++)
+ write_u8_inc(&wrptr, REG_READ_ADDR | REG_ADDR_INC);
+ ret = sigma_write_sr(devc, buf, wrptr - buf);
+ if (ret != SR_OK)
+ return ret;
+
+ return sigma_read_sr(devc, data, count);
}
static int sigma_read_pos(struct dev_context *devc,
- uint32_t *stoppos, uint32_t *triggerpos)
+ uint32_t *stoppos, uint32_t *triggerpos, uint8_t *mode)
{
+ uint8_t result[7];
+ const uint8_t *rdptr;
+ uint32_t v32;
+ uint8_t v8;
+ int ret;
+
/*
- * Read 6 registers starting at trigger position LSB.
- * Which yields two 24bit counter values.
+ * Read 7 registers starting at trigger position LSB.
+ * Which yields two 24bit counter values, and mode flags.
*/
- const uint8_t buf[] = {
- REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
- REG_READ_ADDR | REG_ADDR_INC,
- REG_READ_ADDR | REG_ADDR_INC,
- REG_READ_ADDR | REG_ADDR_INC,
- REG_READ_ADDR | REG_ADDR_INC,
- REG_READ_ADDR | REG_ADDR_INC,
- REG_READ_ADDR | REG_ADDR_INC,
- }, *rdptr;
- uint8_t result[6];
-
- sigma_write(devc, buf, sizeof(buf));
-
- sigma_read(devc, result, sizeof(result));
+ ret = sigma_get_registers(devc, READ_TRIGGER_POS_LOW,
+ result, sizeof(result));
+ if (ret != SR_OK)
+ return ret;
rdptr = &result[0];
- *triggerpos = read_u24le_inc(&rdptr);
- *stoppos = read_u24le_inc(&rdptr);
+ v32 = read_u24le_inc(&rdptr);
+ if (triggerpos)
+ *triggerpos = v32;
+ v32 = read_u24le_inc(&rdptr);
+ if (stoppos)
+ *stoppos = v32;
+ v8 = read_u8_inc(&rdptr);
+ if (mode)
+ *mode = v8;
/*
* These positions consist of "the memory row" in the MSB fields,
* cater for the timestamps when the decrement carries over to
* a different memory row.
*/
- if ((--*stoppos & ROW_MASK) == ROW_MASK)
+ if (stoppos && (--*stoppos & ROW_MASK) == ROW_MASK)
*stoppos -= CLUSTERS_PER_ROW;
- if ((--*triggerpos & ROW_MASK) == ROW_MASK)
+ if (triggerpos && (--*triggerpos & ROW_MASK) == ROW_MASK)
*triggerpos -= CLUSTERS_PER_ROW;
return SR_OK;
}
static int sigma_read_dram(struct dev_context *devc,
- uint16_t startchunk, size_t numchunks, uint8_t *data)
+ size_t startchunk, size_t numchunks, uint8_t *data)
{
- uint8_t buf[128], *wrptr;
+ uint8_t buf[128], *wrptr, regval;
size_t chunk;
- int sel;
+ int sel, ret;
gboolean is_last;
if (2 + 3 * numchunks > ARRAY_SIZE(buf)) {
- sr_err("Read buffer too small to read %zu DRAM rows", numchunks);
+ sr_err("Short write buffer for %zu DRAM row reads.", numchunks);
return SR_ERR_BUG;
}
/* Communicate DRAM start address (memory row, aka samples line). */
wrptr = buf;
- write_u8_inc(&wrptr, startchunk >> 8);
- write_u8_inc(&wrptr, startchunk & 0xff);
- sigma_write_register(devc, WRITE_MEMROW, buf, wrptr - buf);
+ write_u16be_inc(&wrptr, startchunk);
+ ret = sigma_write_register(devc, WRITE_MEMROW, buf, wrptr - buf);
+ if (ret != SR_OK)
+ return ret;
/*
* Access DRAM content. Fetch from DRAM to FPGA's internal RAM,
for (chunk = 0; chunk < numchunks; chunk++) {
sel = chunk % 2;
is_last = chunk == numchunks - 1;
- if (!is_last)
- write_u8_inc(&wrptr, REG_DRAM_BLOCK | REG_DRAM_SEL_BOOL(!sel));
- write_u8_inc(&wrptr, REG_DRAM_BLOCK_DATA | REG_DRAM_SEL_BOOL(sel));
+ if (!is_last) {
+ regval = REG_DRAM_BLOCK | REG_DRAM_SEL_BOOL(!sel);
+ write_u8_inc(&wrptr, regval);
+ }
+ regval = REG_DRAM_BLOCK_DATA | REG_DRAM_SEL_BOOL(sel);
+ write_u8_inc(&wrptr, regval);
if (!is_last)
write_u8_inc(&wrptr, REG_DRAM_WAIT_ACK);
}
- sigma_write(devc, buf, wrptr - buf);
+ ret = sigma_write_sr(devc, buf, wrptr - buf);
+ if (ret != SR_OK)
+ return ret;
- return sigma_read(devc, data, numchunks * ROW_LENGTH_BYTES);
+ return sigma_read_sr(devc, data, numchunks * ROW_LENGTH_BYTES);
}
/* Upload trigger look-up tables to Sigma. */
SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc,
struct triggerlut *lut)
{
- int i;
- uint8_t tmp[2];
+ size_t lut_addr;
uint16_t bit;
- uint8_t buf[6], *wrptr, regval;
+ uint8_t m3d, m2d, m1d, m0d;
+ uint8_t buf[6], *wrptr, v8;
+ uint16_t selreg;
+ int ret;
- /* Transpose the table and send to Sigma. */
- for (i = 0; i < 16; i++) {
- bit = 1 << i;
+ /*
+ * Translate the LUT part of the trigger configuration from the
+ * application's perspective to the hardware register's bitfield
+ * layout. Send the LUT to the device. This configures the logic
+ * which combines pin levels or edges.
+ */
+ for (lut_addr = 0; lut_addr < 16; lut_addr++) {
+ bit = BIT(lut_addr);
- tmp[0] = tmp[1] = 0;
+ /* - M4 M3S M3Q */
+ m3d = 0;
+ if (lut->m4 & bit)
+ m3d |= BIT(2);
+ if (lut->m3s & bit)
+ m3d |= BIT(1);
+ if (lut->m3q & bit)
+ m3d |= BIT(0);
- if (lut->m2d[0] & bit)
- tmp[0] |= 0x01;
- if (lut->m2d[1] & bit)
- tmp[0] |= 0x02;
- if (lut->m2d[2] & bit)
- tmp[0] |= 0x04;
+ /* M2D3 M2D2 M2D1 M2D0 */
+ m2d = 0;
if (lut->m2d[3] & bit)
- tmp[0] |= 0x08;
+ m2d |= BIT(3);
+ if (lut->m2d[2] & bit)
+ m2d |= BIT(2);
+ if (lut->m2d[1] & bit)
+ m2d |= BIT(1);
+ if (lut->m2d[0] & bit)
+ m2d |= BIT(0);
- if (lut->m3 & bit)
- tmp[0] |= 0x10;
- if (lut->m3s & bit)
- tmp[0] |= 0x20;
- if (lut->m4 & bit)
- tmp[0] |= 0x40;
+ /* M1D3 M1D2 M1D1 M1D0 */
+ m1d = 0;
+ if (lut->m1d[3] & bit)
+ m1d |= BIT(3);
+ if (lut->m1d[2] & bit)
+ m1d |= BIT(2);
+ if (lut->m1d[1] & bit)
+ m1d |= BIT(1);
+ if (lut->m1d[0] & bit)
+ m1d |= BIT(0);
- if (lut->m0d[0] & bit)
- tmp[1] |= 0x01;
- if (lut->m0d[1] & bit)
- tmp[1] |= 0x02;
- if (lut->m0d[2] & bit)
- tmp[1] |= 0x04;
+ /* M0D3 M0D2 M0D1 M0D0 */
+ m0d = 0;
if (lut->m0d[3] & bit)
- tmp[1] |= 0x08;
-
- if (lut->m1d[0] & bit)
- tmp[1] |= 0x10;
- if (lut->m1d[1] & bit)
- tmp[1] |= 0x20;
- if (lut->m1d[2] & bit)
- tmp[1] |= 0x40;
- if (lut->m1d[3] & bit)
- tmp[1] |= 0x80;
+ m0d |= BIT(3);
+ if (lut->m0d[2] & bit)
+ m0d |= BIT(2);
+ if (lut->m0d[1] & bit)
+ m0d |= BIT(1);
+ if (lut->m0d[0] & bit)
+ m0d |= BIT(0);
/*
- * This logic seems redundant, but separates the value
- * determination from the wire format, and is useful
- * during future maintenance and research.
+ * Send 16bits with M3D/M2D and M1D/M0D bit masks to the
+ * TriggerSelect register, then strobe the LUT write by
+ * passing A3-A0 to TriggerSelect2. Hold RESET during LUT
+ * programming.
*/
wrptr = buf;
- write_u8_inc(&wrptr, tmp[0]);
- write_u8_inc(&wrptr, tmp[1]);
- sigma_write_register(devc, WRITE_TRIGGER_SELECT, buf, wrptr - buf);
- sigma_set_register(devc, WRITE_TRIGGER_SELECT2, 0x30 | i);
+ write_u8_inc(&wrptr, (m3d << 4) | (m2d << 0));
+ write_u8_inc(&wrptr, (m1d << 4) | (m0d << 0));
+ ret = sigma_write_register(devc, WRITE_TRIGGER_SELECT,
+ buf, wrptr - buf);
+ if (ret != SR_OK)
+ return ret;
+ v8 = TRGSEL2_RESET | TRGSEL2_LUT_WRITE |
+ (lut_addr & TRGSEL2_LUT_ADDR_MASK);
+ ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, v8);
+ if (ret != SR_OK)
+ return ret;
}
- /* Send the parameters */
+ /*
+ * Send the parameters. This covers counters and durations.
+ */
wrptr = buf;
- regval = 0;
- regval |= lut->params.selc << 6;
- regval |= lut->params.selpresc << 0;
- write_u8_inc(&wrptr, regval);
- regval = 0;
- regval |= lut->params.selinc << 6;
- regval |= lut->params.selres << 4;
- regval |= lut->params.sela << 2;
- regval |= lut->params.selb << 0;
- write_u8_inc(&wrptr, regval);
- write_u16le_inc(&wrptr, lut->params.cmpb);
- write_u16le_inc(&wrptr, lut->params.cmpa);
- sigma_write_register(devc, WRITE_TRIGGER_SELECT, buf, wrptr - buf);
+ selreg = 0;
+ selreg |= (lut->params.selinc & TRGSEL_SELINC_MASK) << TRGSEL_SELINC_SHIFT;
+ selreg |= (lut->params.selres & TRGSEL_SELRES_MASK) << TRGSEL_SELRES_SHIFT;
+ selreg |= (lut->params.sela & TRGSEL_SELA_MASK) << TRGSEL_SELA_SHIFT;
+ selreg |= (lut->params.selb & TRGSEL_SELB_MASK) << TRGSEL_SELB_SHIFT;
+ selreg |= (lut->params.selc & TRGSEL_SELC_MASK) << TRGSEL_SELC_SHIFT;
+ selreg |= (lut->params.selpresc & TRGSEL_SELPRESC_MASK) << TRGSEL_SELPRESC_SHIFT;
+ write_u16be_inc(&wrptr, selreg);
+ write_u16be_inc(&wrptr, lut->params.cmpb);
+ write_u16be_inc(&wrptr, lut->params.cmpa);
+ ret = sigma_write_register(devc, WRITE_TRIGGER_SELECT, buf, wrptr - buf);
+ if (ret != SR_OK)
+ return ret;
return SR_OK;
}
* mode and sending configuration data. Set D7 and toggle D2, D3, D4
* a few times.
*/
-#define BB_PIN_CCLK (1 << 0) /* D0, CCLK */
-#define BB_PIN_PROG (1 << 1) /* D1, PROG */
-#define BB_PIN_D2 (1 << 2) /* D2, (part of) SUICIDE */
-#define BB_PIN_D3 (1 << 3) /* D3, (part of) SUICIDE */
-#define BB_PIN_D4 (1 << 4) /* D4, (part of) SUICIDE (unused?) */
-#define BB_PIN_INIT (1 << 5) /* D5, INIT, input pin */
-#define BB_PIN_DIN (1 << 6) /* D6, DIN */
-#define BB_PIN_D7 (1 << 7) /* D7, (part of) SUICIDE */
+#define BB_PIN_CCLK BIT(0) /* D0, CCLK */
+#define BB_PIN_PROG BIT(1) /* D1, PROG */
+#define BB_PIN_D2 BIT(2) /* D2, (part of) SUICIDE */
+#define BB_PIN_D3 BIT(3) /* D3, (part of) SUICIDE */
+#define BB_PIN_D4 BIT(4) /* D4, (part of) SUICIDE (unused?) */
+#define BB_PIN_INIT BIT(5) /* D5, INIT, input pin */
+#define BB_PIN_DIN BIT(6) /* D6, DIN */
+#define BB_PIN_D7 BIT(7) /* D7, (part of) SUICIDE */
#define BB_BITRATE (750 * 1000)
#define BB_PINMASK (0xff & ~BB_PIN_INIT)
BB_PIN_CCLK,
BB_PIN_CCLK,
};
- int retries, ret;
+ size_t retries;
+ int ret;
uint8_t data;
/* Section 2. part 1), do the FPGA suicide. */
- sigma_write(devc, suicide, sizeof(suicide));
- sigma_write(devc, suicide, sizeof(suicide));
- sigma_write(devc, suicide, sizeof(suicide));
- sigma_write(devc, suicide, sizeof(suicide));
+ ret = SR_OK;
+ ret |= sigma_write_sr(devc, suicide, sizeof(suicide));
+ ret |= sigma_write_sr(devc, suicide, sizeof(suicide));
+ ret |= sigma_write_sr(devc, suicide, sizeof(suicide));
+ ret |= sigma_write_sr(devc, suicide, sizeof(suicide));
+ if (ret != SR_OK)
+ return SR_ERR_IO;
g_usleep(10 * 1000);
/* Section 2. part 2), pulse PROG. */
- sigma_write(devc, init_array, sizeof(init_array));
+ ret = sigma_write_sr(devc, init_array, sizeof(init_array));
+ if (ret != SR_OK)
+ return ret;
g_usleep(10 * 1000);
- ftdi_usb_purge_buffers(&devc->ftdic);
+ ftdi_usb_purge_buffers(&devc->ftdi.ctx);
- /* Wait until the FPGA asserts INIT_B. */
+ /*
+ * Wait until the FPGA asserts INIT_B. Check in a maximum number
+ * of bursts with a given delay between them. Read as many pin
+ * capture results as the combination of FTDI chip and FTID lib
+ * may provide. Cope with absence of pin capture data in a cycle.
+ * This approach shall result in fast reponse in case of success,
+ * low cost of execution during wait, reliable error handling in
+ * the transport layer, and robust response to failure or absence
+ * of result data (hardware inactivity after stimulus).
+ */
retries = 10;
while (retries--) {
- ret = sigma_read(devc, &data, sizeof(data));
- if (ret < 0)
- return ret;
- if (data & BB_PIN_INIT)
- return SR_OK;
- g_usleep(10 * 1000);
+ do {
+ ret = sigma_read_raw(devc, &data, sizeof(data));
+ if (ret < 0)
+ return SR_ERR_IO;
+ if (ret == sizeof(data) && (data & BB_PIN_INIT))
+ return SR_OK;
+ } while (ret == sizeof(data));
+ if (retries)
+ g_usleep(10 * 1000);
}
return SR_ERR_TIMEOUT;
*/
static int sigma_fpga_init_la(struct dev_context *devc)
{
- uint8_t buf[16], *wrptr;
+ uint8_t buf[20], *wrptr;
uint8_t data_55, data_aa, mode;
uint8_t result[3];
const uint8_t *rdptr;
wrptr = buf;
/* Read ID register. */
- write_u8_inc(&wrptr, REG_ADDR_LOW | (READ_ID & 0xf));
- write_u8_inc(&wrptr, REG_ADDR_HIGH | (READ_ID >> 4));
+ write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(READ_ID));
+ write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(READ_ID));
write_u8_inc(&wrptr, REG_READ_ADDR);
/* Write 0x55 to scratch register, read back. */
data_55 = 0x55;
- write_u8_inc(&wrptr, REG_ADDR_LOW | (WRITE_TEST & 0xf));
- write_u8_inc(&wrptr, REG_DATA_LOW | (data_55 & 0xf));
- write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | (data_55 >> 4));
+ write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(WRITE_TEST));
+ write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(WRITE_TEST));
+ write_u8_inc(&wrptr, REG_DATA_LOW | LO4(data_55));
+ write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | HI4(data_55));
write_u8_inc(&wrptr, REG_READ_ADDR);
/* Write 0xaa to scratch register, read back. */
data_aa = 0xaa;
- write_u8_inc(&wrptr, REG_ADDR_LOW | (WRITE_TEST & 0xf));
- write_u8_inc(&wrptr, REG_DATA_LOW | (data_aa & 0xf));
- write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | (data_aa >> 4));
+ write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(WRITE_TEST));
+ write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(WRITE_TEST));
+ write_u8_inc(&wrptr, REG_DATA_LOW | LO4(data_aa));
+ write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | HI4(data_aa));
write_u8_inc(&wrptr, REG_READ_ADDR);
/* Initiate SDRAM initialization in mode register. */
mode = WMR_SDRAMINIT;
- write_u8_inc(&wrptr, REG_ADDR_LOW | (WRITE_MODE & 0xf));
- write_u8_inc(&wrptr, REG_DATA_LOW | (mode & 0xf));
- write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | (mode >> 4));
+ write_u8_inc(&wrptr, REG_ADDR_LOW | LO4(WRITE_MODE));
+ write_u8_inc(&wrptr, REG_ADDR_HIGH | HI4(WRITE_MODE));
+ write_u8_inc(&wrptr, REG_DATA_LOW | LO4(mode));
+ write_u8_inc(&wrptr, REG_DATA_HIGH_WRITE | HI4(mode));
/*
* Send the command sequence which contains 3 READ requests.
* Expect to see the corresponding 3 response bytes.
*/
- sigma_write(devc, buf, wrptr - buf);
- ret = sigma_read(devc, result, ARRAY_SIZE(result));
- if (ret != ARRAY_SIZE(result)) {
- sr_err("Insufficient start response length.");
+ ret = sigma_write_sr(devc, buf, wrptr - buf);
+ if (ret != SR_OK) {
+ sr_err("Could not request LA start response.");
+ return ret;
+ }
+ ret = sigma_read_sr(devc, result, ARRAY_SIZE(result));
+ if (ret != SR_OK) {
+ sr_err("Could not receive LA start response.");
return SR_ERR_IO;
}
rdptr = result;
* by the caller of this function.
*/
static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name,
- uint8_t **bb_cmd, gsize *bb_cmd_size)
+ uint8_t **bb_cmd, size_t *bb_cmd_size)
{
uint8_t *firmware;
size_t file_size;
bb_size = file_size * 8 * 2;
bb_stream = g_try_malloc(bb_size);
if (!bb_stream) {
- sr_err("%s: Failed to allocate bitbang stream", __func__);
+ sr_err("Memory allocation failed during firmware upload.");
g_free(firmware);
return SR_ERR_MALLOC;
}
devc->state.state = SIGMA_CONFIG;
/* Set the cable to bitbang mode. */
- ret = ftdi_set_bitmode(&devc->ftdic, BB_PINMASK, BITMODE_BITBANG);
+ ret = ftdi_set_bitmode(&devc->ftdi.ctx, BB_PINMASK, BITMODE_BITBANG);
if (ret < 0) {
- sr_err("ftdi_set_bitmode failed: %s",
- ftdi_get_error_string(&devc->ftdic));
+ sr_err("Could not setup cable mode for upload: %s",
+ ftdi_get_error_string(&devc->ftdi.ctx));
return SR_ERR;
}
- ret = ftdi_set_baudrate(&devc->ftdic, BB_BITRATE);
+ ret = ftdi_set_baudrate(&devc->ftdi.ctx, BB_BITRATE);
if (ret < 0) {
- sr_err("ftdi_set_baudrate failed: %s",
- ftdi_get_error_string(&devc->ftdic));
+ sr_err("Could not setup bitrate for upload: %s",
+ ftdi_get_error_string(&devc->ftdi.ctx));
return SR_ERR;
}
/* Initiate FPGA configuration mode. */
ret = sigma_fpga_init_bitbang(devc);
- if (ret)
+ if (ret) {
+ sr_err("Could not initiate firmware upload to hardware");
return ret;
+ }
/* Prepare wire format of the firmware image. */
ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size);
if (ret != SR_OK) {
- sr_err("Could not prepare file %s for download.", firmware);
+ sr_err("Could not prepare file %s for upload.", firmware);
return ret;
}
/* Write the FPGA netlist to the cable. */
sr_info("Uploading firmware file '%s'.", firmware);
- sigma_write(devc, buf, buf_size);
-
+ ret = sigma_write_sr(devc, buf, buf_size);
g_free(buf);
+ if (ret != SR_OK) {
+ sr_err("Could not upload firmware file '%s'.", firmware);
+ return ret;
+ }
/* Leave bitbang mode and discard pending input data. */
- ret = ftdi_set_bitmode(&devc->ftdic, 0, BITMODE_RESET);
+ ret = ftdi_set_bitmode(&devc->ftdi.ctx, 0, BITMODE_RESET);
if (ret < 0) {
- sr_err("ftdi_set_bitmode failed: %s",
- ftdi_get_error_string(&devc->ftdic));
+ sr_err("Could not setup cable mode after upload: %s",
+ ftdi_get_error_string(&devc->ftdi.ctx));
return SR_ERR;
}
- ftdi_usb_purge_buffers(&devc->ftdic);
- while (sigma_read(devc, &pins, sizeof(pins)) > 0)
+ ftdi_usb_purge_buffers(&devc->ftdi.ctx);
+ while (sigma_read_raw(devc, &pins, sizeof(pins)) > 0)
;
/* Initialize the FPGA for logic-analyzer mode. */
ret = sigma_fpga_init_la(devc);
- if (ret != SR_OK)
+ if (ret != SR_OK) {
+ sr_err("Hardware response after firmware upload failed.");
return ret;
+ }
/* Keep track of successful firmware download completion. */
devc->state.state = SIGMA_IDLE;
uint64_t worst_cluster_time_ms;
uint64_t count_msecs, acquire_msecs;
- sr_sw_limits_init(&devc->acq_limits);
+ sr_sw_limits_init(&devc->limit.acquire);
/* Get sample count limit, convert to msecs. */
- ret = sr_sw_limits_config_get(&devc->cfg_limits,
+ ret = sr_sw_limits_config_get(&devc->limit.config,
SR_CONF_LIMIT_SAMPLES, &data);
if (ret != SR_OK)
return ret;
g_variant_unref(data);
count_msecs = 0;
if (user_count)
- count_msecs = 1000 * user_count / devc->samplerate + 1;
+ count_msecs = 1000 * user_count / devc->clock.samplerate + 1;
/* Get time limit, which is in msecs. */
- ret = sr_sw_limits_config_get(&devc->cfg_limits,
+ ret = sr_sw_limits_config_get(&devc->limit.config,
SR_CONF_LIMIT_MSEC, &data);
if (ret != SR_OK)
return ret;
return SR_OK;
/* Add some slack, and use that timeout for acquisition. */
- worst_cluster_time_ms = 1000 * 65536 / devc->samplerate;
+ worst_cluster_time_ms = 1000 * 65536 / devc->clock.samplerate;
acquire_msecs += 2 * worst_cluster_time_ms;
data = g_variant_new_uint64(acquire_msecs);
- ret = sr_sw_limits_config_set(&devc->acq_limits,
+ ret = sr_sw_limits_config_set(&devc->limit.acquire,
SR_CONF_LIMIT_MSEC, data);
g_variant_unref(data);
if (ret != SR_OK)
return ret;
- sr_sw_limits_acquisition_start(&devc->acq_limits);
+ sr_sw_limits_acquisition_start(&devc->limit.acquire);
return SR_OK;
}
return SR_ERR_ARG;
}
+/* Gets called at probe time. Can seed software settings from hardware state. */
+SR_PRIV int sigma_fetch_hw_config(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc;
+ int ret;
+ uint8_t regaddr, regval;
+
+ devc = sdi->priv;
+ if (!devc)
+ return SR_ERR_ARG;
+
+ /* Seed configuration values from defaults. */
+ devc->firmware_idx = SIGMA_FW_NONE;
+ devc->clock.samplerate = samplerates[0];
+
+ /* TODO
+ * Ideally the device driver could retrieve recently stored
+ * details from hardware registers, thus re-use user specified
+ * configuration values across sigrok sessions. Which could
+ * avoid repeated expensive though unnecessary firmware uploads,
+ * improve performance and usability. Unfortunately it appears
+ * that the registers range which is documented as available for
+ * application use keeps providing 0xff data content. At least
+ * with the netlist version which ships with sigrok. The same
+ * was observed with unused registers in the first page.
+ */
+ return SR_ERR_NA;
+
+ /* This is for research, currently does not work yet. */
+ ret = sigma_check_open(sdi);
+ regaddr = 16;
+ regaddr = 14;
+ ret = sigma_set_register(devc, regaddr, 'F');
+ ret = sigma_get_register(devc, regaddr, ®val);
+ sr_warn("%s() reg[%u] val[%u] rc[%d]", __func__, regaddr, regval, ret);
+ ret = sigma_check_close(devc);
+ return ret;
+}
+
+/* Gets called after successful (volatile) hardware configuration. */
+SR_PRIV int sigma_store_hw_config(const struct sr_dev_inst *sdi)
+{
+ /* TODO See above, registers seem to not hold written data. */
+ (void)sdi;
+ return SR_ERR_NA;
+}
+
SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
struct drv_context *drvc;
uint64_t samplerate;
int ret;
- int num_channels;
+ size_t num_channels;
devc = sdi->priv;
drvc = sdi->driver->context;
/* Accept any caller specified rate which the hardware supports. */
- ret = sigma_normalize_samplerate(devc->samplerate, &samplerate);
+ ret = sigma_normalize_samplerate(devc->clock.samplerate, &samplerate);
if (ret != SR_OK)
return ret;
devc->samples_per_event = 16 / devc->num_channels;
}
+ /*
+ * Store the firmware type and most recently configured samplerate
+ * in hardware, such that subsequent sessions can start from there.
+ * This is a "best effort" approach. Failure is non-fatal.
+ */
+ if (ret == SR_OK)
+ (void)sigma_store_hw_config(sdi);
+
return ret;
}
if (!buffer->sample_data)
return SR_ERR_MALLOC;
buffer->write_pointer = buffer->sample_data;
- sr_sw_limits_init(&devc->feed_limits);
+ sr_sw_limits_init(&devc->limit.submit);
buffer->sdi = sdi;
memset(&buffer->logic, 0, sizeof(buffer->logic));
GVariant *data;
uint64_t total;
- limits = &devc->feed_limits;
+ limits = &devc->limit.submit;
- ret = sr_sw_limits_config_get(&devc->cfg_limits,
+ ret = sr_sw_limits_config_get(&devc->limit.config,
SR_CONF_LIMIT_SAMPLES, &data);
if (ret != SR_OK)
return ret;
int ret;
buffer = devc->buffer;
- limits = &devc->feed_limits;
+ limits = &devc->limit.submit;
if (sr_sw_limits_check(limits))
count = 0;
struct sr_trigger_stage *stage;
struct sr_trigger_match *match;
const GSList *l, *m;
- int channelbit, trigger_set;
+ uint16_t channelbit;
+ size_t trigger_set;
devc = sdi->priv;
- memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
- if (!(trigger = sr_session_trigger_get(sdi->session)))
+ memset(&devc->trigger, 0, sizeof(devc->trigger));
+ devc->use_triggers = FALSE;
+ trigger = sr_session_trigger_get(sdi->session);
+ if (!trigger)
+ return SR_OK;
+
+ if (!ASIX_SIGMA_WITH_TRIGGER) {
+ sr_warn("Trigger support is not implemented. Ignoring the spec.");
return SR_OK;
+ }
trigger_set = 0;
for (l = trigger->stages; l; l = l->next) {
/* Ignore disabled channels with a trigger. */
if (!match->channel->enabled)
continue;
- channelbit = 1 << match->channel->index;
- if (devc->samplerate >= SR_MHZ(100)) {
+ channelbit = BIT(match->channel->index);
+ if (devc->clock.samplerate >= SR_MHZ(100)) {
/* Fast trigger support. */
if (trigger_set) {
- sr_err("Only a single pin trigger is "
- "supported in 100 and 200MHz mode.");
+ sr_err("100/200MHz modes limited to single trigger pin.");
return SR_ERR;
}
if (match->match == SR_TRIGGER_FALLING) {
} else if (match->match == SR_TRIGGER_RISING) {
devc->trigger.risingmask |= channelbit;
} else {
- sr_err("Only rising/falling trigger is "
- "supported in 100 and 200MHz mode.");
+ sr_err("100/200MHz modes limited to edge trigger.");
return SR_ERR;
}
* does not permit ORed triggers.
*/
if (trigger_set > 1) {
- sr_err("Only 1 rising/falling trigger is supported.");
+ sr_err("Limited to 1 edge trigger.");
return SR_ERR;
}
}
}
}
+ /* Keep track whether triggers are involved during acquisition. */
+ devc->use_triggers = TRUE;
+
return SR_OK;
}
struct sigma_trigger *t)
{
const uint8_t *rdptr;
- int i;
+ size_t i;
uint16_t sample;
rdptr = samples;
* See the previous get_trigger_offset() implementation. This
* code needs to get re-used here.
*/
- (void)devc;
+ if (!devc->use_triggers)
+ return FALSE;
+
(void)sample;
(void)get_trigger_offset;
{
struct sigma_state *ss;
uint16_t tsdiff, ts, sample, item16;
- unsigned int i;
+ size_t count;
+ size_t evt;
if (!devc->use_triggers || !ASIX_SIGMA_WITH_TRIGGER)
triggered = FALSE;
ts = sigma_dram_cluster_ts(dram_cluster);
tsdiff = ts - ss->lastts;
if (tsdiff > 0) {
- size_t count;
sample = ss->lastsample;
count = tsdiff * devc->samples_per_event;
(void)check_and_submit_sample(devc, sample, count, FALSE);
* buffer depth is neither assumed nor required here.
*/
sample = 0;
- for (i = 0; i < events_in_cluster; i++) {
- item16 = sigma_dram_cluster_data(dram_cluster, i);
- if (devc->samplerate == SR_MHZ(200)) {
+ for (evt = 0; evt < events_in_cluster; evt++) {
+ item16 = sigma_dram_cluster_data(dram_cluster, evt);
+ if (devc->clock.samplerate == SR_MHZ(200)) {
sample = sigma_deinterlace_200mhz_data(item16, 0);
check_and_submit_sample(devc, sample, 1, triggered);
sample = sigma_deinterlace_200mhz_data(item16, 1);
check_and_submit_sample(devc, sample, 1, triggered);
sample = sigma_deinterlace_200mhz_data(item16, 3);
check_and_submit_sample(devc, sample, 1, triggered);
- } else if (devc->samplerate == SR_MHZ(100)) {
+ } else if (devc->clock.samplerate == SR_MHZ(100)) {
sample = sigma_deinterlace_100mhz_data(item16, 0);
check_and_submit_sample(devc, sample, 1, triggered);
sample = sigma_deinterlace_100mhz_data(item16, 1);
size_t events_in_line, size_t trigger_event)
{
struct sigma_dram_cluster *dram_cluster;
- unsigned int clusters_in_line;
- unsigned int events_in_cluster;
- unsigned int i;
- uint32_t trigger_cluster;
+ size_t clusters_in_line;
+ size_t events_in_cluster;
+ size_t cluster;
+ size_t trigger_cluster;
clusters_in_line = events_in_line;
clusters_in_line += EVENTS_PER_CLUSTER - 1;
clusters_in_line /= EVENTS_PER_CLUSTER;
- trigger_cluster = ~0;
/* Check if trigger is in this chunk. */
+ trigger_cluster = ~0UL;
if (trigger_event < EVENTS_PER_ROW) {
- if (devc->samplerate <= SR_MHZ(50)) {
+ if (devc->clock.samplerate <= SR_MHZ(50)) {
trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
trigger_event);
}
}
/* For each full DRAM cluster. */
- for (i = 0; i < clusters_in_line; i++) {
- dram_cluster = &dram_line->cluster[i];
+ for (cluster = 0; cluster < clusters_in_line; cluster++) {
+ dram_cluster = &dram_line->cluster[cluster];
/* The last cluster might not be full. */
- if ((i == clusters_in_line - 1) &&
+ if ((cluster == clusters_in_line - 1) &&
(events_in_line % EVENTS_PER_CLUSTER)) {
events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
} else {
}
sigma_decode_dram_cluster(devc, dram_cluster,
- events_in_cluster, i == trigger_cluster);
+ events_in_cluster, cluster == trigger_cluster);
}
return SR_OK;
struct dev_context *devc;
struct sigma_dram_line *dram_line;
- int bufsz;
uint32_t stoppos, triggerpos;
uint8_t modestatus;
- uint32_t i;
- uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
- uint32_t dl_first_line, dl_line;
- uint32_t dl_events_in_line;
- uint32_t trg_line, trg_event;
+ size_t line_idx;
+ size_t dl_lines_total, dl_lines_curr, dl_lines_done;
+ size_t dl_first_line, dl_line;
+ size_t dl_events_in_line, trigger_event;
+ size_t trg_line, trg_event;
int ret;
devc = sdi->priv;
- dl_events_in_line = EVENTS_PER_ROW;
sr_info("Downloading sample data.");
devc->state.state = SIGMA_DOWNLOAD;
* clusters to DRAM regardless of whether pin state changes) and
* raise the POSTTRIGGERED flag.
*/
- sigma_set_register(devc, WRITE_MODE, WMR_FORCESTOP | WMR_SDRAMWRITEEN);
+ modestatus = WMR_FORCESTOP | WMR_SDRAMWRITEEN;
+ ret = sigma_set_register(devc, WRITE_MODE, modestatus);
+ if (ret != SR_OK)
+ return ret;
do {
- ret = sigma_read_register(devc, READ_MODE,
- &modestatus, sizeof(modestatus));
- if (ret != sizeof(modestatus)) {
- sr_err("Could not poll for post-trigger condition.");
+ ret = sigma_get_register(devc, READ_MODE, &modestatus);
+ if (ret != SR_OK) {
+ sr_err("Could not poll for post-trigger state.");
return FALSE;
}
} while (!(modestatus & RMR_POSTTRIGGERED));
/* Set SDRAM Read Enable. */
- sigma_set_register(devc, WRITE_MODE, WMR_SDRAMREADEN);
-
- /* Get the current position. */
- sigma_read_pos(devc, &stoppos, &triggerpos);
+ ret = sigma_set_register(devc, WRITE_MODE, WMR_SDRAMREADEN);
+ if (ret != SR_OK)
+ return ret;
- /* Check if trigger has fired. */
- ret = sigma_read_register(devc, READ_MODE,
- &modestatus, sizeof(modestatus));
- if (ret != sizeof(modestatus)) {
- sr_err("Could not query trigger hit.");
+ /* Get the current position. Check if trigger has fired. */
+ ret = sigma_read_pos(devc, &stoppos, &triggerpos, &modestatus);
+ if (ret != SR_OK) {
+ sr_err("Could not query capture positions/state.");
return FALSE;
}
- trg_line = ~0;
- trg_event = ~0;
+ if (!devc->use_triggers)
+ triggerpos = ~0;
+ trg_line = ~0UL;
+ trg_event = ~0UL;
if (modestatus & RMR_TRIGGERED) {
trg_line = triggerpos >> ROW_SHIFT;
trg_event = triggerpos & ROW_MASK;
dl_line = dl_first_line + dl_lines_done;
dl_line %= ROW_COUNT;
- bufsz = sigma_read_dram(devc, dl_line, dl_lines_curr,
- (uint8_t *)dram_line);
- /* TODO: Check bufsz. For now, just avoid compiler warnings. */
- (void)bufsz;
+ ret = sigma_read_dram(devc, dl_line, dl_lines_curr,
+ (uint8_t *)dram_line);
+ if (ret != SR_OK)
+ return FALSE;
/* This is the first DRAM line, so find the initial timestamp. */
if (dl_lines_done == 0) {
devc->state.lastsample = 0;
}
- for (i = 0; i < dl_lines_curr; i++) {
- uint32_t trigger_event = ~0;
+ for (line_idx = 0; line_idx < dl_lines_curr; line_idx++) {
/* The last "DRAM line" need not span its full length. */
- if (dl_lines_done + i == dl_lines_total - 1)
+ dl_events_in_line = EVENTS_PER_ROW;
+ if (dl_lines_done + line_idx == dl_lines_total - 1)
dl_events_in_line = stoppos & ROW_MASK;
/* Test if the trigger happened on this line. */
- if (dl_lines_done + i == trg_line)
+ trigger_event = ~0UL;
+ if (dl_lines_done + line_idx == trg_line)
trigger_event = trg_event;
- decode_chunk_ts(devc, dram_line + i,
+ decode_chunk_ts(devc, dram_line + line_idx,
dl_events_in_line, trigger_event);
}
struct dev_context *devc;
devc = sdi->priv;
- if (sr_sw_limits_check(&devc->acq_limits))
+ if (sr_sw_limits_check(&devc->limit.acquire))
return download_capture(sdi);
return TRUE;
}
/* Build a LUT entry used by the trigger functions. */
-static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
+static void build_lut_entry(uint16_t *lut_entry,
+ uint16_t spec_value, uint16_t spec_mask)
{
- int i, j, k, bit;
-
- /* For each quad channel. */
- for (i = 0; i < 4; i++) {
- entry[i] = 0xffff;
-
- /* For each bit in LUT. */
- for (j = 0; j < 16; j++) {
-
- /* For each channel in quad. */
- for (k = 0; k < 4; k++) {
- bit = 1 << (i * 4 + k);
+ size_t quad, bitidx, ch;
+ uint16_t quadmask, bitmask;
+ gboolean spec_value_low, bit_idx_low;
- /* Set bit in entry */
- if ((mask & bit) && ((!(value & bit)) !=
- (!(j & (1 << k)))))
- entry[i] &= ~(1 << j);
+ /*
+ * For each quad-channel-group, for each bit in the LUT (each
+ * bit pattern of the channel signals, aka LUT address), for
+ * each channel in the quad, setup the bit in the LUT entry.
+ *
+ * Start from all-ones in the LUT (true, always matches), then
+ * "pessimize the truthness" for specified conditions.
+ */
+ for (quad = 0; quad < 4; quad++) {
+ lut_entry[quad] = ~0;
+ for (bitidx = 0; bitidx < 16; bitidx++) {
+ for (ch = 0; ch < 4; ch++) {
+ quadmask = BIT(ch);
+ bitmask = quadmask << (quad * 4);
+ if (!(spec_mask & bitmask))
+ continue;
+ /*
+ * This bit is part of the spec. The
+ * condition which gets checked here
+ * (got checked in all implementations
+ * so far) is uncertain. A bit position
+ * in the current index' number(!) is
+ * checked?
+ */
+ spec_value_low = !(spec_value & bitmask);
+ bit_idx_low = !(bitidx & quadmask);
+ if (spec_value_low == bit_idx_low)
+ continue;
+ lut_entry[quad] &= ~BIT(bitidx);
}
}
}
/* Add a logical function to LUT mask. */
static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
- int index, int neg, uint16_t *mask)
+ size_t index, gboolean neg, uint16_t *mask)
{
- int i, j;
- int x[2][2], tmp, a, b, aset, bset, rset;
+ int x[2][2], a, b, aset, bset, rset;
+ size_t bitidx;
- memset(x, 0, 4 * sizeof(int));
+ /*
+ * Beware! The x, a, b, aset, bset, rset variables strictly
+ * require the limited 0..1 range. They are not interpreted
+ * as logically true, instead bit arith is done on them.
+ */
- /* Trigger detect condition. */
+ /* Construct a pattern which detects the condition. */
+ memset(x, 0, sizeof(x));
switch (oper) {
case OP_LEVEL:
x[0][1] = 1;
break;
}
- /* Transpose if neg is set. */
+ /* Transpose the pattern if the condition is negated. */
if (neg) {
+ size_t i, j;
+ int tmp;
+
for (i = 0; i < 2; i++) {
for (j = 0; j < 2; j++) {
tmp = x[i][j];
}
}
- /* Update mask with function. */
- for (i = 0; i < 16; i++) {
- a = (i >> (2 * index + 0)) & 1;
- b = (i >> (2 * index + 1)) & 1;
+ /* Update the LUT mask with the function's condition. */
+ for (bitidx = 0; bitidx < 16; bitidx++) {
+ a = (bitidx & BIT(2 * index + 0)) ? 1 : 0;
+ b = (bitidx & BIT(2 * index + 1)) ? 1 : 0;
- aset = (*mask >> i) & 1;
+ aset = (*mask & BIT(bitidx)) ? 1 : 0;
bset = x[b][a];
- rset = 0;
if (func == FUNC_AND || func == FUNC_NAND)
rset = aset & bset;
else if (func == FUNC_OR || func == FUNC_NOR)
rset = aset | bset;
else if (func == FUNC_XOR || func == FUNC_NXOR)
rset = aset ^ bset;
+ else
+ rset = 0;
if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
- rset = !rset;
-
- *mask &= ~(1 << i);
+ rset = 1 - rset;
if (rset)
- *mask |= 1 << i;
+ *mask |= BIT(bitidx);
+ else
+ *mask &= ~BIT(bitidx);
}
}
SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc,
struct triggerlut *lut)
{
- int i,j;
- uint16_t masks[2] = { 0, 0 };
+ uint16_t masks[2];
+ size_t bitidx, condidx;
+ uint16_t value, mask;
- memset(lut, 0, sizeof(struct triggerlut));
+ /* Setup something that "won't match" in the absence of a spec. */
+ memset(lut, 0, sizeof(*lut));
+ if (!devc->use_triggers)
+ return SR_OK;
- /* Constant for simple triggers. */
+ /* Start assuming simple triggers. Edges are handled below. */
lut->m4 = 0xa000;
-
- /* Value/mask trigger support. */
- build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
- lut->m2d);
-
- /* Rise/fall trigger support. */
- for (i = 0, j = 0; i < 16; i++) {
- if (devc->trigger.risingmask & (1 << i) ||
- devc->trigger.fallingmask & (1 << i))
- masks[j++] = 1 << i;
+ lut->m3q = 0xffff;
+
+ /* Process value/mask triggers. */
+ value = devc->trigger.simplevalue;
+ mask = devc->trigger.simplemask;
+ build_lut_entry(lut->m2d, value, mask);
+
+ /* Scan for and process rise/fall triggers. */
+ memset(&masks, 0, sizeof(masks));
+ condidx = 0;
+ for (bitidx = 0; bitidx < 16; bitidx++) {
+ mask = BIT(bitidx);
+ value = devc->trigger.risingmask | devc->trigger.fallingmask;
+ if (!(value & mask))
+ continue;
+ if (condidx == 0)
+ build_lut_entry(lut->m0d, mask, mask);
+ if (condidx == 1)
+ build_lut_entry(lut->m1d, mask, mask);
+ masks[condidx++] = mask;
+ if (condidx == ARRAY_SIZE(masks))
+ break;
}
- build_lut_entry(masks[0], masks[0], lut->m0d);
- build_lut_entry(masks[1], masks[1], lut->m1d);
-
- /* Add glue logic */
+ /* Add glue logic for rise/fall triggers. */
if (masks[0] || masks[1]) {
- /* Transition trigger. */
+ lut->m3q = 0;
if (masks[0] & devc->trigger.risingmask)
- add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
+ add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3q);
if (masks[0] & devc->trigger.fallingmask)
- add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
+ add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3q);
if (masks[1] & devc->trigger.risingmask)
- add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
+ add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3q);
if (masks[1] & devc->trigger.fallingmask)
- add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
- } else {
- /* Only value/mask trigger. */
- lut->m3 = 0xffff;
+ add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3q);
}
/* Triggertype: event. */
- lut->params.selres = 3;
+ lut->params.selres = TRGSEL_SELCODE_NEVER;
+ lut->params.selinc = TRGSEL_SELCODE_LEVEL;
+ lut->params.sela = 0; /* Counter >= CMPA && LEVEL */
+ lut->params.cmpa = 0; /* Count 0 -> 1 already triggers. */
return SR_OK;
}
projects / libsigrok.git / blobdiff