SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
+#if ASIX_SIGMA_WITH_TRIGGER
SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
+#endif
};
+#if ASIX_SIGMA_WITH_TRIGGER
static const int32_t trigger_matches[] = {
SR_TRIGGER_ZERO,
SR_TRIGGER_ONE,
SR_TRIGGER_RISING,
SR_TRIGGER_FALLING,
};
-
+#endif
static int dev_clear(const struct sr_dev_driver *di)
{
sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
devc->cur_samplerate = samplerates[0];
- devc->period_ps = 0;
devc->limit_msec = 0;
devc->limit_samples = 0;
devc->cur_firmware = -1;
devc = sdi->priv;
- /* Make sure it's an ASIX SIGMA. */
if ((ret = ftdi_usb_open_desc(&devc->ftdic,
- USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
-
- sr_err("ftdi_usb_open failed: %s",
- ftdi_get_error_string(&devc->ftdic));
-
- return 0;
+ USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
+ sr_err("Failed to open device (%d): %s.",
+ ret, ftdi_get_error_string(&devc->ftdic));
+ return SR_ERR;
}
- sdi->status = SR_ST_ACTIVE;
-
return SR_OK;
}
devc = sdi->priv;
- /* TODO */
- if (sdi->status == SR_ST_ACTIVE)
- ftdi_usb_close(&devc->ftdic);
+ ftdi_usb_close(&devc->ftdic);
sdi->status = SR_ST_INACTIVE;
case SR_CONF_LIMIT_SAMPLES:
*data = g_variant_new_uint64(devc->limit_samples);
break;
+#if ASIX_SIGMA_WITH_TRIGGER
case SR_CONF_CAPTURE_RATIO:
*data = g_variant_new_uint64(devc->capture_ratio);
break;
+#endif
default:
return SR_ERR_NA;
}
(void)cg;
- if (sdi->status != SR_ST_ACTIVE)
- return SR_ERR_DEV_CLOSED;
-
devc = sdi->priv;
ret = SR_OK;
devc->limit_samples = tmp;
devc->limit_msec = sigma_limit_samples_to_msec(devc, tmp);
break;
+#if ASIX_SIGMA_WITH_TRIGGER
case SR_CONF_CAPTURE_RATIO:
tmp = g_variant_get_uint64(data);
- if (tmp <= 100)
- devc->capture_ratio = tmp;
- else
- ret = SR_ERR;
+ if (tmp > 100)
+ return SR_ERR;
+ devc->capture_ratio = tmp;
break;
+#endif
default:
ret = SR_ERR_NA;
}
g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
*data = g_variant_builder_end(&gvb);
break;
+#if ASIX_SIGMA_WITH_TRIGGER
case SR_CONF_TRIGGER_MATCH:
*data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
trigger_matches, ARRAY_SIZE(trigger_matches),
sizeof(int32_t));
break;
+#endif
default:
return SR_ERR_NA;
}
{
struct dev_context *devc;
struct clockselect_50 clockselect;
- int frac, triggerpin, ret;
- uint8_t triggerselect = 0;
+ int triggerpin, ret;
+ uint8_t triggerselect;
struct triggerinout triggerinout_conf;
struct triggerlut lut;
-
- if (sdi->status != SR_ST_ACTIVE)
- return SR_ERR_DEV_CLOSED;
+ uint8_t regval;
+ uint8_t clock_bytes[sizeof(clockselect)];
+ size_t clock_idx;
devc = sdi->priv;
/* Enter trigger programming mode. */
sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
- /* 100 and 200 MHz mode. */
+ triggerselect = 0;
if (devc->cur_samplerate >= SR_MHZ(100)) {
+ /* 100 and 200 MHz mode. */
sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
/* Find which pin to trigger on from mask. */
if (devc->trigger.fallingmask)
triggerselect |= 1 << 3;
- /* All other modes. */
} else if (devc->cur_samplerate <= SR_MHZ(50)) {
+ /* All other modes. */
sigma_build_basic_trigger(&lut, devc);
sigma_write_trigger_lut(&lut, devc);
sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
/* Set clock select register. */
- if (devc->cur_samplerate == SR_MHZ(200))
+ clockselect.async = 0;
+ clockselect.fraction = 1 - 1; /* Divider 1. */
+ clockselect.disabled_channels = 0x0000; /* All channels enabled. */
+ if (devc->cur_samplerate == SR_MHZ(200)) {
/* Enable 4 channels. */
- sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
- else if (devc->cur_samplerate == SR_MHZ(100))
+ clockselect.disabled_channels = 0xf0ff;
+ } else if (devc->cur_samplerate == SR_MHZ(100)) {
/* Enable 8 channels. */
- sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
- else {
+ clockselect.disabled_channels = 0x00ff;
+ } else {
/*
- * 50 MHz mode (or fraction thereof). Any fraction down to
- * 50 MHz / 256 can be used, but is not supported by sigrok API.
+ * 50 MHz mode, or fraction thereof. The 50MHz reference
+ * can get divided by any integer in the range 1 to 256.
+ * Divider minus 1 gets written to the hardware.
+ * (The driver lists a discrete set of sample rates, but
+ * all of them fit the above description.)
*/
- frac = SR_MHZ(50) / devc->cur_samplerate - 1;
-
- clockselect.async = 0;
- clockselect.fraction = frac;
- clockselect.disabled_channels = 0;
-
- sigma_write_register(WRITE_CLOCK_SELECT,
- (uint8_t *) &clockselect,
- sizeof(clockselect), devc);
+ clockselect.fraction = SR_MHZ(50) / devc->cur_samplerate - 1;
}
+ clock_idx = 0;
+ clock_bytes[clock_idx++] = clockselect.async;
+ clock_bytes[clock_idx++] = clockselect.fraction;
+ clock_bytes[clock_idx++] = clockselect.disabled_channels & 0xff;
+ clock_bytes[clock_idx++] = clockselect.disabled_channels >> 8;
+ sigma_write_register(WRITE_CLOCK_SELECT, clock_bytes, clock_idx, devc);
/* Setup maximum post trigger time. */
sigma_set_register(WRITE_POST_TRIGGER,
(devc->capture_ratio * 255) / 100, devc);
/* Start acqusition. */
- gettimeofday(&devc->start_tv, 0);
- sigma_set_register(WRITE_MODE, 0x0d, devc);
+ devc->start_time = g_get_monotonic_time();
+ regval = WMR_TRGRES | WMR_SDRAMWRITEEN;
+#if ASIX_SIGMA_WITH_TRIGGER
+ regval |= WMR_TRGEN;
+#endif
+ sigma_set_register(WRITE_MODE, regval, devc);
std_session_send_df_header(sdi);
projects / libsigrok.git / blobdiff