asix-sigma: sync FPGA register names with documentation

[libsigrok.git] / src / hardware / asix-sigma / api.c

diff --git a/src/hardware/asix-sigma/api.c b/src/hardware/asix-sigma/api.c
index 40f6cd001b57bd375374f0c3d41aba2555f1c612..15c222521aca1c7d6fd0f0ae01ec10f55a694960 100644 (file)
--- a/src/hardware/asix-sigma/api.c
+++ b/src/hardware/asix-sigma/api.c
@@ -412,12 +412,12 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
        }
 
        /* Enter trigger programming mode. */
-       sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
+       sigma_set_register(WRITE_TRIGGER_SELECT2, 0x20, devc);
 
        triggerselect = 0;
        if (devc->cur_samplerate >= SR_MHZ(100)) {
                /* 100 and 200 MHz mode. */
-               sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
+               sigma_set_register(WRITE_TRIGGER_SELECT2, 0x81, devc);
 
                /* Find which pin to trigger on from mask. */
                for (triggerpin = 0; triggerpin < 8; triggerpin++)
@@ -451,7 +451,7 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
                             sizeof(struct triggerinout), devc);
 
        /* Go back to normal mode. */
-       sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
+       sigma_set_register(WRITE_TRIGGER_SELECT2, triggerselect, devc);
 
        /* Set clock select register. */
        clockselect.async = 0;