Skip analog probes in logic-only output formats.

[libsigrok.git] / output / vcd.c

diff --git a/output/vcd.c b/output/vcd.c
index d1526c1b6587e076732b343b07a9c81c692df156..44a12dec37a8c2e2265ea499d4410d61443d5ac3 100644 (file)
--- a/output/vcd.c
+++ b/output/vcd.c
@@ -62,6 +62,8 @@ static int init(struct sr_output *o)
 
        for (l = o->sdi->probes; l; l = l->next) {
                probe = l->data;
+               if (probe->type != SR_PROBE_LOGIC)
+                       continue;
                if (!probe->enabled)
                        continue;
                ctx->probeindices = g_array_append_val(
@@ -124,6 +126,8 @@ static int init(struct sr_output *o)
        /* Wires / channels */
        for (i = 0, l = o->sdi->probes; l; l = l->next, i++) {
                probe = l->data;
+               if (probe->type != SR_PROBE_LOGIC)
+                       continue;
                if (!probe->enabled)
                        continue;
                g_string_append_printf(ctx->header, "$var wire 1 %c %s $end\n",