saleae-logic16: Add voltage threshold conf.

[libsigrok.git] / libsigrok.h

diff --git a/libsigrok.h b/libsigrok.h
index 2f7047a426119ef1a4a909792c8244e138e46cce..a93a07ea3a4745218ce74c167117f254d3df75a8 100644 (file)
--- a/libsigrok.h
+++ b/libsigrok.h
@@ -142,6 +142,7 @@ enum {
        SR_T_RATIONAL_VOLT,
        SR_T_KEYVALUE,
        SR_T_UINT64_RANGE,
+       SR_T_DOUBLE_RANGE,
 };
 
 /** Value for sr_datafeed_packet.type. */
@@ -681,6 +682,9 @@ enum {
        /** Min hold mode. */
        SR_CONF_HOLD_MIN,
 
+       /** Logic low-high threshold range. */
+       SR_CONF_VOLTAGE_THRESHOLD,
+
        /*--- Special stuff -------------------------------------------------*/
 
        /** Scan options supported by the driver. */