Always interleave analog data with all enabled probes.

[libsigrok.git] / hardware / agilent-dmm / sched.c

diff --git a/hardware/agilent-dmm/sched.c b/hardware/agilent-dmm/sched.c
index 67c2a1b66330d01f29a7edc2c927ff192065216e..d7d720d3227af38c87efc2ffb9eaf46cb4a5350d 100644 (file)
--- a/hardware/agilent-dmm/sched.c
+++ b/hardware/agilent-dmm/sched.c
@@ -263,6 +263,7 @@ static int recv_fetc(const struct sr_dev_inst *sdi, GMatchInfo *match)
        analog.mq = devc->cur_mq;
        analog.unit = devc->cur_unit;
        analog.mqflags = devc->cur_mqflags;
+       analog.probes = sdi->probes;
        analog.num_samples = 1;
        analog.data = &fvalue;
        packet.type = SR_DF_ANALOG;