asix-sigma: Adjust clock configuration upon acquisition start

[libsigrok.git] / Makefile.am

diff --git a/Makefile.am b/Makefile.am
index 8114f660dc921b5ac5f6d58916482b1b15017519..731726355ad4b63bcd04e494d4eac4190f39e532 100644 (file)
--- a/Makefile.am
+++ b/Makefile.am
@@ -376,6 +376,12 @@ src_libdrivers_la_SOURCES += \
        src/hardware/lecroy-logicstudio/protocol.c \
        src/hardware/lecroy-logicstudio/api.c
 endif
+if HW_LECROY_XSTREAM
+src_libdrivers_la_SOURCES += \
+       src/hardware/lecroy-xstream/protocol.h \
+       src/hardware/lecroy-xstream/protocol.c \
+       src/hardware/lecroy-xstream/api.c
+endif
 if HW_MANSON_HCS_3XXX
 src_libdrivers_la_SOURCES += \
        src/hardware/manson-hcs-3xxx/protocol.h \
@@ -430,6 +436,12 @@ src_libdrivers_la_SOURCES += \
        src/hardware/rigol-ds/protocol.c \
        src/hardware/rigol-ds/api.c
 endif
+if HW_ROHDE_SCHWARZ_SME_0X
+src_libdrivers_la_SOURCES += \
+       src/hardware/rohde-schwarz-sme-0x/protocol.h \
+       src/hardware/rohde-schwarz-sme-0x/protocol.c \
+       src/hardware/rohde-schwarz-sme-0x/api.c
+endif
 if HW_SALEAE_LOGIC16
 src_libdrivers_la_SOURCES += \
        src/hardware/saleae-logic16/protocol.h \
@@ -648,7 +660,7 @@ PDIR = bindings/python
 PDOC_START = bindings/python/sigrok/core/doc_start.i
 PDOC_END = bindings/python/sigrok/core/doc_end.i
 
-setup_vars = VERSION='$(PACKAGE_VERSION)' CC='$(CC)' CXX='$(CXX)' CFLAGS='$(CFLAGS) $(SR_WXXFLAGS) $(PYSIGROK_CFLAGS)' CXXFLAGS='$(CXXFLAGS) $(SR_WXXFLAGS) $(PYSIGROK_CFLAGS)' LDADD='$(PYSIGROK_LIBS)'
+setup_vars = VERSION='$(PACKAGE_VERSION)' CC='$(CXX)' CXX='$(CXX)' CFLAGS='$(CXXFLAGS) $(SR_WXXFLAGS) $(PYSIGROK_CFLAGS)' CXXFLAGS='$(CXXFLAGS) $(SR_WXXFLAGS) $(PYSIGROK_CFLAGS)' LDADD='$(PYSIGROK_LIBS)'
 setup_quiet = --quiet
 setup_py = $(PYTHON) $(srcdir)/$(PDIR)/setup.py $(setup_vars) $(setup_quiet)