yokogawa-dlm: Integrate driver skeleton

[libsigrok.git] / Makefile.am

diff --git a/Makefile.am b/Makefile.am
index eb72a1468dafd940111fbf63463d4d8c07b6f1e5..3087649cdb93bb5e3fe3dfd12572481543d1418d 100644 (file)
--- a/Makefile.am
+++ b/Makefile.am
@@ -43,10 +43,10 @@ libsigrok_la_SOURCES = \
 
 # Input modules
 libsigrok_la_SOURCES += \
+       src/input/input.c \
        src/input/binary.c \
        src/input/chronovu_la8.c \
        src/input/csv.c \
-       src/input/input.c \
        src/input/vcd.c \
        src/input/wav.c
 
@@ -264,6 +264,12 @@ libsigrok_la_SOURCES += \
        src/hardware/openbench-logic-sniffer/protocol.c \
        src/hardware/openbench-logic-sniffer/api.c
 endif
+if HW_PIPISTRELLO_OLS
+libsigrok_la_SOURCES += \
+       src/hardware/pipistrello-ols/protocol.h \
+       src/hardware/pipistrello-ols/protocol.c \
+       src/hardware/pipistrello-ols/api.c
+endif
 if HW_RIGOL_DS
 libsigrok_la_SOURCES += \
        src/hardware/rigol-ds/protocol.h \
@@ -326,6 +332,14 @@ libsigrok_la_SOURCES += \
        src/hardware/victor-dmm/protocol.c \
        src/hardware/victor-dmm/api.c
 endif
+if HW_YOKOGAWA_DLM
+libsigrok_la_SOURCES += \
+       src/hardware/yokogawa-dlm/protocol.h \
+       src/hardware/yokogawa-dlm/protocol.c \
+       src/hardware/yokogawa-dlm/protocol_wrappers.h \
+       src/hardware/yokogawa-dlm/protocol_wrappers.c \
+       src/hardware/yokogawa-dlm/api.c
+endif
 if HW_ZEROPLUS_LOGIC_CUBE
 libsigrok_la_SOURCES += \
        src/hardware/zeroplus-logic-cube/analyzer.c \
@@ -447,23 +461,24 @@ PDIR = bindings/python
 PDOC = bindings/python/sigrok/core/doc.i
 
 $(PDOC): bindings/swig/doc.py $(CPPXMLDOC)
-       $(AM_V_GEN)python bindings/swig/doc.py python $(CPPXMLDOC) > $@
+       $(AM_V_at)test -d $(PDIR)/sigrok/core || mkdir -p $(PDIR)/sigrok/core
+       $(AM_V_GEN)python $< python $(CPPXMLDOC) > $@
 
 python-build: $(PDIR)/timestamp
 
 python-quietclean:
-       $(AM_V_at)cd $(PDIR) && python setup.py --quiet clean --all 3>&1 1>&2 2>&3 \
+       $(AM_V_at)cd $(PDIR) && python $(abs_srcdir)/$(PDIR)/setup.py --quiet clean --all 3>&1 1>&2 2>&3 \
                | grep -v "can.t clean it"; true
 
 $(PDIR)/timestamp: bindings/cxx/libsigrokxx.la $(PDIR)/sigrok/core/classes.i \
                bindings/swig/classes.i $(PDOC) $(library_include_HEADERS)
        $(AM_V_at)$(MAKE) python-quietclean
-       $(AM_V_GEN)cd $(PDIR) && python setup.py --quiet build 3>&1 1>&2 2>&3 \
+       $(AM_V_GEN)cd $(PDIR) && python $(abs_srcdir)/$(PDIR)/setup.py --quiet build 3>&1 1>&2 2>&3 \
                | grep -v "command line option.*Wstrict-prototypes"; true
        $(AM_V_at)touch $(PDIR)/timestamp
 
 python-install:
-       cd $(PDIR) && python setup.py --quiet install --prefix $(prefix)
+       cd $(PDIR) && python $(abs_srcdir)/$(PDIR)/setup.py --quiet install --prefix $(prefix)
 
 python-clean:
        $(AM_V_at)$(MAKE) python-quietclean
@@ -471,7 +486,7 @@ python-clean:
        $(AM_V_at)rm -rf $(PDIR)/doxy/
 
 python-doc:
-       $(AM_V_at)cd $(PDIR) && doxygen Doxyfile 2>/dev/null
+       $(AM_V_at)cd $(srcdir)/$(PDIR) && BUILDDIR=$(abs_builddir)/$(PDIR)/ doxygen Doxyfile 2>/dev/null
 
 BUILD_EXTRA += python-build
 INSTALL_EXTRA += python-install
@@ -499,6 +514,7 @@ $(JDOC): bindings/swig/doc.py $(CPPXMLDOC)
        $(AM_V_GEN)python $< java $(CPPXMLDOC) > $@
 
 $(JCXX): $(JSWG) $(JDOC) bindings/swig/classes.i $(library_include_HEADERS)
+       $(AM_V_at)make java-clean
        $(AM_V_GEN)swig -c++ -java -package org.sigrok.core.classes \
                -I$(srcdir)/include -I$(srcdir)/bindings/cxx/include -I$(srcdir) -I$(JCLS) -Ibindings/cxx/include -outdir $(JCLS) -o $@ $<