yokogawa-dlm: Integrate driver skeleton

[libsigrok.git] / Makefile.am

diff --git a/Makefile.am b/Makefile.am
index e7b63efb8c648aa0cadff9d6d54194bd34fb2f76..3087649cdb93bb5e3fe3dfd12572481543d1418d 100644 (file)
--- a/Makefile.am
+++ b/Makefile.am
@@ -43,10 +43,10 @@ libsigrok_la_SOURCES = \
 
 # Input modules
 libsigrok_la_SOURCES += \
+       src/input/input.c \
        src/input/binary.c \
        src/input/chronovu_la8.c \
        src/input/csv.c \
-       src/input/input.c \
        src/input/vcd.c \
        src/input/wav.c
 
@@ -332,6 +332,14 @@ libsigrok_la_SOURCES += \
        src/hardware/victor-dmm/protocol.c \
        src/hardware/victor-dmm/api.c
 endif
+if HW_YOKOGAWA_DLM
+libsigrok_la_SOURCES += \
+       src/hardware/yokogawa-dlm/protocol.h \
+       src/hardware/yokogawa-dlm/protocol.c \
+       src/hardware/yokogawa-dlm/protocol_wrappers.h \
+       src/hardware/yokogawa-dlm/protocol_wrappers.c \
+       src/hardware/yokogawa-dlm/api.c
+endif
 if HW_ZEROPLUS_LOGIC_CUBE
 libsigrok_la_SOURCES += \
        src/hardware/zeroplus-logic-cube/analyzer.c \
@@ -506,6 +514,7 @@ $(JDOC): bindings/swig/doc.py $(CPPXMLDOC)
        $(AM_V_GEN)python $< java $(CPPXMLDOC) > $@
 
 $(JCXX): $(JSWG) $(JDOC) bindings/swig/classes.i $(library_include_HEADERS)
+       $(AM_V_at)make java-clean
        $(AM_V_GEN)swig -c++ -java -package org.sigrok.core.classes \
                -I$(srcdir)/include -I$(srcdir)/bindings/cxx/include -I$(srcdir) -I$(JCLS) -Ibindings/cxx/include -outdir $(JCLS) -o $@ $<