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saleae-logic16: Support new bitstream version 1.3 with renumbered registers
[libsigrok.git] / src / hardware / saleae-logic16 / protocol.h
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1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
6 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#ifndef LIBSIGROK_HARDWARE_SALEAE_LOGIC16_PROTOCOL_H
23#define LIBSIGROK_HARDWARE_SALEAE_LOGIC16_PROTOCOL_H
24
25#include <stdint.h>
26#include <glib.h>
27#include "libsigrok.h"
28#include "libsigrok-internal.h"
29
30#define LOG_PREFIX "saleae-logic16"
31
32enum voltage_range {
33 VOLTAGE_RANGE_UNKNOWN,
34 VOLTAGE_RANGE_18_33_V, /* 1.8V and 3.3V logic */
35 VOLTAGE_RANGE_5_V, /* 5V logic */
36};
37
38enum fpga_variant {
39 FPGA_VARIANT_ORIGINAL,
40 FPGA_VARIANT_ORIGINAL_NEW_BITSTREAM,
41 FPGA_VARIANT_MCUPRO /* mcupro clone v4.6 with Actel FPGA */
42};
43
44/** Private, per-device-instance driver context. */
45struct dev_context {
46 /** Distinguishing between original Logic16 and clones */
47 enum fpga_variant fpga_variant;
48
49 /*
50 * Since we can't keep track of a Logic16 device after upgrading
51 * the firmware (it renumerates into a different device address
52 * after the upgrade) this is like a global lock. No device will open
53 * until a proper delay after the last device was upgraded.
54 */
55 int64_t fw_updated;
56
57 /** The currently configured samplerate of the device. */
58 uint64_t cur_samplerate;
59
60 /** Maximum number of samples to capture, if nonzero. */
61 uint64_t limit_samples;
62
63 /** Percent of the samples that should be captured before the trigger. */
64 uint64_t capture_ratio;
65
66 /** The currently configured input voltage of the device. */
67 enum voltage_range cur_voltage_range;
68
69 /** The input voltage selected by the user. */
70 enum voltage_range selected_voltage_range;
71
72 /** Channels to use. */
73 uint16_t cur_channels;
74
75 /* EEPROM data from address 8. */
76 uint8_t eeprom_data[8];
77
78 int64_t sent_samples;
79 int submitted_transfers;
80 int empty_transfer_count;
81 int num_channels;
82 int cur_channel;
83 uint16_t channel_masks[16];
84 uint16_t channel_data[16];
85 uint8_t *convbuffer;
86 size_t convbuffer_size;
87 struct soft_trigger_logic *stl;
88 gboolean trigger_fired;
89
90 void *cb_data;
91 unsigned int num_transfers;
92 struct libusb_transfer **transfers;
93 struct sr_context *ctx;
94
95 const uint8_t *fpga_register_map;
96 const uint8_t *fpga_status_control_bit_map;
97 const uint8_t *fpga_mode_bit_map;
98};
99
100SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
101 uint64_t samplerate, uint16_t channels);
102SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi);
103SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi);
104SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi);
105SR_PRIV void LIBUSB_CALL logic16_receive_transfer(struct libusb_transfer *transfer);
106
107#endif