]> sigrok.org Git - libsigrok.git/blame_incremental - src/hardware/rigol-ds/api.c
projects / libsigrok.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
Change type of SR_CONF keys to uint32_t.
[libsigrok.git] / src / hardware / rigol-ds / api.c
... / ...
CommitLineData
1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2012 Martin Ling <martin-git@earth.li>
5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
6 * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <fcntl.h>
23#include <unistd.h>
24#include <stdlib.h>
25#include <string.h>
26#include <math.h>
27#include <glib.h>
28#include "libsigrok.h"
29#include "libsigrok-internal.h"
30#include "protocol.h"
31
32static const uint32_t hwopts[] = {
33 SR_CONF_CONN,
34 SR_CONF_SERIALCOMM
35};
36
37static const uint32_t hwcaps[] = {
38 SR_CONF_OSCILLOSCOPE,
39 SR_CONF_TIMEBASE,
40 SR_CONF_TRIGGER_SOURCE,
41 SR_CONF_TRIGGER_SLOPE,
42 SR_CONF_HORIZ_TRIGGERPOS,
43 SR_CONF_NUM_TIMEBASE,
44 SR_CONF_LIMIT_FRAMES,
45 SR_CONF_SAMPLERATE,
46};
47
48static const uint32_t analog_hwcaps[] = {
49 SR_CONF_NUM_VDIV,
50 SR_CONF_VDIV,
51 SR_CONF_COUPLING,
52 SR_CONF_DATA_SOURCE,
53};
54
55static const uint64_t timebases[][2] = {
56 /* nanoseconds */
57 { 1, 1000000000 },
58 { 2, 1000000000 },
59 { 5, 1000000000 },
60 { 10, 1000000000 },
61 { 20, 1000000000 },
62 { 50, 1000000000 },
63 { 100, 1000000000 },
64 { 500, 1000000000 },
65 /* microseconds */
66 { 1, 1000000 },
67 { 2, 1000000 },
68 { 5, 1000000 },
69 { 10, 1000000 },
70 { 20, 1000000 },
71 { 50, 1000000 },
72 { 100, 1000000 },
73 { 200, 1000000 },
74 { 500, 1000000 },
75 /* milliseconds */
76 { 1, 1000 },
77 { 2, 1000 },
78 { 5, 1000 },
79 { 10, 1000 },
80 { 20, 1000 },
81 { 50, 1000 },
82 { 100, 1000 },
83 { 200, 1000 },
84 { 500, 1000 },
85 /* seconds */
86 { 1, 1 },
87 { 2, 1 },
88 { 5, 1 },
89 { 10, 1 },
90 { 20, 1 },
91 { 50, 1 },
92 { 100, 1 },
93 { 200, 1 },
94 { 500, 1 },
95 { 1000, 1 },
96};
97
98static const uint64_t vdivs[][2] = {
99 /* microvolts */
100 { 500, 1000000 },
101 /* millivolts */
102 { 1, 1000 },
103 { 2, 1000 },
104 { 5, 1000 },
105 { 10, 1000 },
106 { 20, 1000 },
107 { 50, 1000 },
108 { 100, 1000 },
109 { 200, 1000 },
110 { 500, 1000 },
111 /* volts */
112 { 1, 1 },
113 { 2, 1 },
114 { 5, 1 },
115 { 10, 1 },
116};
117
118#define NUM_TIMEBASE ARRAY_SIZE(timebases)
119#define NUM_VDIV ARRAY_SIZE(vdivs)
120
121static const char *trigger_sources[] = {
122 "CH1",
123 "CH2",
124 "CH3",
125 "CH4",
126 "EXT",
127 "AC Line",
128 "D0",
129 "D1",
130 "D2",
131 "D3",
132 "D4",
133 "D5",
134 "D6",
135 "D7",
136 "D8",
137 "D9",
138 "D10",
139 "D11",
140 "D12",
141 "D13",
142 "D14",
143 "D15",
144};
145
146static const char *trigger_slopes[] = {
147 "r",
148 "f",
149};
150
151static const char *coupling[] = {
152 "AC",
153 "DC",
154 "GND",
155};
156
157/* Do not change the order of entries */
158static const char *data_sources[] = {
159 "Live",
160 "Memory",
161 "Segmented",
162};
163
164enum vendor {
165 RIGOL,
166 AGILENT,
167};
168
169enum series {
170 VS5000,
171 DS1000,
172 DS2000,
173 DS2000A,
174 DSO1000,
175};
176
177/* short name, full name */
178static const struct rigol_ds_vendor supported_vendors[] = {
179 [RIGOL] = {"Rigol", "Rigol Technologies"},
180 [AGILENT] = {"Agilent", "Agilent Technologies"},
181};
182
183#define VENDOR(x) &supported_vendors[x]
184/* vendor, series, protocol, max timebase, min vdiv, number of horizontal divs,
185 * live waveform samples, memory buffer samples */
186static const struct rigol_ds_series supported_series[] = {
187 [VS5000] = {VENDOR(RIGOL), "VS5000", PROTOCOL_V1, FORMAT_RAW,
188 {50, 1}, {2, 1000}, 14, 2048, 0},
189 [DS1000] = {VENDOR(RIGOL), "DS1000", PROTOCOL_V2, FORMAT_IEEE488_2,
190 {50, 1}, {2, 1000}, 12, 600, 1048576},
191 [DS2000] = {VENDOR(RIGOL), "DS2000", PROTOCOL_V3, FORMAT_IEEE488_2,
192 {500, 1}, {2, 1000}, 14, 1400, 14000},
193 [DS2000A] = {VENDOR(RIGOL), "DS2000A", PROTOCOL_V3, FORMAT_IEEE488_2,
194 {1000, 1}, {500, 1000000}, 14, 1400, 14000},
195 [DSO1000] = {VENDOR(AGILENT), "DSO1000", PROTOCOL_V3, FORMAT_IEEE488_2,
196 {50, 1}, {2, 1000}, 12, 600, 20480},
197};
198
199#define SERIES(x) &supported_series[x]
200/* series, model, min timebase, analog channels, digital */
201static const struct rigol_ds_model supported_models[] = {
202 {SERIES(VS5000), "VS5022", {20, 1000000000}, 2, false},
203 {SERIES(VS5000), "VS5042", {10, 1000000000}, 2, false},
204 {SERIES(VS5000), "VS5062", {5, 1000000000}, 2, false},
205 {SERIES(VS5000), "VS5102", {2, 1000000000}, 2, false},
206 {SERIES(VS5000), "VS5202", {2, 1000000000}, 2, false},
207 {SERIES(VS5000), "VS5022D", {20, 1000000000}, 2, true},
208 {SERIES(VS5000), "VS5042D", {10, 1000000000}, 2, true},
209 {SERIES(VS5000), "VS5062D", {5, 1000000000}, 2, true},
210 {SERIES(VS5000), "VS5102D", {2, 1000000000}, 2, true},
211 {SERIES(VS5000), "VS5202D", {2, 1000000000}, 2, true},
212 {SERIES(DS1000), "DS1052E", {5, 1000000000}, 2, false},
213 {SERIES(DS1000), "DS1102E", {2, 1000000000}, 2, false},
214 {SERIES(DS1000), "DS1152E", {2, 1000000000}, 2, false},
215 {SERIES(DS1000), "DS1052D", {5, 1000000000}, 2, true},
216 {SERIES(DS1000), "DS1102D", {2, 1000000000}, 2, true},
217 {SERIES(DS1000), "DS1152D", {2, 1000000000}, 2, true},
218 {SERIES(DS2000), "DS2072", {5, 1000000000}, 2, false},
219 {SERIES(DS2000), "DS2102", {5, 1000000000}, 2, false},
220 {SERIES(DS2000), "DS2202", {2, 1000000000}, 2, false},
221 {SERIES(DS2000), "DS2302", {1, 1000000000}, 2, false},
222 {SERIES(DS2000A), "DS2072A", {5, 1000000000}, 2, false},
223 {SERIES(DS2000A), "DS2102A", {5, 1000000000}, 2, false},
224 {SERIES(DS2000A), "DS2202A", {2, 1000000000}, 2, false},
225 {SERIES(DS2000A), "DS2302A", {1, 1000000000}, 2, false},
226 {SERIES(DSO1000), "DSO1002A", {5, 1000000000}, 2, false},
227 {SERIES(DSO1000), "DSO1004A", {5, 1000000000}, 4, false},
228 {SERIES(DSO1000), "DSO1012A", {2, 1000000000}, 2, false},
229 {SERIES(DSO1000), "DSO1014A", {2, 1000000000}, 4, false},
230 {SERIES(DSO1000), "DSO1022A", {2, 1000000000}, 2, false},
231 {SERIES(DSO1000), "DSO1024A", {2, 1000000000}, 4, false},
232};
233
234SR_PRIV struct sr_dev_driver rigol_ds_driver_info;
235static struct sr_dev_driver *di = &rigol_ds_driver_info;
236
237static void clear_helper(void *priv)
238{
239 struct dev_context *devc;
240 unsigned int i;
241
242 devc = priv;
243 g_free(devc->data);
244 g_free(devc->buffer);
245 for (i = 0; i < ARRAY_SIZE(devc->coupling); i++)
246 g_free(devc->coupling[i]);
247 g_free(devc->trigger_source);
248 g_free(devc->trigger_slope);
249 g_free(devc->analog_groups);
250 g_free(devc->digital_group);
251 g_free(devc);
252}
253
254static int dev_clear(void)
255{
256 return std_dev_clear(di, clear_helper);
257}
258
259static int init(struct sr_context *sr_ctx)
260{
261 return std_init(sr_ctx, di, LOG_PREFIX);
262}
263
264static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
265{
266 struct dev_context *devc;
267 struct sr_dev_inst *sdi;
268 struct sr_scpi_hw_info *hw_info;
269 struct sr_channel *ch;
270 long n[3];
271 unsigned int i;
272 const struct rigol_ds_model *model = NULL;
273 gchar *channel_name, **version;
274
275 if (sr_scpi_get_hw_id(scpi, &hw_info) != SR_OK) {
276 sr_info("Couldn't get IDN response, retrying.");
277 sr_scpi_close(scpi);
278 sr_scpi_open(scpi);
279 if (sr_scpi_get_hw_id(scpi, &hw_info) != SR_OK) {
280 sr_info("Couldn't get IDN response.");
281 return NULL;
282 }
283 }
284
285 for (i = 0; i < ARRAY_SIZE(supported_models); i++) {
286 if (!strcasecmp(hw_info->manufacturer,
287 supported_models[i].series->vendor->full_name) &&
288 !strcmp(hw_info->model, supported_models[i].name)) {
289 model = &supported_models[i];
290 break;
291 }
292 }
293
294 if (!model || !(sdi = sr_dev_inst_new(0, SR_ST_ACTIVE,
295 model->series->vendor->name,
296 model->name,
297 hw_info->firmware_version))) {
298 sr_scpi_hw_info_free(hw_info);
299 return NULL;
300 }
301
302 sdi->conn = scpi;
303
304 sdi->driver = di;
305 sdi->inst_type = SR_INST_SCPI;
306
307 if (!(devc = g_try_malloc0(sizeof(struct dev_context))))
308 return NULL;
309
310 devc->limit_frames = 0;
311 devc->model = model;
312 devc->format = model->series->format;
313
314 /* DS1000 models with firmware before 0.2.4 used the old data format. */
315 if (model->series == SERIES(DS1000)) {
316 version = g_strsplit(hw_info->firmware_version, ".", 0);
317 do {
318 if (!version[0] || !version[1] || !version[2])
319 break;
320 if (version[0][0] == 0 || version[1][0] == 0 || version[2][0] == 0)
321 break;
322 for (i = 0; i < 3; i++) {
323 if (sr_atol(version[i], &n[i]) != SR_OK)
324 break;
325 }
326 if (i != 3)
327 break;
328 if (n[0] != 0 || n[1] > 2)
329 break;
330 if (n[1] == 2 && n[2] > 3)
331 break;
332 sr_dbg("Found DS1000 firmware < 0.2.4, using raw data format.");
333 devc->format = FORMAT_RAW;
334 } while(0);
335 g_strfreev(version);
336 }
337
338 sr_scpi_hw_info_free(hw_info);
339
340 devc->analog_groups = g_malloc0(sizeof(struct sr_channel_group*) *
341 model->analog_channels);
342
343 for (i = 0; i < model->analog_channels; i++) {
344 if (!(channel_name = g_strdup_printf("CH%d", i + 1)))
345 return NULL;
346 ch = sr_channel_new(i, SR_CHANNEL_ANALOG, TRUE, channel_name);
347 sdi->channels = g_slist_append(sdi->channels, ch);
348
349 devc->analog_groups[i] = g_malloc0(sizeof(struct sr_channel_group));
350
351 devc->analog_groups[i]->name = channel_name;
352 devc->analog_groups[i]->channels = g_slist_append(NULL, ch);
353 sdi->channel_groups = g_slist_append(sdi->channel_groups,
354 devc->analog_groups[i]);
355 }
356
357 if (devc->model->has_digital) {
358 devc->digital_group = g_malloc0(sizeof(struct sr_channel_group*));
359
360 for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) {
361 if (!(channel_name = g_strdup_printf("D%d", i)))
362 return NULL;
363 ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE, channel_name);
364 g_free(channel_name);
365 if (!ch)
366 return NULL;
367 sdi->channels = g_slist_append(sdi->channels, ch);
368 devc->digital_group->channels = g_slist_append(
369 devc->digital_group->channels, ch);
370 }
371 devc->digital_group->name = g_strdup("LA");
372 sdi->channel_groups = g_slist_append(sdi->channel_groups,
373 devc->digital_group);
374 }
375
376 for (i = 0; i < NUM_TIMEBASE; i++) {
377 if (!memcmp(&devc->model->min_timebase, &timebases[i], sizeof(uint64_t[2])))
378 devc->timebases = &timebases[i];
379 if (!memcmp(&devc->model->series->max_timebase, &timebases[i], sizeof(uint64_t[2])))
380 devc->num_timebases = &timebases[i] - devc->timebases + 1;
381 }
382
383 for (i = 0; i < NUM_VDIV; i++)
384 if (!memcmp(&devc->model->series->min_vdiv, &vdivs[i], sizeof(uint64_t[2])))
385 devc->vdivs = &vdivs[i];
386
387 if (!(devc->buffer = g_try_malloc(ACQ_BUFFER_SIZE)))
388 return NULL;
389 if (!(devc->data = g_try_malloc(ACQ_BUFFER_SIZE * sizeof(float))))
390 return NULL;
391
392 devc->data_source = DATA_SOURCE_LIVE;
393
394 sdi->priv = devc;
395
396 return sdi;
397}
398
399static GSList *scan(GSList *options)
400{
401 return sr_scpi_scan(di->priv, options, probe_device);
402}
403
404static GSList *dev_list(void)
405{
406 return ((struct drv_context *)(di->priv))->instances;
407}
408
409static int dev_open(struct sr_dev_inst *sdi)
410{
411 struct sr_scpi_dev_inst *scpi = sdi->conn;
412
413 if (sr_scpi_open(scpi) < 0)
414 return SR_ERR;
415
416 if (rigol_ds_get_dev_cfg(sdi) != SR_OK)
417 return SR_ERR;
418
419 sdi->status = SR_ST_ACTIVE;
420
421 return SR_OK;
422}
423
424static int dev_close(struct sr_dev_inst *sdi)
425{
426 struct sr_scpi_dev_inst *scpi;
427 struct dev_context *devc;
428
429 if (sdi->status != SR_ST_ACTIVE)
430 return SR_ERR_DEV_CLOSED;
431
432 scpi = sdi->conn;
433 devc = sdi->priv;
434
435 if (devc->model->series->protocol == PROTOCOL_V2)
436 rigol_ds_config_set(sdi, ":KEY:LOCK DISABLE");
437
438 if (scpi) {
439 if (sr_scpi_close(scpi) < 0)
440 return SR_ERR;
441 sdi->status = SR_ST_INACTIVE;
442 }
443
444 return SR_OK;
445}
446
447static int cleanup(void)
448{
449 return dev_clear();
450}
451
452static int analog_frame_size(const struct sr_dev_inst *sdi)
453{
454 struct dev_context *devc = sdi->priv;
455 struct sr_channel *ch;
456 int analog_channels = 0;
457 GSList *l;
458
459 for (l = sdi->channels; l; l = l->next) {
460 ch = l->data;
461 if (ch->type == SR_CHANNEL_ANALOG && ch->enabled)
462 analog_channels++;
463 }
464
465 if (analog_channels == 0)
466 return 0;
467
468 switch (devc->data_source) {
469 case DATA_SOURCE_LIVE:
470 return devc->model->series->live_samples;
471 case DATA_SOURCE_MEMORY:
472 return devc->model->series->buffer_samples / analog_channels;
473 default:
474 return 0;
475 }
476}
477
478static int digital_frame_size(const struct sr_dev_inst *sdi)
479{
480 struct dev_context *devc = sdi->priv;
481
482 switch (devc->data_source) {
483 case DATA_SOURCE_LIVE:
484 return devc->model->series->live_samples * 2;
485 case DATA_SOURCE_MEMORY:
486 return devc->model->series->buffer_samples * 2;
487 default:
488 return 0;
489 }
490}
491
492static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
493 const struct sr_channel_group *cg)
494{
495 struct dev_context *devc;
496 struct sr_channel *ch;
497 const char *tmp_str;
498 uint64_t samplerate;
499 int analog_channel = -1;
500 float smallest_diff = 0.0000000001;
501 int idx = -1;
502 unsigned i;
503
504 if (!sdi || !(devc = sdi->priv))
505 return SR_ERR_ARG;
506
507 /* If a channel group is specified, it must be a valid one. */
508 if (cg && !g_slist_find(sdi->channel_groups, cg)) {
509 sr_err("Invalid channel group specified.");
510 return SR_ERR;
511 }
512
513 if (cg) {
514 ch = g_slist_nth_data(cg->channels, 0);
515 if (!ch)
516 return SR_ERR;
517 if (ch->type == SR_CHANNEL_ANALOG) {
518 if (ch->name[2] < '1' || ch->name[2] > '4')
519 return SR_ERR;
520 analog_channel = ch->name[2] - '1';
521 }
522 }
523
524 switch (key) {
525 case SR_CONF_NUM_TIMEBASE:
526 *data = g_variant_new_int32(devc->model->series->num_horizontal_divs);
527 break;
528 case SR_CONF_NUM_VDIV:
529 *data = g_variant_new_int32(NUM_VDIV);
530 case SR_CONF_DATA_SOURCE:
531 if (devc->data_source == DATA_SOURCE_LIVE)
532 *data = g_variant_new_string("Live");
533 else if (devc->data_source == DATA_SOURCE_MEMORY)
534 *data = g_variant_new_string("Memory");
535 else
536 *data = g_variant_new_string("Segmented");
537 break;
538 case SR_CONF_SAMPLERATE:
539 if (devc->data_source == DATA_SOURCE_LIVE) {
540 samplerate = analog_frame_size(sdi) /
541 (devc->timebase * devc->model->series->num_horizontal_divs);
542 *data = g_variant_new_uint64(samplerate);
543 } else {
544 return SR_ERR_NA;
545 }
546 break;
547 case SR_CONF_TRIGGER_SOURCE:
548 if (!strcmp(devc->trigger_source, "ACL"))
549 tmp_str = "AC Line";
550 else if (!strcmp(devc->trigger_source, "CHAN1"))
551 tmp_str = "CH1";
552 else if (!strcmp(devc->trigger_source, "CHAN2"))
553 tmp_str = "CH2";
554 else if (!strcmp(devc->trigger_source, "CHAN3"))
555 tmp_str = "CH3";
556 else if (!strcmp(devc->trigger_source, "CHAN4"))
557 tmp_str = "CH4";
558 else
559 tmp_str = devc->trigger_source;
560 *data = g_variant_new_string(tmp_str);
561 break;
562 case SR_CONF_TRIGGER_SLOPE:
563 if (!strcmp(devc->trigger_slope, "POS"))
564 tmp_str = "r";
565 else if (!strcmp(devc->trigger_slope, "NEG"))
566 tmp_str = "f";
567 else
568 return SR_ERR_NA;
569 *data = g_variant_new_string(tmp_str);
570 break;
571 case SR_CONF_TIMEBASE:
572 for (i = 0; i < devc->num_timebases; i++) {
573 float tb = (float)devc->timebases[i][0] / devc->timebases[i][1];
574 float diff = fabs(devc->timebase - tb);
575 if (diff < smallest_diff) {
576 smallest_diff = diff;
577 idx = i;
578 }
579 }
580 if (idx < 0)
581 return SR_ERR_NA;
582 *data = g_variant_new("(tt)", devc->timebases[idx][0],
583 devc->timebases[idx][1]);
584 break;
585 case SR_CONF_VDIV:
586 if (analog_channel < 0)
587 return SR_ERR_NA;
588 for (i = 0; i < ARRAY_SIZE(vdivs); i++) {
589 float vdiv = (float)vdivs[i][0] / vdivs[i][1];
590 float diff = fabs(devc->vdiv[analog_channel] - vdiv);
591 if (diff < smallest_diff) {
592 smallest_diff = diff;
593 idx = i;
594 }
595 }
596 if (idx < 0)
597 return SR_ERR_NA;
598 *data = g_variant_new("(tt)", vdivs[idx][0], vdivs[idx][1]);
599 break;
600 case SR_CONF_COUPLING:
601 if (analog_channel < 0)
602 return SR_ERR_NA;
603 *data = g_variant_new_string(devc->coupling[analog_channel]);
604 break;
605 default:
606 return SR_ERR_NA;
607 }
608
609 return SR_OK;
610}
611
612static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
613 const struct sr_channel_group *cg)
614{
615 struct dev_context *devc;
616 uint64_t p, q;
617 double t_dbl;
618 unsigned int i, j;
619 int ret;
620 const char *tmp_str;
621 char buffer[16];
622
623 if (!(devc = sdi->priv))
624 return SR_ERR_ARG;
625
626 if (sdi->status != SR_ST_ACTIVE)
627 return SR_ERR_DEV_CLOSED;
628
629 /* If a channel group is specified, it must be a valid one. */
630 if (cg && !g_slist_find(sdi->channel_groups, cg)) {
631 sr_err("Invalid channel group specified.");
632 return SR_ERR;
633 }
634
635 ret = SR_OK;
636 switch (key) {
637 case SR_CONF_LIMIT_FRAMES:
638 devc->limit_frames = g_variant_get_uint64(data);
639 break;
640 case SR_CONF_TRIGGER_SLOPE:
641 tmp_str = g_variant_get_string(data, NULL);
642
643 if (!tmp_str || !(tmp_str[0] == 'f' || tmp_str[0] == 'r'))
644 return SR_ERR_ARG;
645
646 g_free(devc->trigger_slope);
647 devc->trigger_slope = g_strdup((tmp_str[0] == 'r') ? "POS" : "NEG");
648 ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope);
649 break;
650 case SR_CONF_HORIZ_TRIGGERPOS:
651 t_dbl = g_variant_get_double(data);
652 if (t_dbl < 0.0 || t_dbl > 1.0)
653 return SR_ERR;
654 devc->horiz_triggerpos = t_dbl;
655 /* We have the trigger offset as a percentage of the frame, but
656 * need to express this in seconds. */
657 t_dbl = -(devc->horiz_triggerpos - 0.5) * devc->timebase * devc->num_timebases;
658 g_ascii_formatd(buffer, sizeof(buffer), "%.6f", t_dbl);
659 ret = rigol_ds_config_set(sdi, ":TIM:OFFS %s", buffer);
660 break;
661 case SR_CONF_TIMEBASE:
662 g_variant_get(data, "(tt)", &p, &q);
663 for (i = 0; i < devc->num_timebases; i++) {
664 if (devc->timebases[i][0] == p && devc->timebases[i][1] == q) {
665 devc->timebase = (float)p / q;
666 g_ascii_formatd(buffer, sizeof(buffer), "%.9f",
667 devc->timebase);
668 ret = rigol_ds_config_set(sdi, ":TIM:SCAL %s", buffer);
669 break;
670 }
671 }
672 if (i == devc->num_timebases)
673 ret = SR_ERR_ARG;
674 break;
675 case SR_CONF_TRIGGER_SOURCE:
676 tmp_str = g_variant_get_string(data, NULL);
677 for (i = 0; i < ARRAY_SIZE(trigger_sources); i++) {
678 if (!strcmp(trigger_sources[i], tmp_str)) {
679 g_free(devc->trigger_source);
680 devc->trigger_source = g_strdup(trigger_sources[i]);
681 if (!strcmp(devc->trigger_source, "AC Line"))
682 tmp_str = "ACL";
683 else if (!strcmp(devc->trigger_source, "CH1"))
684 tmp_str = "CHAN1";
685 else if (!strcmp(devc->trigger_source, "CH2"))
686 tmp_str = "CHAN2";
687 else if (!strcmp(devc->trigger_source, "CH3"))
688 tmp_str = "CHAN3";
689 else if (!strcmp(devc->trigger_source, "CH4"))
690 tmp_str = "CHAN4";
691 else
692 tmp_str = (char *)devc->trigger_source;
693 ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SOUR %s", tmp_str);
694 break;
695 }
696 }
697 if (i == ARRAY_SIZE(trigger_sources))
698 ret = SR_ERR_ARG;
699 break;
700 case SR_CONF_VDIV:
701 if (!cg) {
702 sr_err("No channel group specified.");
703 return SR_ERR_CHANNEL_GROUP;
704 }
705 g_variant_get(data, "(tt)", &p, &q);
706 for (i = 0; i < devc->model->analog_channels; i++) {
707 if (cg == devc->analog_groups[i]) {
708 for (j = 0; j < ARRAY_SIZE(vdivs); j++) {
709 if (vdivs[j][0] != p || vdivs[j][1] != q)
710 continue;
711 devc->vdiv[i] = (float)p / q;
712 g_ascii_formatd(buffer, sizeof(buffer), "%.3f",
713 devc->vdiv[i]);
714 return rigol_ds_config_set(sdi, ":CHAN%d:SCAL %s", i + 1,
715 buffer);
716 }
717 return SR_ERR_ARG;
718 }
719 }
720 return SR_ERR_NA;
721 case SR_CONF_COUPLING:
722 if (!cg) {
723 sr_err("No channel group specified.");
724 return SR_ERR_CHANNEL_GROUP;
725 }
726 tmp_str = g_variant_get_string(data, NULL);
727 for (i = 0; i < devc->model->analog_channels; i++) {
728 if (cg == devc->analog_groups[i]) {
729 for (j = 0; j < ARRAY_SIZE(coupling); j++) {
730 if (!strcmp(tmp_str, coupling[j])) {
731 g_free(devc->coupling[i]);
732 devc->coupling[i] = g_strdup(coupling[j]);
733 return rigol_ds_config_set(sdi, ":CHAN%d:COUP %s", i + 1,
734 devc->coupling[i]);
735 }
736 }
737 return SR_ERR_ARG;
738 }
739 }
740 return SR_ERR_NA;
741 case SR_CONF_DATA_SOURCE:
742 tmp_str = g_variant_get_string(data, NULL);
743 if (!strcmp(tmp_str, "Live"))
744 devc->data_source = DATA_SOURCE_LIVE;
745 else if (devc->model->series->protocol >= PROTOCOL_V2
746 && !strcmp(tmp_str, "Memory"))
747 devc->data_source = DATA_SOURCE_MEMORY;
748 else if (devc->model->series->protocol >= PROTOCOL_V3
749 && !strcmp(tmp_str, "Segmented"))
750 devc->data_source = DATA_SOURCE_SEGMENTED;
751 else
752 return SR_ERR;
753 break;
754 default:
755 ret = SR_ERR_NA;
756 break;
757 }
758
759 return ret;
760}
761
762static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
763 const struct sr_channel_group *cg)
764{
765 GVariant *tuple, *rational[2];
766 GVariantBuilder gvb;
767 unsigned int i;
768 struct dev_context *devc = NULL;
769
770 if (sdi)
771 devc = sdi->priv;
772
773 if (key == SR_CONF_SCAN_OPTIONS) {
774 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
775 hwopts, ARRAY_SIZE(hwopts), sizeof(uint32_t));
776 return SR_OK;
777 } else if (key == SR_CONF_DEVICE_OPTIONS && cg == NULL) {
778 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
779 hwcaps, ARRAY_SIZE(hwcaps), sizeof(uint32_t));
780 return SR_OK;
781 }
782
783 /* Every other option requires a valid device instance. */
784 if (!sdi || !(devc = sdi->priv))
785 return SR_ERR_ARG;
786
787 /* If a channel group is specified, it must be a valid one. */
788 if (cg) {
789 for (i = 0; i < devc->model->analog_channels; i++)
790 if (cg == devc->analog_groups[i])
791 break;
792 if (i >= devc->model->analog_channels) {
793 sr_err("Invalid channel group specified.");
794 return SR_ERR;
795 }
796 }
797
798 switch (key) {
799 case SR_CONF_DEVICE_OPTIONS:
800 if (!cg) {
801 sr_err("No channel group specified.");
802 return SR_ERR_CHANNEL_GROUP;
803 }
804 if (cg == devc->digital_group) {
805 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
806 NULL, 0, sizeof(uint32_t));
807 return SR_OK;
808 } else {
809 for (i = 0; i < devc->model->analog_channels; i++) {
810 if (cg == devc->analog_groups[i]) {
811 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
812 analog_hwcaps, ARRAY_SIZE(analog_hwcaps), sizeof(uint32_t));
813 return SR_OK;
814 }
815 }
816 return SR_ERR_NA;
817 }
818 break;
819 case SR_CONF_COUPLING:
820 if (!cg) {
821 sr_err("No channel group specified.");
822 return SR_ERR_CHANNEL_GROUP;
823 }
824 *data = g_variant_new_strv(coupling, ARRAY_SIZE(coupling));
825 break;
826 case SR_CONF_VDIV:
827 if (!devc)
828 /* Can't know this until we have the exact model. */
829 return SR_ERR_ARG;
830 if (!cg) {
831 sr_err("No channel group specified.");
832 return SR_ERR_CHANNEL_GROUP;
833 }
834 g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
835 for (i = 0; i < NUM_VDIV; i++) {
836 rational[0] = g_variant_new_uint64(devc->vdivs[i][0]);
837 rational[1] = g_variant_new_uint64(devc->vdivs[i][1]);
838 tuple = g_variant_new_tuple(rational, 2);
839 g_variant_builder_add_value(&gvb, tuple);
840 }
841 *data = g_variant_builder_end(&gvb);
842 break;
843 case SR_CONF_TIMEBASE:
844 if (!devc)
845 /* Can't know this until we have the exact model. */
846 return SR_ERR_ARG;
847 if (devc->num_timebases <= 0)
848 return SR_ERR_NA;
849 g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
850 for (i = 0; i < devc->num_timebases; i++) {
851 rational[0] = g_variant_new_uint64(devc->timebases[i][0]);
852 rational[1] = g_variant_new_uint64(devc->timebases[i][1]);
853 tuple = g_variant_new_tuple(rational, 2);
854 g_variant_builder_add_value(&gvb, tuple);
855 }
856 *data = g_variant_builder_end(&gvb);
857 break;
858 case SR_CONF_TRIGGER_SOURCE:
859 if (!devc)
860 /* Can't know this until we have the exact model. */
861 return SR_ERR_ARG;
862 *data = g_variant_new_strv(trigger_sources,
863 devc->model->has_digital ? ARRAY_SIZE(trigger_sources) : 4);
864 break;
865 case SR_CONF_TRIGGER_SLOPE:
866 *data = g_variant_new_strv(trigger_slopes, ARRAY_SIZE(trigger_slopes));
867 break;
868 case SR_CONF_DATA_SOURCE:
869 if (!devc)
870 /* Can't know this until we have the exact model. */
871 return SR_ERR_ARG;
872 switch (devc->model->series->protocol) {
873 case PROTOCOL_V1:
874 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 2);
875 break;
876 case PROTOCOL_V2:
877 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 1);
878 break;
879 default:
880 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources));
881 break;
882 }
883 break;
884 default:
885 return SR_ERR_NA;
886 }
887
888 return SR_OK;
889}
890
891static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
892{
893 struct sr_scpi_dev_inst *scpi;
894 struct dev_context *devc;
895 struct sr_channel *ch;
896 struct sr_datafeed_packet packet;
897 GSList *l;
898
899 if (sdi->status != SR_ST_ACTIVE)
900 return SR_ERR_DEV_CLOSED;
901
902 scpi = sdi->conn;
903 devc = sdi->priv;
904
905 devc->num_frames = 0;
906
907 for (l = sdi->channels; l; l = l->next) {
908 ch = l->data;
909 sr_dbg("handling channel %s", ch->name);
910 if (ch->type == SR_CHANNEL_ANALOG) {
911 if (ch->enabled)
912 devc->enabled_analog_channels = g_slist_append(
913 devc->enabled_analog_channels, ch);
914 if (ch->enabled != devc->analog_channels[ch->index]) {
915 /* Enabled channel is currently disabled, or vice versa. */
916 if (rigol_ds_config_set(sdi, ":CHAN%d:DISP %s", ch->index + 1,
917 ch->enabled ? "ON" : "OFF") != SR_OK)
918 return SR_ERR;
919 devc->analog_channels[ch->index] = ch->enabled;
920 }
921 } else if (ch->type == SR_CHANNEL_LOGIC) {
922 if (ch->enabled) {
923 devc->enabled_digital_channels = g_slist_append(
924 devc->enabled_digital_channels, ch);
925 /* Turn on LA module if currently off. */
926 if (!devc->la_enabled) {
927 if (rigol_ds_config_set(sdi, ":LA:DISP ON") != SR_OK)
928 return SR_ERR;
929 devc->la_enabled = TRUE;
930 }
931 }
932 if (ch->enabled != devc->digital_channels[ch->index]) {
933 /* Enabled channel is currently disabled, or vice versa. */
934 if (rigol_ds_config_set(sdi, ":DIG%d:TURN %s", ch->index,
935 ch->enabled ? "ON" : "OFF") != SR_OK)
936 return SR_ERR;
937 devc->digital_channels[ch->index] = ch->enabled;
938 }
939 }
940 }
941
942 if (!devc->enabled_analog_channels && !devc->enabled_digital_channels)
943 return SR_ERR;
944
945 /* Turn off LA module if on and no digital channels selected. */
946 if (devc->la_enabled && !devc->enabled_digital_channels)
947 if (rigol_ds_config_set(sdi, ":LA:DISP OFF") != SR_OK)
948 return SR_ERR;
949
950 /* Set memory mode. */
951 if (devc->data_source == DATA_SOURCE_SEGMENTED) {
952 sr_err("Data source 'Segmented' not yet supported");
953 return SR_ERR;
954 }
955
956 devc->analog_frame_size = analog_frame_size(sdi);
957 devc->digital_frame_size = digital_frame_size(sdi);
958
959 switch (devc->model->series->protocol) {
960 case PROTOCOL_V2:
961 if (rigol_ds_config_set(sdi, ":ACQ:MEMD LONG") != SR_OK)
962 return SR_ERR;
963 break;
964 case PROTOCOL_V3:
965 /* Apparently for the DS2000 the memory
966 * depth can only be set in Running state -
967 * this matches the behaviour of the UI. */
968 if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
969 return SR_ERR;
970 if (rigol_ds_config_set(sdi, ":ACQ:MDEP %d",
971 devc->analog_frame_size) != SR_OK)
972 return SR_ERR;
973 if (rigol_ds_config_set(sdi, ":STOP") != SR_OK)
974 return SR_ERR;
975 break;
976 default:
977 break;
978 }
979
980 if (devc->data_source == DATA_SOURCE_LIVE)
981 if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
982 return SR_ERR;
983
984 sr_scpi_source_add(sdi->session, scpi, G_IO_IN, 50,
985 rigol_ds_receive, (void *)sdi);
986
987 /* Send header packet to the session bus. */
988 std_session_send_df_header(cb_data, LOG_PREFIX);
989
990 if (devc->enabled_analog_channels)
991 devc->channel_entry = devc->enabled_analog_channels;
992 else
993 devc->channel_entry = devc->enabled_digital_channels;
994
995 if (rigol_ds_capture_start(sdi) != SR_OK)
996 return SR_ERR;
997
998 /* Start of first frame. */
999 packet.type = SR_DF_FRAME_BEGIN;
1000 sr_session_send(cb_data, &packet);
1001
1002 return SR_OK;
1003}
1004
1005static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1006{
1007 struct dev_context *devc;
1008 struct sr_scpi_dev_inst *scpi;
1009 struct sr_datafeed_packet packet;
1010
1011 (void)cb_data;
1012
1013 devc = sdi->priv;
1014
1015 if (sdi->status != SR_ST_ACTIVE) {
1016 sr_err("Device inactive, can't stop acquisition.");
1017 return SR_ERR;
1018 }
1019
1020 /* End of last frame. */
1021 packet.type = SR_DF_END;
1022 sr_session_send(sdi, &packet);
1023
1024 g_slist_free(devc->enabled_analog_channels);
1025 g_slist_free(devc->enabled_digital_channels);
1026 devc->enabled_analog_channels = NULL;
1027 devc->enabled_digital_channels = NULL;
1028 scpi = sdi->conn;
1029 sr_scpi_source_remove(sdi->session, scpi);
1030
1031 return SR_OK;
1032}
1033
1034SR_PRIV struct sr_dev_driver rigol_ds_driver_info = {
1035 .name = "rigol-ds",
1036 .longname = "Rigol DS",
1037 .api_version = 1,
1038 .init = init,
1039 .cleanup = cleanup,
1040 .scan = scan,
1041 .dev_list = dev_list,
1042 .dev_clear = dev_clear,
1043 .config_get = config_get,
1044 .config_set = config_set,
1045 .config_list = config_list,
1046 .dev_open = dev_open,
1047 .dev_close = dev_close,
1048 .dev_acquisition_start = dev_acquisition_start,
1049 .dev_acquisition_stop = dev_acquisition_stop,
1050 .priv = NULL,
1051};
Hardware access and backend lib