[libsigrok.git] / src / hardware / pipistrello-ols / api.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <config.h>
#include "protocol.h"

static const uint32_t drvopts[] = {
	SR_CONF_LOGIC_ANALYZER,
};

static const uint32_t devopts[] = {
	SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
	SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
	SR_CONF_PATTERN_MODE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
	SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
	SR_CONF_SWAP | SR_CONF_SET,
	SR_CONF_RLE | SR_CONF_GET | SR_CONF_SET,
};

static const int32_t trigger_matches[] = {
	SR_TRIGGER_ZERO,
	SR_TRIGGER_ONE,
	SR_TRIGGER_RISING,
	SR_TRIGGER_FALLING,
};

#define STR_PATTERN_NONE     "None"
#define STR_PATTERN_EXTERNAL "External"
#define STR_PATTERN_INTERNAL "Internal"

/* Supported methods of test pattern outputs */
enum {
	/**
	 * Capture pins 31:16 (unbuffered wing) output a test pattern
	 * that can captured on pins 0:15.
	 */
	PATTERN_EXTERNAL,

	/** Route test pattern internally to capture buffer. */
	PATTERN_INTERNAL,
};

static const char *patterns[] = {
	STR_PATTERN_NONE,
	STR_PATTERN_EXTERNAL,
	STR_PATTERN_INTERNAL,
};

/* Channels are numbered 0-31 (on the PCB silkscreen). */
SR_PRIV const char *p_ols_channel_names[] = {
	"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12",
	"13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23",
	"24", "25", "26", "27", "28", "29", "30", "31",
};

/* Default supported samplerates, can be overridden by device metadata. */
static const uint64_t samplerates[] = {
	SR_HZ(10),
	SR_MHZ(200),
	SR_HZ(1),
};

static GSList *scan(struct sr_dev_driver *di, GSList *options)
{
	struct sr_dev_inst *sdi;
	struct dev_context *devc;
	GSList *devices;
	int ret, i;
	char buf[70];
	int bytes_read;

	(void)options;

	devices = NULL;

	devc = g_malloc0(sizeof(struct dev_context));

	devc->max_samplebytes = devc->max_samplerate = devc->protocol_version = 0;

	devc->limit_samples = devc->capture_ratio = 0;
	devc->trigger_at = -1;
	devc->channel_mask = 0xffffffff;
	devc->flag_reg = 0;

	devc->ftdi_buf = g_malloc0(FTDI_BUF_SIZE);

	if (!(devc->ftdic = ftdi_new())) {
		sr_err("Failed to initialize libftdi.");
		goto err_free_ftdi_buf;;
	}

	if (p_ols_open(devc) != SR_OK)
		goto err_free_ftdic;

	/* The discovery procedure is like this: first send the Reset
	 * command (0x00) 5 times, since the device could be anywhere
	 * in a 5-byte command. Then send the ID command (0x02).
	 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
	 * have a match.
	 */

	ret = SR_OK;
	for (i = 0; i < 5; i++) {
		if ((ret = write_shortcommand(devc, CMD_RESET)) != SR_OK) {
			break;
		}
	}
	if (ret != SR_OK) {
		sr_err("Could not reset device. Quitting.");
		goto err_close_ftdic;
	}
	write_shortcommand(devc, CMD_ID);

	/* Read the response data. */
	bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 4);
	if (bytes_read < 0) {
		sr_err("Failed to read FTDI data (%d): %s.",
		       bytes_read, ftdi_get_error_string(devc->ftdic));
		goto err_close_ftdic;
	}
	if (bytes_read == 0) {
		goto err_close_ftdic;
	}

	if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
		goto err_close_ftdic;

	/* Definitely using the OLS protocol, check if it supports
	 * the metadata command.
	 */
	write_shortcommand(devc, CMD_METADATA);

        /* Read the metadata. */
	bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 64);
	if (bytes_read < 0) {
		sr_err("Failed to read FTDI data (%d): %s.",
		       bytes_read, ftdi_get_error_string(devc->ftdic));
		goto err_close_ftdic;
	}
	if (bytes_read == 0) {
		goto err_close_ftdic;
	}

	p_ols_close(devc);

	/* Parse the metadata. */
	sdi = p_ols_get_metadata((uint8_t *)buf, bytes_read, devc);

	/* Configure samplerate and divider. */
	if (p_ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK)
		sr_dbg("Failed to set default samplerate (%"PRIu64").",
				DEFAULT_SAMPLERATE);

	devices = g_slist_append(devices, sdi);

	return std_scan_complete(di, devices);

err_close_ftdic:
	p_ols_close(devc);
err_free_ftdic:
	ftdi_free(devc->ftdic);
err_free_ftdi_buf:
	g_free(devc->ftdi_buf);
	g_free(devc);

	return NULL;
}

static void clear_helper(struct dev_context *devc)
{
	ftdi_free(devc->ftdic);
	g_free(devc->ftdi_buf);
}

static int dev_clear(const struct sr_dev_driver *di)
{
	return std_dev_clear_with_callback(di, (std_dev_clear_callback)clear_helper);
}

static int config_get(uint32_t key, GVariant **data,
	const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
	struct dev_context *devc;

	(void)cg;

	if (!sdi)
		return SR_ERR_ARG;

	devc = sdi->priv;

	switch (key) {
	case SR_CONF_SAMPLERATE:
		*data = g_variant_new_uint64(devc->cur_samplerate);
		break;
	case SR_CONF_CAPTURE_RATIO:
		*data = g_variant_new_uint64(devc->capture_ratio);
		break;
	case SR_CONF_LIMIT_SAMPLES:
		*data = g_variant_new_uint64(devc->limit_samples);
		break;
	case SR_CONF_PATTERN_MODE:
		if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE)
			*data = g_variant_new_string(STR_PATTERN_EXTERNAL);
		else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE)
			*data = g_variant_new_string(STR_PATTERN_INTERNAL);
		else
			*data = g_variant_new_string(STR_PATTERN_NONE);
		break;
	case SR_CONF_RLE:
		*data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE);
		break;
	case SR_CONF_EXTERNAL_CLOCK:
		*data = g_variant_new_boolean(devc->flag_reg & FLAG_CLOCK_EXTERNAL ? TRUE : FALSE);
		break;
	default:
		return SR_ERR_NA;
	}

	return SR_OK;
}

static int config_set(uint32_t key, GVariant *data,
	const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
	struct dev_context *devc;
	uint16_t flag;
	uint64_t tmp_u64;
	const char *stropt;

	(void)cg;

	devc = sdi->priv;

	switch (key) {
	case SR_CONF_SAMPLERATE:
		tmp_u64 = g_variant_get_uint64(data);
		if (tmp_u64 < samplerates[0] || tmp_u64 > samplerates[1])
			return SR_ERR_SAMPLERATE;
		return p_ols_set_samplerate(sdi, g_variant_get_uint64(data));
	case SR_CONF_LIMIT_SAMPLES:
		tmp_u64 = g_variant_get_uint64(data);
		if (tmp_u64 < MIN_NUM_SAMPLES)
			return SR_ERR;
		devc->limit_samples = tmp_u64;
		break;
	case SR_CONF_CAPTURE_RATIO:
		devc->capture_ratio = g_variant_get_uint64(data);
		break;
	case SR_CONF_EXTERNAL_CLOCK:
		if (g_variant_get_boolean(data)) {
			sr_info("Enabling external clock.");
			devc->flag_reg |= FLAG_CLOCK_EXTERNAL;
		} else {
			sr_info("Disabled external clock.");
			devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL;
		}
		break;
	case SR_CONF_PATTERN_MODE:
		stropt = g_variant_get_string(data, NULL);
		if (!strcmp(stropt, STR_PATTERN_NONE)) {
			sr_info("Disabling test modes.");
			flag = 0x0000;
		} else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) {
			sr_info("Enabling internal test mode.");
			flag = FLAG_INTERNAL_TEST_MODE;
		} else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) {
			sr_info("Enabling external test mode.");
			flag = FLAG_EXTERNAL_TEST_MODE;
		} else {
			return SR_ERR;
		}
		devc->flag_reg &= ~FLAG_INTERNAL_TEST_MODE;
		devc->flag_reg &= ~FLAG_EXTERNAL_TEST_MODE;
		devc->flag_reg |= flag;
		break;
	case SR_CONF_SWAP:
		if (g_variant_get_boolean(data)) {
			sr_info("Enabling channel swapping.");
			devc->flag_reg |= FLAG_SWAP_CHANNELS;
		} else {
			sr_info("Disabling channel swapping.");
			devc->flag_reg &= ~FLAG_SWAP_CHANNELS;
		}
		break;
	case SR_CONF_RLE:
		if (g_variant_get_boolean(data)) {
			sr_info("Enabling RLE.");
			devc->flag_reg |= FLAG_RLE;
		} else {
			sr_info("Disabling RLE.");
			devc->flag_reg &= ~FLAG_RLE;
		}
		break;
	default:
		return SR_ERR_NA;
	}

	return SR_OK;
}

static int config_list(uint32_t key, GVariant **data,
	const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
{
	struct dev_context *devc;
	int num_pols_changrp, i;

	switch (key) {
	case SR_CONF_DEVICE_OPTIONS:
		return STD_CONFIG_LIST(key, data, sdi, cg, NO_OPTS, drvopts, devopts);
	case SR_CONF_SAMPLERATE:
		*data = std_gvar_samplerates_steps(ARRAY_AND_SIZE(samplerates));
		break;
	case SR_CONF_TRIGGER_MATCH:
		*data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
		break;
	case SR_CONF_PATTERN_MODE:
		*data = g_variant_new_strv(ARRAY_AND_SIZE(patterns));
		break;
	case SR_CONF_LIMIT_SAMPLES:
		if (!sdi)
			return SR_ERR_ARG;
		devc = sdi->priv;
		if (devc->flag_reg & FLAG_RLE)
			return SR_ERR_NA;
		if (devc->max_samplebytes == 0)
			/* Device didn't specify sample memory size in metadata. */
			return SR_ERR_NA;
		/*
		 * Channel groups are turned off if no channels in that group are
		 * enabled, making more room for samples for the enabled group.
		*/
		pols_channel_mask(sdi);
		num_pols_changrp = 0;
		for (i = 0; i < 4; i++) {
			if (devc->channel_mask & (0xff << (i * 8)))
				num_pols_changrp++;
		}
		/* 3 channel groups takes as many bytes as 4 channel groups */
		if (num_pols_changrp == 3)
			num_pols_changrp = 4;

		*data = std_gvar_tuple_u64(MIN_NUM_SAMPLES,
			(num_pols_changrp) ? devc->max_samplebytes / num_pols_changrp : MIN_NUM_SAMPLES);
		break;
	default:
		return SR_ERR_NA;
	}

	return SR_OK;
}

static int dev_open(struct sr_dev_inst *sdi)
{
	struct dev_context *devc;

	devc = sdi->priv;

	return p_ols_open(devc);
}

static int dev_close(struct sr_dev_inst *sdi)
{
	struct dev_context *devc;

	devc = sdi->priv;

	return p_ols_close(devc);
}

static int set_trigger(const struct sr_dev_inst *sdi, int stage)
{
	struct dev_context *devc;
	uint8_t cmd, arg[4];

	devc = sdi->priv;

	cmd = CMD_SET_TRIGGER_MASK + stage * 4;
	arg[0] = devc->trigger_mask[stage] & 0xff;
	arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff;
	arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff;
	arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff;
	if (write_longcommand(devc, cmd, arg) != SR_OK)
		return SR_ERR;

	cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
	arg[0] = devc->trigger_value[stage] & 0xff;
	arg[1] = (devc->trigger_value[stage] >> 8) & 0xff;
	arg[2] = (devc->trigger_value[stage] >> 16) & 0xff;
	arg[3] = (devc->trigger_value[stage] >> 24) & 0xff;
	if (write_longcommand(devc, cmd, arg) != SR_OK)
		return SR_ERR;

	cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
	arg[0] = arg[1] = arg[3] = 0x00;
	arg[2] = stage;
	if (stage == devc->num_stages)
		/* Last stage, fire when this one matches. */
		arg[3] |= TRIGGER_START;
	if (write_longcommand(devc, cmd, arg) != SR_OK)
		return SR_ERR;

	cmd = CMD_SET_TRIGGER_EDGE + stage * 4;
	arg[0] = devc->trigger_edge[stage] & 0xff;
	arg[1] = (devc->trigger_edge[stage] >> 8) & 0xff;
	arg[2] = (devc->trigger_edge[stage] >> 16) & 0xff;
	arg[3] = (devc->trigger_edge[stage] >> 24) & 0xff;
	if (write_longcommand(devc, cmd, arg) != SR_OK)
		return SR_ERR;

	return SR_OK;
}

static int disable_trigger(const struct sr_dev_inst *sdi, int stage)
{
	struct dev_context *devc;
	uint8_t cmd, arg[4];

	devc = sdi->priv;

	cmd = CMD_SET_TRIGGER_MASK + stage * 4;
	arg[0] = arg[1] = arg[2] = arg[3] = 0x00;
	if (write_longcommand(devc, cmd, arg) != SR_OK)
		return SR_ERR;

	cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
	if (write_longcommand(devc, cmd, arg) != SR_OK)
		return SR_ERR;

	cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
	arg[2] = 0x03;
	if (write_longcommand(devc, cmd, arg) != SR_OK)
		return SR_ERR;

	cmd = CMD_SET_TRIGGER_EDGE + stage * 4;
	arg[2] = 0x00;
	if (write_longcommand(devc, cmd, arg) != SR_OK)
		return SR_ERR;

	return SR_OK;
}

static int dev_acquisition_start(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	uint32_t samplecount, readcount, delaycount;
	uint8_t pols_changrp_mask, arg[4];
	uint16_t flag_tmp;
	int num_pols_changrp, samplespercount;
	int ret, i;

	devc = sdi->priv;

	pols_channel_mask(sdi);

	/*
	 * Enable/disable channel groups in the flag register according to the
	 * channel mask. Calculate this here, because num_pols_changrp is
	 * needed to limit readcount.
	 */
	pols_changrp_mask = 0;
	num_pols_changrp = 0;
	for (i = 0; i < 4; i++) {
		if (devc->channel_mask & (0xff << (i * 8))) {
			pols_changrp_mask |= (1 << i);
			num_pols_changrp++;
		}
	}
	/* 3 channel groups takes as many bytes as 4 channel groups */
	if (num_pols_changrp == 3)
		num_pols_changrp = 4;
	/* maximum number of samples (or RLE counts) the buffer memory can hold */
	devc->max_samples = devc->max_samplebytes / num_pols_changrp;

	/*
	 * Limit readcount to prevent reading past the end of the hardware
	 * buffer.
	 */
	sr_dbg("max_samples = %d", devc->max_samples);
	sr_dbg("limit_samples = %" PRIu64, devc->limit_samples);
	samplecount = MIN(devc->max_samples, devc->limit_samples);
	sr_dbg("Samplecount = %d", samplecount);

	/* In demux mode the OLS is processing two samples per clock */
	if (devc->flag_reg & FLAG_DEMUX) {
		samplespercount = 8;
	}
	else {
		samplespercount = 4;
	}

	readcount = samplecount / samplespercount;

	/* Rather read too many samples than too few. */
	if (samplecount % samplespercount != 0)
		readcount++;

	/* Basic triggers. */
	if (pols_convert_trigger(sdi) != SR_OK) {
		sr_err("Failed to configure channels.");
		return SR_ERR;
	}

	if (devc->num_stages > 0) {
		delaycount = readcount * (1 - devc->capture_ratio / 100.0);
		devc->trigger_at = (readcount - delaycount) * samplespercount - devc->num_stages;
		for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
			if (i <= devc->num_stages) {
				sr_dbg("Setting p-ols stage %d trigger.", i);
				if ((ret = set_trigger(sdi, i)) != SR_OK)
					return ret;
			}
			else {
				sr_dbg("Disabling p-ols stage %d trigger.", i);
				if ((ret = disable_trigger(sdi, i)) != SR_OK)
					return ret;
			}
		}
	} else {
		/* No triggers configured, force trigger on first stage. */
		sr_dbg("Forcing trigger at stage 0.");
		if ((ret = set_trigger(sdi, 0)) != SR_OK)
			return ret;
		delaycount = readcount;
	}

	/* Samplerate. */
	sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
			devc->cur_samplerate, devc->cur_samplerate_divider);
	arg[0] = devc->cur_samplerate_divider & 0xff;
	arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8;
	arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16;
	arg[3] = 0x00;
	if (write_longcommand(devc, CMD_SET_DIVIDER, arg) != SR_OK)
		return SR_ERR;

	/* Send extended sample limit and pre/post-trigger capture ratio. */
	arg[0] = ((readcount - 1) & 0xff);
	arg[1] = ((readcount - 1) & 0xff00) >> 8;
	arg[2] = ((readcount - 1) & 0xff0000) >> 16;
	arg[3] = ((readcount - 1) & 0xff000000) >> 24;
	if (write_longcommand(devc, CMD_CAPTURE_DELAY, arg) != SR_OK)
		return SR_ERR;
	arg[0] = ((delaycount - 1) & 0xff);
	arg[1] = ((delaycount - 1) & 0xff00) >> 8;
	arg[2] = ((delaycount - 1) & 0xff0000) >> 16;
	arg[3] = ((delaycount - 1) & 0xff000000) >> 24;
	if (write_longcommand(devc, CMD_CAPTURE_COUNT, arg) != SR_OK)
		return SR_ERR;

	/* Flag register. */
	sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
			devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off",
			devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off",
			devc->flag_reg & FLAG_RLE ? "on" : "off",
			devc->flag_reg & FLAG_FILTER ? "on": "off",
			devc->flag_reg & FLAG_DEMUX ? "on" : "off");

	/*
	* Enable/disable OLS channel groups in the flag register according
	* to the channel mask. 1 means "disable channel".
	*/
	devc->flag_reg &= ~0x3c;
	devc->flag_reg |= ~(pols_changrp_mask << 2) & 0x3c;
	sr_dbg("flag_reg = %x", devc->flag_reg);

	/*
	* In demux mode the OLS is processing two 8-bit or 16-bit samples
	* in parallel and for this to work the lower two bits of the four
	* "channel_disable" bits must be replicated to the upper two bits.
	*/
	flag_tmp = devc->flag_reg;
	if (devc->flag_reg & FLAG_DEMUX) {
		flag_tmp &= ~0x30;
		flag_tmp |= ~(pols_changrp_mask << 4) & 0x30;
	}
	arg[0] = flag_tmp & 0xff;
	arg[1] = flag_tmp >> 8;
	arg[2] = arg[3] = 0x00;
	if (write_longcommand(devc, CMD_SET_FLAGS, arg) != SR_OK)
		return SR_ERR;

	/* Start acquisition on the device. */
	if (write_shortcommand(devc, CMD_RUN) != SR_OK)
		return SR_ERR;

	/* Reset all operational states. */
	devc->rle_count = devc->num_transfers = 0;
	devc->num_samples = devc->num_bytes = 0;
	devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0;
	memset(devc->sample, 0, 4);

	std_session_send_df_header(sdi);

	/* Hook up a dummy handler to receive data from the device. */
	sr_session_source_add(sdi->session, -1, 0, 10, p_ols_receive_data,
				(struct sr_dev_inst *)sdi);

	return SR_OK;
}

static int dev_acquisition_stop(struct sr_dev_inst *sdi)
{
	struct dev_context *devc;

	devc = sdi->priv;

	write_shortcommand(devc, CMD_RESET);
	write_shortcommand(devc, CMD_RESET);
	write_shortcommand(devc, CMD_RESET);
	write_shortcommand(devc, CMD_RESET);
	write_shortcommand(devc, CMD_RESET);

	sr_session_source_remove(sdi->session, -1);

	std_session_send_df_end(sdi);

	return SR_OK;
}

SR_PRIV struct sr_dev_driver p_ols_driver_info = {
	.name = "p-ols",
	.longname = "Pipistrello OLS",
	.api_version = 1,
	.init = std_init,
	.cleanup = std_cleanup,
	.scan = scan,
	.dev_list = std_dev_list,
	.dev_clear = dev_clear,
	.config_get = config_get,
	.config_set = config_set,
	.config_list = config_list,
	.dev_open = dev_open,
	.dev_close = dev_close,
	.dev_acquisition_start = dev_acquisition_start,
	.dev_acquisition_stop = dev_acquisition_stop,
	.context = NULL,
};
SR_REGISTER_DEV_DRIVER(p_ols_driver_info);
Commit	Line	Data
	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation, either version 3 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <config.h>
	21	#include "protocol.h"
	22
	23	static const uint32_t drvopts[] = {
	24	SR_CONF_LOGIC_ANALYZER,
	25	};
	26
	27	static const uint32_t devopts[] = {
	28	SR_CONF_LIMIT_SAMPLES \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	29	SR_CONF_SAMPLERATE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	30	SR_CONF_TRIGGER_MATCH \| SR_CONF_LIST,
	31	SR_CONF_CAPTURE_RATIO \| SR_CONF_GET \| SR_CONF_SET,
	32	SR_CONF_PATTERN_MODE \| SR_CONF_GET \| SR_CONF_SET \| SR_CONF_LIST,
	33	SR_CONF_EXTERNAL_CLOCK \| SR_CONF_GET \| SR_CONF_SET,
	34	SR_CONF_SWAP \| SR_CONF_SET,
	35	SR_CONF_RLE \| SR_CONF_GET \| SR_CONF_SET,
	36	};
	37
	38	static const int32_t trigger_matches[] = {
	39	SR_TRIGGER_ZERO,
	40	SR_TRIGGER_ONE,
	41	SR_TRIGGER_RISING,
	42	SR_TRIGGER_FALLING,
	43	};
	44
	45	#define STR_PATTERN_NONE "None"
	46	#define STR_PATTERN_EXTERNAL "External"
	47	#define STR_PATTERN_INTERNAL "Internal"
	48
	49	/* Supported methods of test pattern outputs */
	50	enum {
	51	/**
	52	* Capture pins 31:16 (unbuffered wing) output a test pattern
	53	* that can captured on pins 0:15.
	54	*/
	55	PATTERN_EXTERNAL,
	56
	57	/** Route test pattern internally to capture buffer. */
	58	PATTERN_INTERNAL,
	59	};
	60
	61	static const char *patterns[] = {
	62	STR_PATTERN_NONE,
	63	STR_PATTERN_EXTERNAL,
	64	STR_PATTERN_INTERNAL,
	65	};
	66
	67	/* Channels are numbered 0-31 (on the PCB silkscreen). */
	68	SR_PRIV const char *p_ols_channel_names[] = {
	69	"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12",
	70	"13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23",
	71	"24", "25", "26", "27", "28", "29", "30", "31",
	72	};
	73
	74	/* Default supported samplerates, can be overridden by device metadata. */
	75	static const uint64_t samplerates[] = {
	76	SR_HZ(10),
	77	SR_MHZ(200),
	78	SR_HZ(1),
	79	};
	80
	81	static GSList scan(struct sr_dev_driver di, GSList *options)
	82	{
	83	struct sr_dev_inst *sdi;
	84	struct dev_context *devc;
	85	GSList *devices;
	86	int ret, i;
	87	char buf[70];
	88	int bytes_read;
	89
	90	(void)options;
	91
	92	devices = NULL;
	93
	94	devc = g_malloc0(sizeof(struct dev_context));
	95
	96	devc->max_samplebytes = devc->max_samplerate = devc->protocol_version = 0;
	97
	98	devc->limit_samples = devc->capture_ratio = 0;
	99	devc->trigger_at = -1;
	100	devc->channel_mask = 0xffffffff;
	101	devc->flag_reg = 0;
	102
	103	devc->ftdi_buf = g_malloc0(FTDI_BUF_SIZE);
	104
	105	if (!(devc->ftdic = ftdi_new())) {
	106	sr_err("Failed to initialize libftdi.");
	107	goto err_free_ftdi_buf;;
	108	}
	109
	110	if (p_ols_open(devc) != SR_OK)
	111	goto err_free_ftdic;
	112
	113	/* The discovery procedure is like this: first send the Reset
	114	* command (0x00) 5 times, since the device could be anywhere
	115	* in a 5-byte command. Then send the ID command (0x02).
	116	* If the device responds with 4 bytes ("OLS1" or "SLA1"), we
	117	* have a match.
	118	*/
	119
	120	ret = SR_OK;
	121	for (i = 0; i < 5; i++) {
	122	if ((ret = write_shortcommand(devc, CMD_RESET)) != SR_OK) {
	123	break;
	124	}
	125	}
	126	if (ret != SR_OK) {
	127	sr_err("Could not reset device. Quitting.");
	128	goto err_close_ftdic;
	129	}
	130	write_shortcommand(devc, CMD_ID);
	131
	132	/* Read the response data. */
	133	bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 4);
	134	if (bytes_read < 0) {
	135	sr_err("Failed to read FTDI data (%d): %s.",
	136	bytes_read, ftdi_get_error_string(devc->ftdic));
	137	goto err_close_ftdic;
	138	}
	139	if (bytes_read == 0) {
	140	goto err_close_ftdic;
	141	}
	142
	143	if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
	144	goto err_close_ftdic;
	145
	146	/* Definitely using the OLS protocol, check if it supports
	147	* the metadata command.
	148	*/
	149	write_shortcommand(devc, CMD_METADATA);
	150
	151	/* Read the metadata. */
	152	bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 64);
	153	if (bytes_read < 0) {
	154	sr_err("Failed to read FTDI data (%d): %s.",
	155	bytes_read, ftdi_get_error_string(devc->ftdic));
	156	goto err_close_ftdic;
	157	}
	158	if (bytes_read == 0) {
	159	goto err_close_ftdic;
	160	}
	161
	162	p_ols_close(devc);
	163
	164	/* Parse the metadata. */
	165	sdi = p_ols_get_metadata((uint8_t *)buf, bytes_read, devc);
	166
	167	/* Configure samplerate and divider. */
	168	if (p_ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK)
	169	sr_dbg("Failed to set default samplerate (%"PRIu64").",
	170	DEFAULT_SAMPLERATE);
	171
	172	devices = g_slist_append(devices, sdi);
	173
	174	return std_scan_complete(di, devices);
	175
	176	err_close_ftdic:
	177	p_ols_close(devc);
	178	err_free_ftdic:
	179	ftdi_free(devc->ftdic);
	180	err_free_ftdi_buf:
	181	g_free(devc->ftdi_buf);
	182	g_free(devc);
	183
	184	return NULL;
	185	}
	186
	187	static void clear_helper(struct dev_context *devc)
	188	{
	189	ftdi_free(devc->ftdic);
	190	g_free(devc->ftdi_buf);
	191	}
	192
	193	static int dev_clear(const struct sr_dev_driver *di)
	194	{
	195	return std_dev_clear_with_callback(di, (std_dev_clear_callback)clear_helper);
	196	}
	197
	198	static int config_get(uint32_t key, GVariant **data,
	199	const struct sr_dev_inst sdi, const struct sr_channel_group cg)
	200	{
	201	struct dev_context *devc;
	202
	203	(void)cg;
	204
	205	if (!sdi)
	206	return SR_ERR_ARG;
	207
	208	devc = sdi->priv;
	209
	210	switch (key) {
	211	case SR_CONF_SAMPLERATE:
	212	*data = g_variant_new_uint64(devc->cur_samplerate);
	213	break;
	214	case SR_CONF_CAPTURE_RATIO:
	215	*data = g_variant_new_uint64(devc->capture_ratio);
	216	break;
	217	case SR_CONF_LIMIT_SAMPLES:
	218	*data = g_variant_new_uint64(devc->limit_samples);
	219	break;
	220	case SR_CONF_PATTERN_MODE:
	221	if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE)
	222	*data = g_variant_new_string(STR_PATTERN_EXTERNAL);
	223	else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE)
	224	*data = g_variant_new_string(STR_PATTERN_INTERNAL);
	225	else
	226	*data = g_variant_new_string(STR_PATTERN_NONE);
	227	break;
	228	case SR_CONF_RLE:
	229	*data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE);
	230	break;
	231	case SR_CONF_EXTERNAL_CLOCK:
	232	*data = g_variant_new_boolean(devc->flag_reg & FLAG_CLOCK_EXTERNAL ? TRUE : FALSE);
	233	break;
	234	default:
	235	return SR_ERR_NA;
	236	}
	237
	238	return SR_OK;
	239	}
	240
	241	static int config_set(uint32_t key, GVariant *data,
	242	const struct sr_dev_inst sdi, const struct sr_channel_group cg)
	243	{
	244	struct dev_context *devc;
	245	uint16_t flag;
	246	uint64_t tmp_u64;
	247	const char *stropt;
	248
	249	(void)cg;
	250
	251	devc = sdi->priv;
	252
	253	switch (key) {
	254	case SR_CONF_SAMPLERATE:
	255	tmp_u64 = g_variant_get_uint64(data);
	256	if (tmp_u64 < samplerates[0] \|\| tmp_u64 > samplerates[1])
	257	return SR_ERR_SAMPLERATE;
	258	return p_ols_set_samplerate(sdi, g_variant_get_uint64(data));
	259	case SR_CONF_LIMIT_SAMPLES:
	260	tmp_u64 = g_variant_get_uint64(data);
	261	if (tmp_u64 < MIN_NUM_SAMPLES)
	262	return SR_ERR;
	263	devc->limit_samples = tmp_u64;
	264	break;
	265	case SR_CONF_CAPTURE_RATIO:
	266	devc->capture_ratio = g_variant_get_uint64(data);
	267	break;
	268	case SR_CONF_EXTERNAL_CLOCK:
	269	if (g_variant_get_boolean(data)) {
	270	sr_info("Enabling external clock.");
	271	devc->flag_reg \|= FLAG_CLOCK_EXTERNAL;
	272	} else {
	273	sr_info("Disabled external clock.");
	274	devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL;
	275	}
	276	break;
	277	case SR_CONF_PATTERN_MODE:
	278	stropt = g_variant_get_string(data, NULL);
	279	if (!strcmp(stropt, STR_PATTERN_NONE)) {
	280	sr_info("Disabling test modes.");
	281	flag = 0x0000;
	282	} else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) {
	283	sr_info("Enabling internal test mode.");
	284	flag = FLAG_INTERNAL_TEST_MODE;
	285	} else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) {
	286	sr_info("Enabling external test mode.");
	287	flag = FLAG_EXTERNAL_TEST_MODE;
	288	} else {
	289	return SR_ERR;
	290	}
	291	devc->flag_reg &= ~FLAG_INTERNAL_TEST_MODE;
	292	devc->flag_reg &= ~FLAG_EXTERNAL_TEST_MODE;
	293	devc->flag_reg \|= flag;
	294	break;
	295	case SR_CONF_SWAP:
	296	if (g_variant_get_boolean(data)) {
	297	sr_info("Enabling channel swapping.");
	298	devc->flag_reg \|= FLAG_SWAP_CHANNELS;
	299	} else {
	300	sr_info("Disabling channel swapping.");
	301	devc->flag_reg &= ~FLAG_SWAP_CHANNELS;
	302	}
	303	break;
	304	case SR_CONF_RLE:
	305	if (g_variant_get_boolean(data)) {
	306	sr_info("Enabling RLE.");
	307	devc->flag_reg \|= FLAG_RLE;
	308	} else {
	309	sr_info("Disabling RLE.");
	310	devc->flag_reg &= ~FLAG_RLE;
	311	}
	312	break;
	313	default:
	314	return SR_ERR_NA;
	315	}
	316
	317	return SR_OK;
	318	}
	319
	320	static int config_list(uint32_t key, GVariant **data,
	321	const struct sr_dev_inst sdi, const struct sr_channel_group cg)
	322	{
	323	struct dev_context *devc;
	324	int num_pols_changrp, i;
	325
	326	switch (key) {
	327	case SR_CONF_DEVICE_OPTIONS:
	328	return STD_CONFIG_LIST(key, data, sdi, cg, NO_OPTS, drvopts, devopts);
	329	case SR_CONF_SAMPLERATE:
	330	*data = std_gvar_samplerates_steps(ARRAY_AND_SIZE(samplerates));
	331	break;
	332	case SR_CONF_TRIGGER_MATCH:
	333	*data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
	334	break;
	335	case SR_CONF_PATTERN_MODE:
	336	*data = g_variant_new_strv(ARRAY_AND_SIZE(patterns));
	337	break;
	338	case SR_CONF_LIMIT_SAMPLES:
	339	if (!sdi)
	340	return SR_ERR_ARG;
	341	devc = sdi->priv;
	342	if (devc->flag_reg & FLAG_RLE)
	343	return SR_ERR_NA;
	344	if (devc->max_samplebytes == 0)
	345	/* Device didn't specify sample memory size in metadata. */
	346	return SR_ERR_NA;
	347	/*
	348	* Channel groups are turned off if no channels in that group are
	349	* enabled, making more room for samples for the enabled group.
	350	*/
	351	pols_channel_mask(sdi);
	352	num_pols_changrp = 0;
	353	for (i = 0; i < 4; i++) {
	354	if (devc->channel_mask & (0xff << (i * 8)))
	355	num_pols_changrp++;
	356	}
	357	/* 3 channel groups takes as many bytes as 4 channel groups */
	358	if (num_pols_changrp == 3)
	359	num_pols_changrp = 4;
	360
	361	*data = std_gvar_tuple_u64(MIN_NUM_SAMPLES,
	362	(num_pols_changrp) ? devc->max_samplebytes / num_pols_changrp : MIN_NUM_SAMPLES);
	363	break;
	364	default:
	365	return SR_ERR_NA;
	366	}
	367
	368	return SR_OK;
	369	}
	370
	371	static int dev_open(struct sr_dev_inst *sdi)
	372	{
	373	struct dev_context *devc;
	374
	375	devc = sdi->priv;
	376
	377	return p_ols_open(devc);
	378	}
	379
	380	static int dev_close(struct sr_dev_inst *sdi)
	381	{
	382	struct dev_context *devc;
	383
	384	devc = sdi->priv;
	385
	386	return p_ols_close(devc);
	387	}
	388
	389	static int set_trigger(const struct sr_dev_inst *sdi, int stage)
	390	{
	391	struct dev_context *devc;
	392	uint8_t cmd, arg[4];
	393
	394	devc = sdi->priv;
	395
	396	cmd = CMD_SET_TRIGGER_MASK + stage * 4;
	397	arg[0] = devc->trigger_mask[stage] & 0xff;
	398	arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff;
	399	arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff;
	400	arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff;
	401	if (write_longcommand(devc, cmd, arg) != SR_OK)
	402	return SR_ERR;
	403
	404	cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
	405	arg[0] = devc->trigger_value[stage] & 0xff;
	406	arg[1] = (devc->trigger_value[stage] >> 8) & 0xff;
	407	arg[2] = (devc->trigger_value[stage] >> 16) & 0xff;
	408	arg[3] = (devc->trigger_value[stage] >> 24) & 0xff;
	409	if (write_longcommand(devc, cmd, arg) != SR_OK)
	410	return SR_ERR;
	411
	412	cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
	413	arg[0] = arg[1] = arg[3] = 0x00;
	414	arg[2] = stage;
	415	if (stage == devc->num_stages)
	416	/* Last stage, fire when this one matches. */
	417	arg[3] \|= TRIGGER_START;
	418	if (write_longcommand(devc, cmd, arg) != SR_OK)
	419	return SR_ERR;
	420
	421	cmd = CMD_SET_TRIGGER_EDGE + stage * 4;
	422	arg[0] = devc->trigger_edge[stage] & 0xff;
	423	arg[1] = (devc->trigger_edge[stage] >> 8) & 0xff;
	424	arg[2] = (devc->trigger_edge[stage] >> 16) & 0xff;
	425	arg[3] = (devc->trigger_edge[stage] >> 24) & 0xff;
	426	if (write_longcommand(devc, cmd, arg) != SR_OK)
	427	return SR_ERR;
	428
	429	return SR_OK;
	430	}
	431
	432	static int disable_trigger(const struct sr_dev_inst *sdi, int stage)
	433	{
	434	struct dev_context *devc;
	435	uint8_t cmd, arg[4];
	436
	437	devc = sdi->priv;
	438
	439	cmd = CMD_SET_TRIGGER_MASK + stage * 4;
	440	arg[0] = arg[1] = arg[2] = arg[3] = 0x00;
	441	if (write_longcommand(devc, cmd, arg) != SR_OK)
	442	return SR_ERR;
	443
	444	cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
	445	if (write_longcommand(devc, cmd, arg) != SR_OK)
	446	return SR_ERR;
	447
	448	cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
	449	arg[2] = 0x03;
	450	if (write_longcommand(devc, cmd, arg) != SR_OK)
	451	return SR_ERR;
	452
	453	cmd = CMD_SET_TRIGGER_EDGE + stage * 4;
	454	arg[2] = 0x00;
	455	if (write_longcommand(devc, cmd, arg) != SR_OK)
	456	return SR_ERR;
	457
	458	return SR_OK;
	459	}
	460
	461	static int dev_acquisition_start(const struct sr_dev_inst *sdi)
	462	{
	463	struct dev_context *devc;
	464	uint32_t samplecount, readcount, delaycount;
	465	uint8_t pols_changrp_mask, arg[4];
	466	uint16_t flag_tmp;
	467	int num_pols_changrp, samplespercount;
	468	int ret, i;
	469
	470	devc = sdi->priv;
	471
	472	pols_channel_mask(sdi);
	473
	474	/*
	475	* Enable/disable channel groups in the flag register according to the
	476	* channel mask. Calculate this here, because num_pols_changrp is
	477	* needed to limit readcount.
	478	*/
	479	pols_changrp_mask = 0;
	480	num_pols_changrp = 0;
	481	for (i = 0; i < 4; i++) {
	482	if (devc->channel_mask & (0xff << (i * 8))) {
	483	pols_changrp_mask \|= (1 << i);
	484	num_pols_changrp++;
	485	}
	486	}
	487	/* 3 channel groups takes as many bytes as 4 channel groups */
	488	if (num_pols_changrp == 3)
	489	num_pols_changrp = 4;
	490	/* maximum number of samples (or RLE counts) the buffer memory can hold */
	491	devc->max_samples = devc->max_samplebytes / num_pols_changrp;
	492
	493	/*
	494	* Limit readcount to prevent reading past the end of the hardware
	495	* buffer.
	496	*/
	497	sr_dbg("max_samples = %d", devc->max_samples);
	498	sr_dbg("limit_samples = %" PRIu64, devc->limit_samples);
	499	samplecount = MIN(devc->max_samples, devc->limit_samples);
	500	sr_dbg("Samplecount = %d", samplecount);
	501
	502	/* In demux mode the OLS is processing two samples per clock */
	503	if (devc->flag_reg & FLAG_DEMUX) {
	504	samplespercount = 8;
	505	}
	506	else {
	507	samplespercount = 4;
	508	}
	509
	510	readcount = samplecount / samplespercount;
	511
	512	/* Rather read too many samples than too few. */
	513	if (samplecount % samplespercount != 0)
	514	readcount++;
	515
	516	/* Basic triggers. */
	517	if (pols_convert_trigger(sdi) != SR_OK) {
	518	sr_err("Failed to configure channels.");
	519	return SR_ERR;
	520	}
	521
	522	if (devc->num_stages > 0) {
	523	delaycount = readcount * (1 - devc->capture_ratio / 100.0);
	524	devc->trigger_at = (readcount - delaycount) * samplespercount - devc->num_stages;
	525	for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
	526	if (i <= devc->num_stages) {
	527	sr_dbg("Setting p-ols stage %d trigger.", i);
	528	if ((ret = set_trigger(sdi, i)) != SR_OK)
	529	return ret;
	530	}
	531	else {
	532	sr_dbg("Disabling p-ols stage %d trigger.", i);
	533	if ((ret = disable_trigger(sdi, i)) != SR_OK)
	534	return ret;
	535	}
	536	}
	537	} else {
	538	/* No triggers configured, force trigger on first stage. */
	539	sr_dbg("Forcing trigger at stage 0.");
	540	if ((ret = set_trigger(sdi, 0)) != SR_OK)
	541	return ret;
	542	delaycount = readcount;
	543	}
	544
	545	/* Samplerate. */
	546	sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
	547	devc->cur_samplerate, devc->cur_samplerate_divider);
	548	arg[0] = devc->cur_samplerate_divider & 0xff;
	549	arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8;
	550	arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16;
	551	arg[3] = 0x00;
	552	if (write_longcommand(devc, CMD_SET_DIVIDER, arg) != SR_OK)
	553	return SR_ERR;
	554
	555	/* Send extended sample limit and pre/post-trigger capture ratio. */
	556	arg[0] = ((readcount - 1) & 0xff);
	557	arg[1] = ((readcount - 1) & 0xff00) >> 8;
	558	arg[2] = ((readcount - 1) & 0xff0000) >> 16;
	559	arg[3] = ((readcount - 1) & 0xff000000) >> 24;
	560	if (write_longcommand(devc, CMD_CAPTURE_DELAY, arg) != SR_OK)
	561	return SR_ERR;
	562	arg[0] = ((delaycount - 1) & 0xff);
	563	arg[1] = ((delaycount - 1) & 0xff00) >> 8;
	564	arg[2] = ((delaycount - 1) & 0xff0000) >> 16;
	565	arg[3] = ((delaycount - 1) & 0xff000000) >> 24;
	566	if (write_longcommand(devc, CMD_CAPTURE_COUNT, arg) != SR_OK)
	567	return SR_ERR;
	568
	569	/* Flag register. */
	570	sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
	571	devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off",
	572	devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off",
	573	devc->flag_reg & FLAG_RLE ? "on" : "off",
	574	devc->flag_reg & FLAG_FILTER ? "on": "off",
	575	devc->flag_reg & FLAG_DEMUX ? "on" : "off");
	576
	577	/*
	578	* Enable/disable OLS channel groups in the flag register according
	579	* to the channel mask. 1 means "disable channel".
	580	*/
	581	devc->flag_reg &= ~0x3c;
	582	devc->flag_reg \|= ~(pols_changrp_mask << 2) & 0x3c;
	583	sr_dbg("flag_reg = %x", devc->flag_reg);
	584
	585	/*
	586	* In demux mode the OLS is processing two 8-bit or 16-bit samples
	587	* in parallel and for this to work the lower two bits of the four
	588	* "channel_disable" bits must be replicated to the upper two bits.
	589	*/
	590	flag_tmp = devc->flag_reg;
	591	if (devc->flag_reg & FLAG_DEMUX) {
	592	flag_tmp &= ~0x30;
	593	flag_tmp \|= ~(pols_changrp_mask << 4) & 0x30;
	594	}
	595	arg[0] = flag_tmp & 0xff;
	596	arg[1] = flag_tmp >> 8;
	597	arg[2] = arg[3] = 0x00;
	598	if (write_longcommand(devc, CMD_SET_FLAGS, arg) != SR_OK)
	599	return SR_ERR;
	600
	601	/* Start acquisition on the device. */
	602	if (write_shortcommand(devc, CMD_RUN) != SR_OK)
	603	return SR_ERR;
	604
	605	/* Reset all operational states. */
	606	devc->rle_count = devc->num_transfers = 0;
	607	devc->num_samples = devc->num_bytes = 0;
	608	devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0;
	609	memset(devc->sample, 0, 4);
	610
	611	std_session_send_df_header(sdi);
	612
	613	/* Hook up a dummy handler to receive data from the device. */
	614	sr_session_source_add(sdi->session, -1, 0, 10, p_ols_receive_data,
	615	(struct sr_dev_inst *)sdi);
	616
	617	return SR_OK;
	618	}
	619
	620	static int dev_acquisition_stop(struct sr_dev_inst *sdi)
	621	{
	622	struct dev_context *devc;
	623
	624	devc = sdi->priv;
	625
	626	write_shortcommand(devc, CMD_RESET);
	627	write_shortcommand(devc, CMD_RESET);
	628	write_shortcommand(devc, CMD_RESET);
	629	write_shortcommand(devc, CMD_RESET);
	630	write_shortcommand(devc, CMD_RESET);
	631
	632	sr_session_source_remove(sdi->session, -1);
	633
	634	std_session_send_df_end(sdi);
	635
	636	return SR_OK;
	637	}
	638
	639	SR_PRIV struct sr_dev_driver p_ols_driver_info = {
	640	.name = "p-ols",
	641	.longname = "Pipistrello OLS",
	642	.api_version = 1,
	643	.init = std_init,
	644	.cleanup = std_cleanup,
	645	.scan = scan,
	646	.dev_list = std_dev_list,
	647	.dev_clear = dev_clear,
	648	.config_get = config_get,
	649	.config_set = config_set,
	650	.config_list = config_list,
	651	.dev_open = dev_open,
	652	.dev_close = dev_close,
	653	.dev_acquisition_start = dev_acquisition_start,
	654	.dev_acquisition_stop = dev_acquisition_stop,
	655	.context = NULL,
	656	};
	657	SR_REGISTER_DEV_DRIVER(p_ols_driver_info);