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1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de> | |
5 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
6 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
7 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
8 | * | |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <config.h> | |
24 | ||
25 | #include <libsigrok/libsigrok.h> | |
26 | #include <string.h> | |
27 | ||
28 | #include "libsigrok-internal.h" | |
29 | #include "protocol.h" | |
30 | ||
31 | #define UC_FIRMWARE "kingst-la-%04x.fw" | |
32 | #define FPGA_FW_LA2016 "kingst-la2016-fpga.bitstream" | |
33 | #define FPGA_FW_LA2016A "kingst-la2016a1-fpga.bitstream" | |
34 | #define FPGA_FW_LA1016 "kingst-la1016-fpga.bitstream" | |
35 | #define FPGA_FW_LA1016A "kingst-la1016a1-fpga.bitstream" | |
36 | ||
37 | #define MAX_SAMPLE_RATE_LA2016 SR_MHZ(200) | |
38 | #define MAX_SAMPLE_RATE_LA1016 SR_MHZ(100) | |
39 | #define MAX_SAMPLE_DEPTH 10e9 | |
40 | #define MAX_PWM_FREQ SR_MHZ(20) | |
41 | #define PWM_CLOCK SR_MHZ(200) /* 200MHz for both LA2016 and LA1016 */ | |
42 | ||
43 | /* usb vendor class control requests to the cypress FX2 microcontroller */ | |
44 | #define CMD_FPGA_ENABLE 0x10 | |
45 | #define CMD_FPGA_SPI 0x20 /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */ | |
46 | #define CMD_BULK_START 0x30 /* begin transfer of capture data via usb endpoint 6 IN */ | |
47 | #define CMD_BULK_RESET 0x38 /* flush FX2 usb endpoint 6 IN fifos */ | |
48 | #define CMD_FPGA_INIT 0x50 /* used before and after FPGA bitstream loading */ | |
49 | #define CMD_KAUTH 0x60 /* communicate with authentication ic U10, not used */ | |
50 | #define CMD_EEPROM 0xa2 /* ctrl_in reads, ctrl_out writes */ | |
51 | ||
52 | /* | |
53 | * fpga spi register addresses for control request CMD_FPGA_SPI: | |
54 | * There are around 60 byte-wide registers within the fpga and | |
55 | * these are the base addresses used for accessing them. | |
56 | * On the spi bus, the msb of the address byte is set for read | |
57 | * and cleared for write, but that is handled by the fx2 mcu | |
58 | * as appropriate. In this driver code just use IN transactions | |
59 | * to read, OUT to write. | |
60 | */ | |
61 | #define REG_RUN 0x00 /* read capture status, write capture start */ | |
62 | #define REG_PWM_EN 0x02 /* user pwm channels on/off */ | |
63 | #define REG_CAPT_MODE 0x03 /* set to 0x00 for capture to sdram, 0x01 bypass sdram for streaming */ | |
64 | #define REG_BULK 0x08 /* write start address and number of bytes for capture data bulk upload */ | |
65 | #define REG_SAMPLING 0x10 /* write capture config, read capture data location in sdram */ | |
66 | #define REG_TRIGGER 0x20 /* write level and edge trigger config */ | |
67 | #define REG_THRESHOLD 0x68 /* write two pwm configs to control input threshold dac */ | |
68 | #define REG_PWM1 0x70 /* write config for user pwm1 */ | |
69 | #define REG_PWM2 0x78 /* write config for user pwm2 */ | |
70 | ||
71 | static int ctrl_in(const struct sr_dev_inst *sdi, | |
72 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, | |
73 | void *data, uint16_t wLength) | |
74 | { | |
75 | struct sr_usb_dev_inst *usb; | |
76 | int ret; | |
77 | ||
78 | usb = sdi->conn; | |
79 | ||
80 | if ((ret = libusb_control_transfer( | |
81 | usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, | |
82 | bRequest, wValue, wIndex, (unsigned char *)data, wLength, | |
83 | DEFAULT_TIMEOUT_MS)) != wLength) { | |
84 | sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.", | |
85 | wLength, bRequest, wValue, wIndex, | |
86 | libusb_error_name(ret)); | |
87 | sr_err("Cannot read %d bytes from USB: %s.", | |
88 | wLength, libusb_error_name(ret)); | |
89 | return SR_ERR; | |
90 | } | |
91 | ||
92 | return SR_OK; | |
93 | } | |
94 | ||
95 | static int ctrl_out(const struct sr_dev_inst *sdi, | |
96 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, | |
97 | void *data, uint16_t wLength) | |
98 | { | |
99 | struct sr_usb_dev_inst *usb; | |
100 | int ret; | |
101 | ||
102 | usb = sdi->conn; | |
103 | ||
104 | if ((ret = libusb_control_transfer( | |
105 | usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, | |
106 | bRequest, wValue, wIndex, (unsigned char*)data, wLength, | |
107 | DEFAULT_TIMEOUT_MS)) != wLength) { | |
108 | sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.", | |
109 | wLength, bRequest, wValue, wIndex, | |
110 | libusb_error_name(ret)); | |
111 | sr_err("Cannot write %d bytes to USB: %s.", | |
112 | wLength, libusb_error_name(ret)); | |
113 | return SR_ERR; | |
114 | } | |
115 | ||
116 | return SR_OK; | |
117 | } | |
118 | ||
119 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, const char *bitstream_fname) | |
120 | { | |
121 | struct dev_context *devc; | |
122 | struct drv_context *drvc; | |
123 | struct sr_usb_dev_inst *usb; | |
124 | struct sr_resource bitstream; | |
125 | uint8_t buffer[sizeof(uint32_t)]; | |
126 | uint8_t *wrptr; | |
127 | uint8_t cmd_resp; | |
128 | uint8_t block[4096]; | |
129 | int len, act_len; | |
130 | unsigned int pos; | |
131 | int ret; | |
132 | unsigned int zero_pad_to = 0x2c000; | |
133 | ||
134 | devc = sdi->priv; | |
135 | drvc = sdi->driver->context; | |
136 | usb = sdi->conn; | |
137 | ||
138 | sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname); | |
139 | ||
140 | ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, bitstream_fname); | |
141 | if (ret != SR_OK) { | |
142 | sr_err("Cannot find FPGA bitstream %s.", bitstream_fname); | |
143 | return ret; | |
144 | } | |
145 | ||
146 | devc->bitstream_size = (uint32_t)bitstream.size; | |
147 | wrptr = buffer; | |
148 | write_u32le_inc(&wrptr, devc->bitstream_size); | |
149 | if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) { | |
150 | sr_err("Cannot initiate FPGA bitstream upload."); | |
151 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
152 | return ret; | |
153 | } | |
154 | ||
155 | pos = 0; | |
156 | while (1) { | |
157 | if (pos < bitstream.size) { | |
158 | len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, &block, sizeof(block)); | |
159 | if (len < 0) { | |
160 | sr_err("Cannot read FPGA bitstream."); | |
161 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
162 | return SR_ERR; | |
163 | } | |
164 | } else { | |
165 | // fill with zero's until zero_pad_to | |
166 | len = zero_pad_to - pos; | |
167 | if ((unsigned)len > sizeof(block)) | |
168 | len = sizeof(block); | |
169 | memset(&block, 0, len); | |
170 | } | |
171 | if (len == 0) | |
172 | break; | |
173 | ||
174 | ret = libusb_bulk_transfer(usb->devhdl, 2, (unsigned char*)&block[0], len, &act_len, DEFAULT_TIMEOUT_MS); | |
175 | if (ret != 0) { | |
176 | sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.", | |
177 | pos, (int)len, libusb_error_name(ret)); | |
178 | ret = SR_ERR; | |
179 | break; | |
180 | } | |
181 | if (act_len != len) { | |
182 | sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.", | |
183 | pos, (int)len, act_len); | |
184 | ret = SR_ERR; | |
185 | break; | |
186 | } | |
187 | pos += len; | |
188 | } | |
189 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
190 | if (ret != 0) | |
191 | return ret; | |
192 | sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", | |
193 | bitstream.size); | |
194 | ||
195 | if ((ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) { | |
196 | sr_err("Cannot read response after FPGA bitstream upload."); | |
197 | return ret; | |
198 | } | |
199 | if (cmd_resp != 0) { | |
200 | sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.", | |
201 | cmd_resp); | |
202 | return SR_ERR; | |
203 | } | |
204 | ||
205 | g_usleep(30000); | |
206 | ||
207 | if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0)) != SR_OK) { | |
208 | sr_err("Cannot enable FPGA after bitstream upload."); | |
209 | return ret; | |
210 | } | |
211 | ||
212 | g_usleep(40000); | |
213 | return SR_OK; | |
214 | } | |
215 | ||
216 | static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) | |
217 | { | |
218 | struct dev_context *devc; | |
219 | int ret; | |
220 | ||
221 | devc = sdi->priv; | |
222 | ||
223 | uint16_t duty_R79,duty_R56; | |
224 | uint8_t buf[2 * sizeof(uint16_t)]; | |
225 | uint8_t *wrptr; | |
226 | ||
227 | /* clamp threshold setting within valid range for LA2016 */ | |
228 | if (voltage > 4.0) { | |
229 | voltage = 4.0; | |
230 | } | |
231 | else if (voltage < -4.0) { | |
232 | voltage = -4.0; | |
233 | } | |
234 | ||
235 | /* | |
236 | * The fpga has two programmable pwm outputs which feed a dac that | |
237 | * is used to adjust input offset. The dac changes the input | |
238 | * swing around the fixed fpga input threshold. | |
239 | * The two pwm outputs can be seen on R79 and R56 respectvely. | |
240 | * Frequency is fixed at 100kHz and duty is varied. | |
241 | * The R79 pwm uses just three settings. | |
242 | * The R56 pwm varies with required threshold and its behaviour | |
243 | * also changes depending on the setting of R79 PWM. | |
244 | */ | |
245 | ||
246 | /* | |
247 | * calculate required pwm duty register values from requested threshold voltage | |
248 | * see last page of schematic (on wiki) for an explanation of these numbers | |
249 | */ | |
250 | if (voltage >= 2.9) { | |
251 | duty_R79 = 0; /* this pwm is off (0V)*/ | |
252 | duty_R56 = (uint16_t)(302 * voltage - 363); | |
253 | } | |
254 | else if (voltage <= -0.4) { | |
255 | duty_R79 = 0x02D7; /* 72% duty */ | |
256 | duty_R56 = (uint16_t)(302 * voltage + 1090); | |
257 | } | |
258 | else { | |
259 | duty_R79 = 0x00f2; /* 25% duty */ | |
260 | duty_R56 = (uint16_t)(302 * voltage + 121); | |
261 | } | |
262 | ||
263 | /* clamp duty register values at sensible limits */ | |
264 | if (duty_R56 < 10) { | |
265 | duty_R56 = 10; | |
266 | } | |
267 | else if (duty_R56 > 1100) { | |
268 | duty_R56 = 1100; | |
269 | } | |
270 | ||
271 | sr_dbg("Set threshold voltage %.2fV.", voltage); | |
272 | sr_dbg("Duty cycle values: R56 0x%04x, R79 0x%04x.", duty_R56, duty_R79); | |
273 | ||
274 | wrptr = buf; | |
275 | write_u16le_inc(&wrptr, duty_R56); | |
276 | write_u16le_inc(&wrptr, duty_R79); | |
277 | ||
278 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf); | |
279 | if (ret != SR_OK) { | |
280 | sr_err("Cannot set threshold voltage %.2fV.", voltage); | |
281 | return ret; | |
282 | } | |
283 | devc->threshold_voltage = voltage; | |
284 | ||
285 | return SR_OK; | |
286 | } | |
287 | ||
288 | static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2) | |
289 | { | |
290 | struct dev_context *devc; | |
291 | uint8_t cfg; | |
292 | int ret; | |
293 | ||
294 | devc = sdi->priv; | |
295 | cfg = 0; | |
296 | ||
297 | if (p1) cfg |= 1 << 0; | |
298 | if (p2) cfg |= 1 << 1; | |
299 | ||
300 | sr_dbg("Set PWM enable %d %d. Config 0x%02x.", p1, p2, cfg); | |
301 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg)); | |
302 | if (ret != SR_OK) { | |
303 | sr_err("Cannot setup PWM enabled state."); | |
304 | return ret; | |
305 | } | |
306 | devc->pwm_setting[0].enabled = (p1) ? 1 : 0; | |
307 | devc->pwm_setting[1].enabled = (p2) ? 1 : 0; | |
308 | ||
309 | return SR_OK; | |
310 | } | |
311 | ||
312 | static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, float duty) | |
313 | { | |
314 | int CTRL_PWM[] = { REG_PWM1, REG_PWM2 }; | |
315 | struct dev_context *devc; | |
316 | pwm_setting_dev_t cfg; | |
317 | pwm_setting_t *setting; | |
318 | int ret; | |
319 | uint8_t buf[2 * sizeof(uint32_t)]; | |
320 | uint8_t *wrptr; | |
321 | ||
322 | devc = sdi->priv; | |
323 | ||
324 | if (which < 1 || which > 2) { | |
325 | sr_err("Invalid PWM channel: %d.", which); | |
326 | return SR_ERR; | |
327 | } | |
328 | if (freq > MAX_PWM_FREQ) { | |
329 | sr_err("Too high a PWM frequency: %.1f.", freq); | |
330 | return SR_ERR; | |
331 | } | |
332 | if (duty > 100 || duty < 0) { | |
333 | sr_err("Invalid PWM duty cycle: %f.", duty); | |
334 | return SR_ERR; | |
335 | } | |
336 | ||
337 | cfg.period = (uint32_t)(PWM_CLOCK / freq); | |
338 | cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.)); | |
339 | sr_dbg("Set PWM%d period %d, duty %d.", which, cfg.period, cfg.duty); | |
340 | ||
341 | wrptr = buf; | |
342 | write_u32le_inc(&wrptr, cfg.period); | |
343 | write_u32le_inc(&wrptr, cfg.duty); | |
344 | ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM[which - 1], 0, buf, wrptr - buf); | |
345 | if (ret != SR_OK) { | |
346 | sr_err("Cannot setup PWM%d configuration %d %d.", | |
347 | which, cfg.period, cfg.duty); | |
348 | return ret; | |
349 | } | |
350 | setting = &devc->pwm_setting[which - 1]; | |
351 | setting->freq = freq; | |
352 | setting->duty = duty; | |
353 | ||
354 | return SR_OK; | |
355 | } | |
356 | ||
357 | static int set_defaults(const struct sr_dev_inst *sdi) | |
358 | { | |
359 | struct dev_context *devc; | |
360 | int ret; | |
361 | ||
362 | devc = sdi->priv; | |
363 | ||
364 | devc->capture_ratio = 5; /* percent */ | |
365 | devc->cur_channels = 0xffff; | |
366 | devc->limit_samples = 5000000; | |
367 | devc->cur_samplerate = SR_MHZ(100); | |
368 | ||
369 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); | |
370 | if (ret) | |
371 | return ret; | |
372 | ||
373 | ret = enable_pwm(sdi, 0, 0); | |
374 | if (ret) | |
375 | return ret; | |
376 | ||
377 | ret = set_pwm(sdi, 1, 1e3, 50); | |
378 | if (ret) | |
379 | return ret; | |
380 | ||
381 | ret = set_pwm(sdi, 2, 100e3, 50); | |
382 | if (ret) | |
383 | return ret; | |
384 | ||
385 | ret = enable_pwm(sdi, 1, 1); | |
386 | if (ret) | |
387 | return ret; | |
388 | ||
389 | return SR_OK; | |
390 | } | |
391 | ||
392 | static int set_trigger_config(const struct sr_dev_inst *sdi) | |
393 | { | |
394 | struct dev_context *devc; | |
395 | struct sr_trigger *trigger; | |
396 | trigger_cfg_t cfg; | |
397 | GSList *stages; | |
398 | GSList *channel; | |
399 | struct sr_trigger_stage *stage1; | |
400 | struct sr_trigger_match *match; | |
401 | uint16_t ch_mask; | |
402 | int ret; | |
403 | uint8_t buf[4 * sizeof(uint32_t)]; | |
404 | uint8_t *wrptr; | |
405 | ||
406 | devc = sdi->priv; | |
407 | trigger = sr_session_trigger_get(sdi->session); | |
408 | ||
409 | memset(&cfg, 0, sizeof(cfg)); | |
410 | ||
411 | cfg.channels = devc->cur_channels; | |
412 | ||
413 | if (trigger && trigger->stages) { | |
414 | stages = trigger->stages; | |
415 | stage1 = stages->data; | |
416 | if (stages->next) { | |
417 | sr_err("Only one trigger stage supported for now."); | |
418 | return SR_ERR; | |
419 | } | |
420 | channel = stage1->matches; | |
421 | while (channel) { | |
422 | match = channel->data; | |
423 | ch_mask = 1 << match->channel->index; | |
424 | ||
425 | switch (match->match) { | |
426 | case SR_TRIGGER_ZERO: | |
427 | cfg.level |= ch_mask; | |
428 | cfg.high_or_falling &= ~ch_mask; | |
429 | break; | |
430 | case SR_TRIGGER_ONE: | |
431 | cfg.level |= ch_mask; | |
432 | cfg.high_or_falling |= ch_mask; | |
433 | break; | |
434 | case SR_TRIGGER_RISING: | |
435 | if ((cfg.enabled & ~cfg.level)) { | |
436 | sr_err("Device only supports one edge trigger."); | |
437 | return SR_ERR; | |
438 | } | |
439 | cfg.level &= ~ch_mask; | |
440 | cfg.high_or_falling &= ~ch_mask; | |
441 | break; | |
442 | case SR_TRIGGER_FALLING: | |
443 | if ((cfg.enabled & ~cfg.level)) { | |
444 | sr_err("Device only supports one edge trigger."); | |
445 | return SR_ERR; | |
446 | } | |
447 | cfg.level &= ~ch_mask; | |
448 | cfg.high_or_falling |= ch_mask; | |
449 | break; | |
450 | default: | |
451 | sr_err("Unknown trigger condition."); | |
452 | return SR_ERR; | |
453 | } | |
454 | cfg.enabled |= ch_mask; | |
455 | channel = channel->next; | |
456 | } | |
457 | } | |
458 | sr_dbg("Set trigger config: " | |
459 | "channels 0x%04x, trigger-enabled 0x%04x, " | |
460 | "level-triggered 0x%04x, high/falling 0x%04x.", | |
461 | cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling); | |
462 | ||
463 | devc->had_triggers_configured = cfg.enabled != 0; | |
464 | ||
465 | wrptr = buf; | |
466 | write_u32le_inc(&wrptr, cfg.channels); | |
467 | write_u32le_inc(&wrptr, cfg.enabled); | |
468 | write_u32le_inc(&wrptr, cfg.level); | |
469 | write_u32le_inc(&wrptr, cfg.high_or_falling); | |
470 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf); | |
471 | if (ret != SR_OK) { | |
472 | sr_err("Cannot setup trigger configuration."); | |
473 | return ret; | |
474 | } | |
475 | ||
476 | return SR_OK; | |
477 | } | |
478 | ||
479 | static int set_sample_config(const struct sr_dev_inst *sdi) | |
480 | { | |
481 | struct dev_context *devc; | |
482 | double clock_divisor; | |
483 | uint64_t total; | |
484 | int ret; | |
485 | uint16_t divisor; | |
486 | uint8_t buf[2 * sizeof(uint32_t) + 48 / 8 + sizeof(uint16_t)]; | |
487 | uint8_t *wrptr; | |
488 | ||
489 | devc = sdi->priv; | |
490 | total = 128 * 1024 * 1024; | |
491 | ||
492 | if (devc->cur_samplerate > devc->max_samplerate) { | |
493 | sr_err("Too high a sample rate: %" PRIu64 ".", | |
494 | devc->cur_samplerate); | |
495 | return SR_ERR; | |
496 | } | |
497 | ||
498 | clock_divisor = devc->max_samplerate / (double)devc->cur_samplerate; | |
499 | if (clock_divisor > 0xffff) | |
500 | clock_divisor = 0xffff; | |
501 | divisor = (uint16_t)(clock_divisor + 0.5); | |
502 | devc->cur_samplerate = devc->max_samplerate / divisor; | |
503 | ||
504 | if (devc->limit_samples > MAX_SAMPLE_DEPTH) { | |
505 | sr_err("Too high a sample depth: %" PRIu64 ".", | |
506 | devc->limit_samples); | |
507 | return SR_ERR; | |
508 | } | |
509 | ||
510 | devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100; | |
511 | ||
512 | sr_dbg("Set sample config: %" PRIu64 "kHz, %" PRIu64 " samples, trigger-pos %" PRIu64 "%%.", | |
513 | devc->cur_samplerate / 1000, | |
514 | devc->limit_samples, | |
515 | devc->capture_ratio); | |
516 | ||
517 | wrptr = buf; | |
518 | write_u32le_inc(&wrptr, devc->limit_samples); | |
519 | write_u8_inc(&wrptr, 0); | |
520 | write_u32le_inc(&wrptr, devc->pre_trigger_size); | |
521 | write_u32le_inc(&wrptr, ((total * devc->capture_ratio) / 100) & 0xFFFFFF00); | |
522 | write_u16le_inc(&wrptr, divisor); | |
523 | write_u8_inc(&wrptr, 0); | |
524 | ||
525 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf); | |
526 | if (ret != SR_OK) { | |
527 | sr_err("Cannot setup acquisition configuration."); | |
528 | return ret; | |
529 | } | |
530 | ||
531 | return SR_OK; | |
532 | } | |
533 | ||
534 | /* The run state is read from FPGA registers 1[hi-byte] and 0[lo-byte] | |
535 | * and the bits are interpreted as follows: | |
536 | * | |
537 | * register 0: | |
538 | * bit0 1= idle | |
539 | * bit1 1= writing to sdram | |
540 | * bit2 0= waiting_for_trigger 1=been_triggered | |
541 | * bit3 0= pretrigger_sampling 1=posttrigger_sampling | |
542 | * ...unknown... | |
543 | * register 1: | |
544 | * meaning of bits unknown (but vendor software reads this, so just do the same) | |
545 | * | |
546 | * The run state values occur in this order: | |
547 | * 0x85E2: pre-sampling (for samples before trigger position, capture ratio > 0%) | |
548 | * 0x85EA: pre-sampling complete, now waiting for trigger (whilst sampling continuously) | |
549 | * 0x85EE: running | |
550 | * 0x85ED: idle | |
551 | */ | |
552 | static uint16_t run_state(const struct sr_dev_inst *sdi) | |
553 | { | |
554 | uint16_t state; | |
555 | static uint16_t previous_state = 0; | |
556 | int ret; | |
557 | ||
558 | if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, &state, sizeof(state))) != SR_OK) { | |
559 | sr_err("Cannot read run state."); | |
560 | return ret; | |
561 | } | |
562 | ||
563 | /* This function is called about every 50ms. | |
564 | * To avoid filling the log file with redundant information during long captures, | |
565 | * just print a log message if status has changed. | |
566 | */ | |
567 | ||
568 | if (state != previous_state) { | |
569 | previous_state = state; | |
570 | if ((state & 0x0003) == 0x01) { | |
571 | sr_dbg("Run state: 0x%04x (%s).", state, "idle"); | |
572 | } | |
573 | else if ((state & 0x000f) == 0x02) { | |
574 | sr_dbg("Run state: 0x%04x (%s).", state, | |
575 | "pre-trigger sampling"); | |
576 | } | |
577 | else if ((state & 0x000f) == 0x0a) { | |
578 | sr_dbg("Run state: 0x%04x (%s).", state, | |
579 | "sampling, waiting for trigger"); | |
580 | } | |
581 | else if ((state & 0x000f) == 0x0e) { | |
582 | sr_dbg("Run state: 0x%04x (%s).", state, | |
583 | "post-trigger sampling"); | |
584 | } | |
585 | else { | |
586 | sr_dbg("Run state: 0x%04x.", state); | |
587 | } | |
588 | } | |
589 | ||
590 | return state; | |
591 | } | |
592 | ||
593 | static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t fast_blinking) | |
594 | { | |
595 | int ret; | |
596 | ||
597 | if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) { | |
598 | sr_err("Cannot configure run mode %d.", fast_blinking); | |
599 | return ret; | |
600 | } | |
601 | ||
602 | return SR_OK; | |
603 | } | |
604 | ||
605 | static int get_capture_info(const struct sr_dev_inst *sdi) | |
606 | { | |
607 | struct dev_context *devc; | |
608 | int ret; | |
609 | uint8_t buf[3 * sizeof(uint32_t)]; | |
610 | const uint8_t *rdptr; | |
611 | ||
612 | devc = sdi->priv; | |
613 | ||
614 | if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf))) != SR_OK) { | |
615 | sr_err("Cannot read capture info."); | |
616 | return ret; | |
617 | } | |
618 | ||
619 | rdptr = buf; | |
620 | devc->info.n_rep_packets = read_u32le_inc(&rdptr); | |
621 | devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr); | |
622 | devc->info.write_pos = read_u32le_inc(&rdptr); | |
623 | ||
624 | sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d.", | |
625 | devc->info.n_rep_packets, devc->info.n_rep_packets, | |
626 | devc->info.n_rep_packets_before_trigger, | |
627 | devc->info.n_rep_packets_before_trigger, | |
628 | devc->info.write_pos, devc->info.write_pos); | |
629 | ||
630 | if (devc->info.n_rep_packets % 5) { | |
631 | sr_warn("Unexpected packets count %lu, not a multiple of 5.", | |
632 | (unsigned long)devc->info.n_rep_packets); | |
633 | } | |
634 | ||
635 | return SR_OK; | |
636 | } | |
637 | ||
638 | SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id) | |
639 | { | |
640 | char fw_file[1024]; | |
641 | snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id); | |
642 | return ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file); | |
643 | } | |
644 | ||
645 | SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi) | |
646 | { | |
647 | struct dev_context *devc; | |
648 | int ret; | |
649 | uint8_t cmd; | |
650 | ||
651 | devc = sdi->priv; | |
652 | ||
653 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); | |
654 | if (ret != SR_OK) | |
655 | return ret; | |
656 | ||
657 | cmd = 0; | |
658 | if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd))) != SR_OK) { | |
659 | sr_err("Cannot send command to stop sampling."); | |
660 | return ret; | |
661 | } | |
662 | ||
663 | ret = set_trigger_config(sdi); | |
664 | if (ret != SR_OK) | |
665 | return ret; | |
666 | ||
667 | ret = set_sample_config(sdi); | |
668 | if (ret != SR_OK) | |
669 | return ret; | |
670 | ||
671 | return SR_OK; | |
672 | } | |
673 | ||
674 | SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) | |
675 | { | |
676 | int ret; | |
677 | ||
678 | ret = set_run_mode(sdi, 3); | |
679 | if (ret != SR_OK) | |
680 | return ret; | |
681 | ||
682 | return SR_OK; | |
683 | } | |
684 | ||
685 | static int la2016_stop_acquisition(const struct sr_dev_inst *sdi) | |
686 | { | |
687 | int ret; | |
688 | ||
689 | ret = set_run_mode(sdi, 0); | |
690 | if (ret != SR_OK) | |
691 | return ret; | |
692 | ||
693 | return SR_OK; | |
694 | } | |
695 | ||
696 | SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) | |
697 | { | |
698 | int ret; | |
699 | struct dev_context *devc; | |
700 | ||
701 | ret = la2016_stop_acquisition(sdi); | |
702 | if (ret != SR_OK) | |
703 | return ret; | |
704 | ||
705 | devc = sdi ? sdi->priv : NULL; | |
706 | if (devc && devc->transfer) | |
707 | libusb_cancel_transfer(devc->transfer); | |
708 | ||
709 | return SR_OK; | |
710 | } | |
711 | ||
712 | static int la2016_has_triggered(const struct sr_dev_inst *sdi) | |
713 | { | |
714 | uint16_t state; | |
715 | ||
716 | state = run_state(sdi); | |
717 | ||
718 | return (state & 0x3) == 1; | |
719 | } | |
720 | ||
721 | static int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb) | |
722 | { | |
723 | struct dev_context *devc; | |
724 | struct sr_usb_dev_inst *usb; | |
725 | int ret; | |
726 | uint8_t wrbuf[2 * sizeof(uint32_t)]; | |
727 | uint8_t *wrptr; | |
728 | uint32_t to_read; | |
729 | uint8_t *buffer; | |
730 | ||
731 | devc = sdi->priv; | |
732 | usb = sdi->conn; | |
733 | ||
734 | if ((ret = get_capture_info(sdi)) != SR_OK) | |
735 | return ret; | |
736 | ||
737 | devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK; | |
738 | devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH; | |
739 | devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read; | |
740 | devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; | |
741 | ||
742 | sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".", | |
743 | devc->n_transfer_packets_to_read, devc->read_pos); | |
744 | ||
745 | if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { | |
746 | sr_err("Cannot reset USB bulk state."); | |
747 | return ret; | |
748 | } | |
749 | sr_dbg("Will read from 0x%08lx, 0x%08x bytes.", | |
750 | (unsigned long)devc->read_pos, devc->n_bytes_to_read); | |
751 | wrptr = wrbuf; | |
752 | write_u32le_inc(&wrptr, devc->read_pos); | |
753 | write_u32le_inc(&wrptr, devc->n_bytes_to_read); | |
754 | if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) { | |
755 | sr_err("Cannot send USB bulk config."); | |
756 | return ret; | |
757 | } | |
758 | if ((ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0)) != SR_OK) { | |
759 | sr_err("Cannot unblock USB bulk transfers."); | |
760 | return ret; | |
761 | } | |
762 | ||
763 | to_read = devc->n_bytes_to_read; | |
764 | /* choose a buffer size for all of the usb transfers */ | |
765 | if (to_read >= LA2016_USB_BUFSZ) | |
766 | to_read = LA2016_USB_BUFSZ; /* multiple transfers */ | |
767 | else /* one transfer, make buffer size some multiple of LA2016_EP6_PKTSZ */ | |
768 | to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); | |
769 | buffer = g_try_malloc(to_read); | |
770 | if (!buffer) { | |
771 | sr_dbg("USB bulk transfer size %d bytes.", (int)to_read); | |
772 | sr_err("Cannot allocate buffer for USB bulk transfer."); | |
773 | return SR_ERR_MALLOC; | |
774 | } | |
775 | ||
776 | devc->transfer = libusb_alloc_transfer(0); | |
777 | libusb_fill_bulk_transfer( | |
778 | devc->transfer, usb->devhdl, | |
779 | 0x86, buffer, to_read, | |
780 | cb, (void *)sdi, DEFAULT_TIMEOUT_MS); | |
781 | ||
782 | if ((ret = libusb_submit_transfer(devc->transfer)) != 0) { | |
783 | sr_err("Cannot submit USB transfer: %s.", libusb_error_name(ret)); | |
784 | libusb_free_transfer(devc->transfer); | |
785 | devc->transfer = NULL; | |
786 | g_free(buffer); | |
787 | return SR_ERR; | |
788 | } | |
789 | ||
790 | return SR_OK; | |
791 | } | |
792 | ||
793 | static void send_chunk(struct sr_dev_inst *sdi, | |
794 | const uint8_t *packets, unsigned int num_tfers) | |
795 | { | |
796 | struct dev_context *devc; | |
797 | struct sr_datafeed_logic logic; | |
798 | struct sr_datafeed_packet sr_packet; | |
799 | unsigned int max_samples, n_samples, total_samples, free_n_samples; | |
800 | unsigned int i, j, k; | |
801 | int do_signal_trigger; | |
802 | uint16_t *wp; | |
803 | const uint8_t *rp; | |
804 | uint16_t state; | |
805 | uint8_t repetitions; | |
806 | ||
807 | devc = sdi->priv; | |
808 | ||
809 | logic.unitsize = 2; | |
810 | logic.data = devc->convbuffer; | |
811 | ||
812 | sr_packet.type = SR_DF_LOGIC; | |
813 | sr_packet.payload = &logic; | |
814 | ||
815 | max_samples = devc->convbuffer_size / 2; | |
816 | n_samples = 0; | |
817 | wp = (uint16_t *)devc->convbuffer; | |
818 | total_samples = 0; | |
819 | do_signal_trigger = 0; | |
820 | ||
821 | if (devc->had_triggers_configured && devc->reading_behind_trigger == 0 && devc->info.n_rep_packets_before_trigger == 0) { | |
822 | std_session_send_df_trigger(sdi); | |
823 | devc->reading_behind_trigger = 1; | |
824 | } | |
825 | ||
826 | rp = packets; | |
827 | for (i = 0; i < num_tfers; i++) { | |
828 | for (k = 0; k < NUM_PACKETS_IN_CHUNK; k++) { | |
829 | free_n_samples = max_samples - n_samples; | |
830 | if (free_n_samples < 256 || do_signal_trigger) { | |
831 | logic.length = n_samples * 2; | |
832 | sr_session_send(sdi, &sr_packet); | |
833 | n_samples = 0; | |
834 | wp = (uint16_t *)devc->convbuffer; | |
835 | if (do_signal_trigger) { | |
836 | std_session_send_df_trigger(sdi); | |
837 | do_signal_trigger = 0; | |
838 | } | |
839 | } | |
840 | ||
841 | state = read_u16le_inc(&rp); | |
842 | repetitions = read_u8_inc(&rp); | |
843 | for (j = 0; j < repetitions; j++) | |
844 | *wp++ = state; | |
845 | ||
846 | n_samples += repetitions; | |
847 | total_samples += repetitions; | |
848 | devc->total_samples += repetitions; | |
849 | if (!devc->reading_behind_trigger) { | |
850 | devc->n_reps_until_trigger--; | |
851 | if (devc->n_reps_until_trigger == 0) { | |
852 | devc->reading_behind_trigger = 1; | |
853 | do_signal_trigger = 1; | |
854 | sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.", | |
855 | devc->total_samples, | |
856 | (double)devc->total_samples / devc->cur_samplerate * 1e3); | |
857 | } | |
858 | } | |
859 | } | |
860 | (void)read_u8_inc(&rp); /* Skip sequence number. */ | |
861 | } | |
862 | if (n_samples) { | |
863 | logic.length = n_samples * 2; | |
864 | sr_session_send(sdi, &sr_packet); | |
865 | if (do_signal_trigger) { | |
866 | std_session_send_df_trigger(sdi); | |
867 | } | |
868 | } | |
869 | sr_dbg("Send_chunk done after %u samples.", total_samples); | |
870 | } | |
871 | ||
872 | static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) | |
873 | { | |
874 | struct sr_dev_inst *sdi; | |
875 | struct dev_context *devc; | |
876 | struct sr_usb_dev_inst *usb; | |
877 | int ret; | |
878 | ||
879 | sdi = transfer->user_data; | |
880 | devc = sdi->priv; | |
881 | usb = sdi->conn; | |
882 | ||
883 | sr_dbg("receive_transfer(): status %s received %d bytes.", | |
884 | libusb_error_name(transfer->status), transfer->actual_length); | |
885 | ||
886 | if (transfer->status == LIBUSB_TRANSFER_TIMED_OUT) { | |
887 | sr_err("USB bulk transfer timeout."); | |
888 | devc->transfer_finished = 1; | |
889 | } | |
890 | send_chunk(sdi, transfer->buffer, transfer->actual_length / TRANSFER_PACKET_LENGTH); | |
891 | ||
892 | devc->n_bytes_to_read -= transfer->actual_length; | |
893 | if (devc->n_bytes_to_read) { | |
894 | uint32_t to_read = devc->n_bytes_to_read; | |
895 | /* determine read size for the next usb transfer */ | |
896 | if (to_read >= LA2016_USB_BUFSZ) | |
897 | to_read = LA2016_USB_BUFSZ; | |
898 | else /* last transfer, make read size some multiple of LA2016_EP6_PKTSZ */ | |
899 | to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); | |
900 | libusb_fill_bulk_transfer( | |
901 | transfer, usb->devhdl, | |
902 | 0x86, transfer->buffer, to_read, | |
903 | receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS); | |
904 | ||
905 | if ((ret = libusb_submit_transfer(transfer)) == 0) | |
906 | return; | |
907 | sr_err("Cannot submit another USB transfer: %s.", | |
908 | libusb_error_name(ret)); | |
909 | } | |
910 | ||
911 | g_free(transfer->buffer); | |
912 | libusb_free_transfer(transfer); | |
913 | devc->transfer_finished = 1; | |
914 | } | |
915 | ||
916 | SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) | |
917 | { | |
918 | const struct sr_dev_inst *sdi; | |
919 | struct dev_context *devc; | |
920 | struct drv_context *drvc; | |
921 | struct timeval tv; | |
922 | ||
923 | (void)fd; | |
924 | (void)revents; | |
925 | ||
926 | sdi = cb_data; | |
927 | devc = sdi->priv; | |
928 | drvc = sdi->driver->context; | |
929 | ||
930 | if (devc->have_trigger == 0) { | |
931 | if (la2016_has_triggered(sdi) == 0) { | |
932 | /* not yet ready for download */ | |
933 | return TRUE; | |
934 | } | |
935 | devc->have_trigger = 1; | |
936 | devc->transfer_finished = 0; | |
937 | devc->reading_behind_trigger = 0; | |
938 | devc->total_samples = 0; | |
939 | /* we can start retrieving data! */ | |
940 | if (la2016_start_retrieval(sdi, receive_transfer) != SR_OK) { | |
941 | sr_err("Cannot start acquisition data download."); | |
942 | return FALSE; | |
943 | } | |
944 | sr_dbg("Acquisition data download started."); | |
945 | std_session_send_df_frame_begin(sdi); | |
946 | ||
947 | return TRUE; | |
948 | } | |
949 | ||
950 | tv.tv_sec = tv.tv_usec = 0; | |
951 | libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv); | |
952 | ||
953 | if (devc->transfer_finished) { | |
954 | sr_dbg("Download finished, post processing."); | |
955 | std_session_send_df_frame_end(sdi); | |
956 | ||
957 | usb_source_remove(sdi->session, drvc->sr_ctx); | |
958 | std_session_send_df_end(sdi); | |
959 | ||
960 | la2016_stop_acquisition(sdi); | |
961 | ||
962 | g_free(devc->convbuffer); | |
963 | devc->convbuffer = NULL; | |
964 | ||
965 | devc->transfer = NULL; | |
966 | ||
967 | sr_dbg("Download finished, done post processing."); | |
968 | } | |
969 | ||
970 | return TRUE; | |
971 | } | |
972 | ||
973 | SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) | |
974 | { | |
975 | struct dev_context *devc; | |
976 | uint16_t state; | |
977 | uint8_t buf[8]; | |
978 | int16_t purchase_date_bcd[2]; | |
979 | uint8_t magic; | |
980 | int ret; | |
981 | ||
982 | devc = sdi->priv; | |
983 | ||
984 | /* Four bytes of eeprom at 0x20 are purchase year & month in BCD format, with 16bit | |
985 | * complemented checksum; e.g. 2004DFFB = 2020-April. | |
986 | * This helps to identify the age of devices if unknown magic numbers occur. | |
987 | */ | |
988 | if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, purchase_date_bcd, sizeof(purchase_date_bcd))) != SR_OK) { | |
989 | sr_err("Cannot read purchase date in EEPROM."); | |
990 | } | |
991 | else { | |
992 | sr_dbg("Purchase date: 20%02hx-%02hx.", | |
993 | (purchase_date_bcd[0]) & 0xff, | |
994 | (purchase_date_bcd[0] >> 8) & 0xff); | |
995 | if (purchase_date_bcd[0] != (0x0ffff & ~purchase_date_bcd[1])) { | |
996 | sr_err("Purchase date fails checksum test."); | |
997 | } | |
998 | } | |
999 | ||
1000 | /* | |
1001 | * There are four known kingst logic analyser devices which use this same usb vid and pid: | |
1002 | * LA2016, LA1016 and the older revision of each of these. They all use the same hardware | |
1003 | * and the same FX2 mcu firmware but each requires a different fpga bitstream. They are | |
1004 | * differentiated by a 'magic' byte within the 8 bytes of EEPROM from address 0x08. | |
1005 | * For example; | |
1006 | * | |
1007 | * magic=0x08 | |
1008 | * | ~magic=0xf7 | |
1009 | * | | | |
1010 | * 08F7000008F710EF | |
1011 | * | | | |
1012 | * | ~magic-backup | |
1013 | * magic-backup | |
1014 | * | |
1015 | * It seems that only these magic bytes are used, other bytes shown above are 'don't care'. | |
1016 | * Changing the magic byte on newer device to older magic causes OEM software to load | |
1017 | * the older fpga bitstream. The device then functions but has channels out of order. | |
1018 | * It's likely the bitstreams were changed to move input channel pins due to PCB changes. | |
1019 | * | |
1020 | * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others) | |
1021 | * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" (latest v1.3.0 PCB, perhaps others) | |
1022 | * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" | |
1023 | * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" | |
1024 | * | |
1025 | * This was all determined by altering the eeprom contents of an LA2016 and LA1016 and observing | |
1026 | * the vendor software actions, either raising errors or loading specific bitstreams. | |
1027 | * | |
1028 | * Note: | |
1029 | * An LA1016 cannot be converted to an LA2016 by changing the magic number - the bitstream | |
1030 | * will not authenticate with ic U10, which has different security coding for each device type. | |
1031 | */ | |
1032 | ||
1033 | if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &buf, sizeof(buf))) != SR_OK) { | |
1034 | sr_err("Cannot read EEPROM device identifier bytes."); | |
1035 | return ret; | |
1036 | } | |
1037 | ||
1038 | magic = 0; | |
1039 | if (buf[0] == (0x0ff & ~buf[1])) { | |
1040 | /* primary copy of magic passes complement check */ | |
1041 | magic = buf[0]; | |
1042 | } | |
1043 | else if (buf[4] == (0x0ff & ~buf[5])) { | |
1044 | /* backup copy of magic passes complement check */ | |
1045 | sr_dbg("Using backup copy of device type magic number."); | |
1046 | magic = buf[4]; | |
1047 | } | |
1048 | ||
1049 | sr_dbg("Device type: magic number is %hhu.", magic); | |
1050 | ||
1051 | /* select the correct fpga bitstream for this device */ | |
1052 | switch (magic) { | |
1053 | case 2: | |
1054 | ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016); | |
1055 | devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; | |
1056 | break; | |
1057 | case 3: | |
1058 | ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016); | |
1059 | devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; | |
1060 | break; | |
1061 | case 8: | |
1062 | ret = upload_fpga_bitstream(sdi, FPGA_FW_LA2016A); | |
1063 | devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; | |
1064 | break; | |
1065 | case 9: | |
1066 | ret = upload_fpga_bitstream(sdi, FPGA_FW_LA1016A); | |
1067 | devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; | |
1068 | break; | |
1069 | default: | |
1070 | sr_err("Cannot identify as one of the supported models."); | |
1071 | return SR_ERR; | |
1072 | } | |
1073 | ||
1074 | if (ret != SR_OK) { | |
1075 | sr_err("Cannot upload FPGA bitstream."); | |
1076 | return ret; | |
1077 | } | |
1078 | ||
1079 | state = run_state(sdi); | |
1080 | if (state != 0x85e9) { | |
1081 | sr_warn("Unexpected run state, want 0x85e9, got 0x%04x.", state); | |
1082 | } | |
1083 | ||
1084 | if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { | |
1085 | sr_err("Cannot reset USB bulk transfer."); | |
1086 | return ret; | |
1087 | } | |
1088 | ||
1089 | sr_dbg("Device should be initialized."); | |
1090 | ||
1091 | return set_defaults(sdi); | |
1092 | } | |
1093 | ||
1094 | SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi) | |
1095 | { | |
1096 | int ret; | |
1097 | ||
1098 | if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) { | |
1099 | sr_err("Cannot deinitialize device's FPGA."); | |
1100 | return ret; | |
1101 | } | |
1102 | ||
1103 | return SR_OK; | |
1104 | } |