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1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <config.h>
27#include "protocol.h"
28
29/*
30 * The ASIX Sigma supports arbitrary integer frequency divider in
31 * the 50MHz mode. The divider is in range 1...256 , allowing for
32 * very precise sampling rate selection. This driver supports only
33 * a subset of the sampling rates.
34 */
35SR_PRIV const uint64_t samplerates[] = {
36 SR_KHZ(200), /* div=250 */
37 SR_KHZ(250), /* div=200 */
38 SR_KHZ(500), /* div=100 */
39 SR_MHZ(1), /* div=50 */
40 SR_MHZ(5), /* div=10 */
41 SR_MHZ(10), /* div=5 */
42 SR_MHZ(25), /* div=2 */
43 SR_MHZ(50), /* div=1 */
44 SR_MHZ(100), /* Special FW needed */
45 SR_MHZ(200), /* Special FW needed */
46};
47
48SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates);
49
50static const char firmware_files[][24] = {
51 /* 50 MHz, supports 8 bit fractions */
52 "asix-sigma-50.fw",
53 /* 100 MHz */
54 "asix-sigma-100.fw",
55 /* 200 MHz */
56 "asix-sigma-200.fw",
57 /* Synchronous clock from pin */
58 "asix-sigma-50sync.fw",
59 /* Frequency counter */
60 "asix-sigma-phasor.fw",
61};
62
63static int sigma_read(void *buf, size_t size, struct dev_context *devc)
64{
65 int ret;
66
67 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
68 if (ret < 0) {
69 sr_err("ftdi_read_data failed: %s",
70 ftdi_get_error_string(&devc->ftdic));
71 }
72
73 return ret;
74}
75
76static int sigma_write(void *buf, size_t size, struct dev_context *devc)
77{
78 int ret;
79
80 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
81 if (ret < 0)
82 sr_err("ftdi_write_data failed: %s",
83 ftdi_get_error_string(&devc->ftdic));
84 else if ((size_t) ret != size)
85 sr_err("ftdi_write_data did not complete write.");
86
87 return ret;
88}
89
90/*
91 * NOTE: We chose the buffer size to be large enough to hold any write to the
92 * device. We still print a message just in case.
93 */
94SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
95 struct dev_context *devc)
96{
97 size_t i;
98 uint8_t buf[80];
99 int idx = 0;
100
101 if ((2 * len + 2) > sizeof(buf)) {
102 sr_err("Attempted to write %zu bytes, but buffer is too small.",
103 len);
104 return SR_ERR_BUG;
105 }
106
107 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
108 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
109
110 for (i = 0; i < len; i++) {
111 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
112 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
113 }
114
115 return sigma_write(buf, idx, devc);
116}
117
118SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
119{
120 return sigma_write_register(reg, &value, 1, devc);
121}
122
123static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
124 struct dev_context *devc)
125{
126 uint8_t buf[3];
127
128 buf[0] = REG_ADDR_LOW | (reg & 0xf);
129 buf[1] = REG_ADDR_HIGH | (reg >> 4);
130 buf[2] = REG_READ_ADDR;
131
132 sigma_write(buf, sizeof(buf), devc);
133
134 return sigma_read(data, len, devc);
135}
136
137static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
138 struct dev_context *devc)
139{
140 uint8_t buf[] = {
141 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
142
143 REG_READ_ADDR | NEXT_REG,
144 REG_READ_ADDR | NEXT_REG,
145 REG_READ_ADDR | NEXT_REG,
146 REG_READ_ADDR | NEXT_REG,
147 REG_READ_ADDR | NEXT_REG,
148 REG_READ_ADDR | NEXT_REG,
149 };
150 uint8_t result[6];
151
152 sigma_write(buf, sizeof(buf), devc);
153
154 sigma_read(result, sizeof(result), devc);
155
156 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
157 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
158
159 /*
160 * These "position" values point to after the event (end of
161 * capture data, trigger condition matched). This is why they
162 * get decremented here. Sample memory consists of 512-byte
163 * chunks with meta data in the upper 64 bytes. Thus when the
164 * decrements takes us into this upper part of the chunk, then
165 * further move backwards to the end of the chunk's data part.
166 */
167 if ((--*stoppos & 0x1ff) == 0x1ff)
168 *stoppos -= 64;
169 if ((--*triggerpos & 0x1ff) == 0x1ff)
170 *triggerpos -= 64;
171
172 return 1;
173}
174
175static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
176 uint8_t *data, struct dev_context *devc)
177{
178 size_t i;
179 uint8_t buf[4096];
180 int idx;
181
182 /* Send the startchunk. Index start with 1. */
183 idx = 0;
184 buf[idx++] = startchunk >> 8;
185 buf[idx++] = startchunk & 0xff;
186 sigma_write_register(WRITE_MEMROW, buf, idx, devc);
187
188 /* Read the DRAM. */
189 idx = 0;
190 buf[idx++] = REG_DRAM_BLOCK;
191 buf[idx++] = REG_DRAM_WAIT_ACK;
192
193 for (i = 0; i < numchunks; i++) {
194 /* Alternate bit to copy from DRAM to cache. */
195 if (i != (numchunks - 1))
196 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
197
198 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
199
200 if (i != (numchunks - 1))
201 buf[idx++] = REG_DRAM_WAIT_ACK;
202 }
203
204 sigma_write(buf, idx, devc);
205
206 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
207}
208
209/* Upload trigger look-up tables to Sigma. */
210SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
211{
212 int i;
213 uint8_t tmp[2];
214 uint16_t bit;
215
216 /* Transpose the table and send to Sigma. */
217 for (i = 0; i < 16; i++) {
218 bit = 1 << i;
219
220 tmp[0] = tmp[1] = 0;
221
222 if (lut->m2d[0] & bit)
223 tmp[0] |= 0x01;
224 if (lut->m2d[1] & bit)
225 tmp[0] |= 0x02;
226 if (lut->m2d[2] & bit)
227 tmp[0] |= 0x04;
228 if (lut->m2d[3] & bit)
229 tmp[0] |= 0x08;
230
231 if (lut->m3 & bit)
232 tmp[0] |= 0x10;
233 if (lut->m3s & bit)
234 tmp[0] |= 0x20;
235 if (lut->m4 & bit)
236 tmp[0] |= 0x40;
237
238 if (lut->m0d[0] & bit)
239 tmp[1] |= 0x01;
240 if (lut->m0d[1] & bit)
241 tmp[1] |= 0x02;
242 if (lut->m0d[2] & bit)
243 tmp[1] |= 0x04;
244 if (lut->m0d[3] & bit)
245 tmp[1] |= 0x08;
246
247 if (lut->m1d[0] & bit)
248 tmp[1] |= 0x10;
249 if (lut->m1d[1] & bit)
250 tmp[1] |= 0x20;
251 if (lut->m1d[2] & bit)
252 tmp[1] |= 0x40;
253 if (lut->m1d[3] & bit)
254 tmp[1] |= 0x80;
255
256 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
257 devc);
258 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
259 }
260
261 /* Send the parameters */
262 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
263 sizeof(lut->params), devc);
264
265 return SR_OK;
266}
267
268/*
269 * Configure the FPGA for bitbang mode.
270 * This sequence is documented in section 2. of the ASIX Sigma programming
271 * manual. This sequence is necessary to configure the FPGA in the Sigma
272 * into Bitbang mode, in which it can be programmed with the firmware.
273 */
274static int sigma_fpga_init_bitbang(struct dev_context *devc)
275{
276 uint8_t suicide[] = {
277 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
278 };
279 uint8_t init_array[] = {
280 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
281 0x01, 0x01,
282 };
283 int i, ret, timeout = (10 * 1000);
284 uint8_t data;
285
286 /* Section 2. part 1), do the FPGA suicide. */
287 sigma_write(suicide, sizeof(suicide), devc);
288 sigma_write(suicide, sizeof(suicide), devc);
289 sigma_write(suicide, sizeof(suicide), devc);
290 sigma_write(suicide, sizeof(suicide), devc);
291
292 /* Section 2. part 2), do pulse on D1. */
293 sigma_write(init_array, sizeof(init_array), devc);
294 ftdi_usb_purge_buffers(&devc->ftdic);
295
296 /* Wait until the FPGA asserts D6/INIT_B. */
297 for (i = 0; i < timeout; i++) {
298 ret = sigma_read(&data, 1, devc);
299 if (ret < 0)
300 return ret;
301 /* Test if pin D6 got asserted. */
302 if (data & (1 << 5))
303 return 0;
304 /* The D6 was not asserted yet, wait a bit. */
305 g_usleep(10 * 1000);
306 }
307
308 return SR_ERR_TIMEOUT;
309}
310
311/*
312 * Configure the FPGA for logic-analyzer mode.
313 */
314static int sigma_fpga_init_la(struct dev_context *devc)
315{
316 /* Initialize the logic analyzer mode. */
317 uint8_t mode_regval = WMR_SDRAMINIT;
318 uint8_t logic_mode_start[] = {
319 REG_ADDR_LOW | (READ_ID & 0xf),
320 REG_ADDR_HIGH | (READ_ID >> 4),
321 REG_READ_ADDR, /* Read ID register. */
322
323 REG_ADDR_LOW | (WRITE_TEST & 0xf),
324 REG_DATA_LOW | 0x5,
325 REG_DATA_HIGH_WRITE | 0x5,
326 REG_READ_ADDR, /* Read scratch register. */
327
328 REG_DATA_LOW | 0xa,
329 REG_DATA_HIGH_WRITE | 0xa,
330 REG_READ_ADDR, /* Read scratch register. */
331
332 REG_ADDR_LOW | (WRITE_MODE & 0xf),
333 REG_DATA_LOW | (mode_regval & 0xf),
334 REG_DATA_HIGH_WRITE | (mode_regval >> 4),
335 };
336
337 uint8_t result[3];
338 int ret;
339
340 /* Initialize the logic analyzer mode. */
341 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
342
343 /* Expect a 3 byte reply since we issued three READ requests. */
344 ret = sigma_read(result, 3, devc);
345 if (ret != 3)
346 goto err;
347
348 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
349 goto err;
350
351 return SR_OK;
352err:
353 sr_err("Configuration failed. Invalid reply received.");
354 return SR_ERR;
355}
356
357/*
358 * Read the firmware from a file and transform it into a series of bitbang
359 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
360 * by the caller of this function.
361 */
362static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name,
363 uint8_t **bb_cmd, gsize *bb_cmd_size)
364{
365 size_t i, file_size, bb_size;
366 char *firmware;
367 uint8_t *bb_stream, *bbs;
368 uint32_t imm;
369 int bit, v;
370 int ret = SR_OK;
371
372 /* Retrieve the on-disk firmware file content. */
373 firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE,
374 name, &file_size, 256 * 1024);
375 if (!firmware)
376 return SR_ERR;
377
378 /* Unscramble the file content (XOR with "random" sequence). */
379 imm = 0x3f6df2ab;
380 for (i = 0; i < file_size; i++) {
381 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
382 firmware[i] ^= imm & 0xff;
383 }
384
385 /*
386 * Generate a sequence of bitbang samples. With two samples per
387 * FPGA configuration bit, providing the level for the DIN signal
388 * as well as two edges for CCLK. See Xilinx UG332 for details
389 * ("slave serial" mode).
390 *
391 * Note that CCLK is inverted in hardware. That's why the
392 * respective bit is first set and then cleared in the bitbang
393 * sample sets. So that the DIN level will be stable when the
394 * data gets sampled at the rising CCLK edge, and the signals'
395 * setup time constraint will be met.
396 *
397 * The caller will put the FPGA into download mode, will send
398 * the bitbang samples, and release the allocated memory.
399 */
400 bb_size = file_size * 8 * 2;
401 bb_stream = (uint8_t *)g_try_malloc(bb_size);
402 if (!bb_stream) {
403 sr_err("%s: Failed to allocate bitbang stream", __func__);
404 ret = SR_ERR_MALLOC;
405 goto exit;
406 }
407 bbs = bb_stream;
408 for (i = 0; i < file_size; i++) {
409 for (bit = 7; bit >= 0; bit--) {
410 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
411 *bbs++ = v | 0x01;
412 *bbs++ = v;
413 }
414 }
415
416 /* The transformation completed successfully, return the result. */
417 *bb_cmd = bb_stream;
418 *bb_cmd_size = bb_size;
419
420exit:
421 g_free(firmware);
422 return ret;
423}
424
425static int upload_firmware(struct sr_context *ctx,
426 int firmware_idx, struct dev_context *devc)
427{
428 int ret;
429 unsigned char *buf;
430 unsigned char pins;
431 size_t buf_size;
432 const char *firmware;
433
434 /* Avoid downloading the same firmware multiple times. */
435 firmware = firmware_files[firmware_idx];
436 if (devc->cur_firmware == firmware_idx) {
437 sr_info("Not uploading firmware file '%s' again.", firmware);
438 return SR_OK;
439 }
440
441 ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG);
442 if (ret < 0) {
443 sr_err("ftdi_set_bitmode failed: %s",
444 ftdi_get_error_string(&devc->ftdic));
445 return SR_ERR;
446 }
447
448 /* Four times the speed of sigmalogan - Works well. */
449 ret = ftdi_set_baudrate(&devc->ftdic, 750 * 1000);
450 if (ret < 0) {
451 sr_err("ftdi_set_baudrate failed: %s",
452 ftdi_get_error_string(&devc->ftdic));
453 return SR_ERR;
454 }
455
456 /* Initialize the FPGA for firmware upload. */
457 ret = sigma_fpga_init_bitbang(devc);
458 if (ret)
459 return ret;
460
461 /* Prepare firmware. */
462 ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size);
463 if (ret != SR_OK) {
464 sr_err("An error occurred while reading the firmware: %s",
465 firmware);
466 return ret;
467 }
468
469 /* Upload firmware. */
470 sr_info("Uploading firmware file '%s'.", firmware);
471 sigma_write(buf, buf_size, devc);
472
473 g_free(buf);
474
475 ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET);
476 if (ret < 0) {
477 sr_err("ftdi_set_bitmode failed: %s",
478 ftdi_get_error_string(&devc->ftdic));
479 return SR_ERR;
480 }
481
482 ftdi_usb_purge_buffers(&devc->ftdic);
483
484 /* Discard garbage. */
485 while (sigma_read(&pins, 1, devc) == 1)
486 ;
487
488 /* Initialize the FPGA for logic-analyzer mode. */
489 ret = sigma_fpga_init_la(devc);
490 if (ret != SR_OK)
491 return ret;
492
493 devc->cur_firmware = firmware_idx;
494
495 sr_info("Firmware uploaded.");
496
497 return SR_OK;
498}
499
500/*
501 * Sigma doesn't support limiting the number of samples, so we have to
502 * translate the number and the samplerate to an elapsed time.
503 *
504 * In addition we need to ensure that the last data cluster has passed
505 * the hardware pipeline, and became available to the PC side. With RLE
506 * compression up to 327ms could pass before another cluster accumulates
507 * at 200kHz samplerate when input pins don't change.
508 */
509SR_PRIV uint64_t sigma_limit_samples_to_msec(const struct dev_context *devc,
510 uint64_t limit_samples)
511{
512 uint64_t limit_msec;
513 uint64_t worst_cluster_time_ms;
514
515 limit_msec = limit_samples * 1000 / devc->cur_samplerate;
516 worst_cluster_time_ms = 65536 * 1000 / devc->cur_samplerate;
517 /*
518 * One cluster time is not enough to flush pipeline when sampling
519 * grounded pins with 1 sample limit at 200kHz. Hence the 2* fix.
520 */
521 return limit_msec + 2 * worst_cluster_time_ms;
522}
523
524SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
525{
526 struct dev_context *devc;
527 struct drv_context *drvc;
528 size_t i;
529 int ret;
530 int num_channels;
531
532 devc = sdi->priv;
533 drvc = sdi->driver->context;
534 ret = SR_OK;
535
536 /* Reject rates that are not in the list of supported rates. */
537 for (i = 0; i < samplerates_count; i++) {
538 if (samplerates[i] == samplerate)
539 break;
540 }
541 if (i >= samplerates_count || samplerates[i] == 0)
542 return SR_ERR_SAMPLERATE;
543
544 /*
545 * Depending on the samplerates of 200/100/50- MHz, specific
546 * firmware is required and higher rates might limit the set
547 * of available channels.
548 */
549 num_channels = devc->num_channels;
550 if (samplerate <= SR_MHZ(50)) {
551 ret = upload_firmware(drvc->sr_ctx, 0, devc);
552 num_channels = 16;
553 } else if (samplerate == SR_MHZ(100)) {
554 ret = upload_firmware(drvc->sr_ctx, 1, devc);
555 num_channels = 8;
556 } else if (samplerate == SR_MHZ(200)) {
557 ret = upload_firmware(drvc->sr_ctx, 2, devc);
558 num_channels = 4;
559 }
560
561 /*
562 * Derive the sample period from the sample rate as well as the
563 * number of samples that the device will communicate within
564 * an "event" (memory organization internal to the device).
565 */
566 if (ret == SR_OK) {
567 devc->num_channels = num_channels;
568 devc->cur_samplerate = samplerate;
569 devc->samples_per_event = 16 / devc->num_channels;
570 devc->state.state = SIGMA_IDLE;
571 }
572
573 /*
574 * Support for "limit_samples" is implemented by stopping
575 * acquisition after a corresponding period of time.
576 * Re-calculate that period of time, in case the limit is
577 * set first and the samplerate gets (re-)configured later.
578 */
579 if (ret == SR_OK && devc->limit_samples) {
580 uint64_t msecs;
581 msecs = sigma_limit_samples_to_msec(devc, devc->limit_samples);
582 devc->limit_msec = msecs;
583 }
584
585 return ret;
586}
587
588/*
589 * In 100 and 200 MHz mode, only a single pin rising/falling can be
590 * set as trigger. In other modes, two rising/falling triggers can be set,
591 * in addition to value/mask trigger for any number of channels.
592 *
593 * The Sigma supports complex triggers using boolean expressions, but this
594 * has not been implemented yet.
595 */
596SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi)
597{
598 struct dev_context *devc;
599 struct sr_trigger *trigger;
600 struct sr_trigger_stage *stage;
601 struct sr_trigger_match *match;
602 const GSList *l, *m;
603 int channelbit, trigger_set;
604
605 devc = sdi->priv;
606 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
607 if (!(trigger = sr_session_trigger_get(sdi->session)))
608 return SR_OK;
609
610 trigger_set = 0;
611 for (l = trigger->stages; l; l = l->next) {
612 stage = l->data;
613 for (m = stage->matches; m; m = m->next) {
614 match = m->data;
615 if (!match->channel->enabled)
616 /* Ignore disabled channels with a trigger. */
617 continue;
618 channelbit = 1 << (match->channel->index);
619 if (devc->cur_samplerate >= SR_MHZ(100)) {
620 /* Fast trigger support. */
621 if (trigger_set) {
622 sr_err("Only a single pin trigger is "
623 "supported in 100 and 200MHz mode.");
624 return SR_ERR;
625 }
626 if (match->match == SR_TRIGGER_FALLING)
627 devc->trigger.fallingmask |= channelbit;
628 else if (match->match == SR_TRIGGER_RISING)
629 devc->trigger.risingmask |= channelbit;
630 else {
631 sr_err("Only rising/falling trigger is "
632 "supported in 100 and 200MHz mode.");
633 return SR_ERR;
634 }
635
636 trigger_set++;
637 } else {
638 /* Simple trigger support (event). */
639 if (match->match == SR_TRIGGER_ONE) {
640 devc->trigger.simplevalue |= channelbit;
641 devc->trigger.simplemask |= channelbit;
642 } else if (match->match == SR_TRIGGER_ZERO) {
643 devc->trigger.simplevalue &= ~channelbit;
644 devc->trigger.simplemask |= channelbit;
645 } else if (match->match == SR_TRIGGER_FALLING) {
646 devc->trigger.fallingmask |= channelbit;
647 trigger_set++;
648 } else if (match->match == SR_TRIGGER_RISING) {
649 devc->trigger.risingmask |= channelbit;
650 trigger_set++;
651 }
652
653 /*
654 * Actually, Sigma supports 2 rising/falling triggers,
655 * but they are ORed and the current trigger syntax
656 * does not permit ORed triggers.
657 */
658 if (trigger_set > 1) {
659 sr_err("Only 1 rising/falling trigger "
660 "is supported.");
661 return SR_ERR;
662 }
663 }
664 }
665 }
666
667 return SR_OK;
668}
669
670/* Software trigger to determine exact trigger position. */
671static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
672 struct sigma_trigger *t)
673{
674 int i;
675 uint16_t sample = 0;
676
677 for (i = 0; i < 8; i++) {
678 if (i > 0)
679 last_sample = sample;
680 sample = samples[2 * i] | (samples[2 * i + 1] << 8);
681
682 /* Simple triggers. */
683 if ((sample & t->simplemask) != t->simplevalue)
684 continue;
685
686 /* Rising edge. */
687 if (((last_sample & t->risingmask) != 0) ||
688 ((sample & t->risingmask) != t->risingmask))
689 continue;
690
691 /* Falling edge. */
692 if ((last_sample & t->fallingmask) != t->fallingmask ||
693 (sample & t->fallingmask) != 0)
694 continue;
695
696 break;
697 }
698
699 /* If we did not match, return original trigger pos. */
700 return i & 0x7;
701}
702
703/*
704 * Return the timestamp of "DRAM cluster".
705 */
706static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
707{
708 return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
709}
710
711/*
712 * Return one 16bit data entity of a DRAM cluster at the specified index.
713 */
714static uint16_t sigma_dram_cluster_data(struct sigma_dram_cluster *cl, int idx)
715{
716 uint16_t sample;
717
718 sample = 0;
719 sample |= cl->samples[idx].sample_lo << 0;
720 sample |= cl->samples[idx].sample_hi << 8;
721 sample = (sample >> 8) | (sample << 8);
722 return sample;
723}
724
725/*
726 * Deinterlace sample data that was retrieved at 100MHz samplerate.
727 * One 16bit item contains two samples of 8bits each. The bits of
728 * multiple samples are interleaved.
729 */
730static uint16_t sigma_deinterlace_100mhz_data(uint16_t indata, int idx)
731{
732 uint16_t outdata;
733
734 indata >>= idx;
735 outdata = 0;
736 outdata |= (indata >> (0 * 2 - 0)) & (1 << 0);
737 outdata |= (indata >> (1 * 2 - 1)) & (1 << 1);
738 outdata |= (indata >> (2 * 2 - 2)) & (1 << 2);
739 outdata |= (indata >> (3 * 2 - 3)) & (1 << 3);
740 outdata |= (indata >> (4 * 2 - 4)) & (1 << 4);
741 outdata |= (indata >> (5 * 2 - 5)) & (1 << 5);
742 outdata |= (indata >> (6 * 2 - 6)) & (1 << 6);
743 outdata |= (indata >> (7 * 2 - 7)) & (1 << 7);
744 return outdata;
745}
746
747/*
748 * Deinterlace sample data that was retrieved at 200MHz samplerate.
749 * One 16bit item contains four samples of 4bits each. The bits of
750 * multiple samples are interleaved.
751 */
752static uint16_t sigma_deinterlace_200mhz_data(uint16_t indata, int idx)
753{
754 uint16_t outdata;
755
756 indata >>= idx;
757 outdata = 0;
758 outdata |= (indata >> (0 * 4 - 0)) & (1 << 0);
759 outdata |= (indata >> (1 * 4 - 1)) & (1 << 1);
760 outdata |= (indata >> (2 * 4 - 2)) & (1 << 2);
761 outdata |= (indata >> (3 * 4 - 3)) & (1 << 3);
762 return outdata;
763}
764
765static void store_sr_sample(uint8_t *samples, int idx, uint16_t data)
766{
767 samples[2 * idx + 0] = (data >> 0) & 0xff;
768 samples[2 * idx + 1] = (data >> 8) & 0xff;
769}
770
771/*
772 * Local wrapper around sr_session_send() calls. Make sure to not send
773 * more samples to the session's datafeed than what was requested by a
774 * previously configured (optional) sample count.
775 */
776static void sigma_session_send(struct sr_dev_inst *sdi,
777 struct sr_datafeed_packet *packet)
778{
779 struct dev_context *devc;
780 struct sr_datafeed_logic *logic;
781 uint64_t send_now;
782
783 devc = sdi->priv;
784 if (devc->limit_samples) {
785 logic = (void *)packet->payload;
786 send_now = logic->length / logic->unitsize;
787 if (devc->sent_samples + send_now > devc->limit_samples) {
788 send_now = devc->limit_samples - devc->sent_samples;
789 logic->length = send_now * logic->unitsize;
790 }
791 if (!send_now)
792 return;
793 devc->sent_samples += send_now;
794 }
795
796 sr_session_send(sdi, packet);
797}
798
799/*
800 * This size translates to: event count (1K events per cluster), times
801 * the sample width (unitsize, 16bits per event), times the maximum
802 * number of samples per event.
803 */
804#define SAMPLES_BUFFER_SIZE (1024 * 2 * 4)
805
806static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
807 unsigned int events_in_cluster,
808 unsigned int triggered,
809 struct sr_dev_inst *sdi)
810{
811 struct dev_context *devc = sdi->priv;
812 struct sigma_state *ss = &devc->state;
813 struct sr_datafeed_packet packet;
814 struct sr_datafeed_logic logic;
815 uint16_t tsdiff, ts, sample, item16;
816 uint8_t samples[SAMPLES_BUFFER_SIZE];
817 uint8_t *send_ptr;
818 size_t send_count, trig_count;
819 unsigned int i;
820 int j;
821
822 ts = sigma_dram_cluster_ts(dram_cluster);
823 tsdiff = ts - ss->lastts;
824 ss->lastts = ts + EVENTS_PER_CLUSTER;
825
826 packet.type = SR_DF_LOGIC;
827 packet.payload = &logic;
828 logic.unitsize = 2;
829 logic.data = samples;
830
831 /*
832 * If this cluster is not adjacent to the previously received
833 * cluster, then send the appropriate number of samples with the
834 * previous values to the sigrok session. This "decodes RLE".
835 */
836 for (ts = 0; ts < tsdiff; ts++) {
837 i = ts % 1024;
838 store_sr_sample(samples, i, ss->lastsample);
839
840 /*
841 * If we have 1024 samples ready or we're at the
842 * end of submitting the padding samples, submit
843 * the packet to Sigrok. Since constant data is
844 * sent, duplication of data for rates above 50MHz
845 * is simple.
846 */
847 if ((i == 1023) || (ts == tsdiff - 1)) {
848 logic.length = (i + 1) * logic.unitsize;
849 for (j = 0; j < devc->samples_per_event; j++)
850 sigma_session_send(sdi, &packet);
851 }
852 }
853
854 /*
855 * Parse the samples in current cluster and prepare them
856 * to be submitted to Sigrok. Cope with memory layouts that
857 * vary with the samplerate.
858 */
859 send_ptr = &samples[0];
860 send_count = 0;
861 sample = 0;
862 for (i = 0; i < events_in_cluster; i++) {
863 item16 = sigma_dram_cluster_data(dram_cluster, i);
864 if (devc->cur_samplerate == SR_MHZ(200)) {
865 sample = sigma_deinterlace_200mhz_data(item16, 0);
866 store_sr_sample(samples, send_count++, sample);
867 sample = sigma_deinterlace_200mhz_data(item16, 1);
868 store_sr_sample(samples, send_count++, sample);
869 sample = sigma_deinterlace_200mhz_data(item16, 2);
870 store_sr_sample(samples, send_count++, sample);
871 sample = sigma_deinterlace_200mhz_data(item16, 3);
872 store_sr_sample(samples, send_count++, sample);
873 } else if (devc->cur_samplerate == SR_MHZ(100)) {
874 sample = sigma_deinterlace_100mhz_data(item16, 0);
875 store_sr_sample(samples, send_count++, sample);
876 sample = sigma_deinterlace_100mhz_data(item16, 1);
877 store_sr_sample(samples, send_count++, sample);
878 } else {
879 sample = item16;
880 store_sr_sample(samples, send_count++, sample);
881 }
882 }
883
884 /*
885 * If a trigger position applies, then provide the datafeed with
886 * the first part of data up to that position, then send the
887 * trigger marker.
888 */
889 int trigger_offset = 0;
890 if (triggered) {
891 /*
892 * Trigger is not always accurate to sample because of
893 * pipeline delay. However, it always triggers before
894 * the actual event. We therefore look at the next
895 * samples to pinpoint the exact position of the trigger.
896 */
897 trigger_offset = get_trigger_offset(samples,
898 ss->lastsample, &devc->trigger);
899
900 if (trigger_offset > 0) {
901 trig_count = trigger_offset * devc->samples_per_event;
902 packet.type = SR_DF_LOGIC;
903 logic.length = trig_count * logic.unitsize;
904 sigma_session_send(sdi, &packet);
905 send_ptr += trig_count * logic.unitsize;
906 send_count -= trig_count;
907 }
908
909 /* Only send trigger if explicitly enabled. */
910 if (devc->use_triggers) {
911 packet.type = SR_DF_TRIGGER;
912 sr_session_send(sdi, &packet);
913 }
914 }
915
916 /*
917 * Send the data after the trigger, or all of the received data
918 * if no trigger position applies.
919 */
920 if (send_count) {
921 packet.type = SR_DF_LOGIC;
922 logic.length = send_count * logic.unitsize;
923 logic.data = send_ptr;
924 sigma_session_send(sdi, &packet);
925 }
926
927 ss->lastsample = sample;
928}
929
930/*
931 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
932 * Each event is 20ns apart, and can contain multiple samples.
933 *
934 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
935 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
936 * For 50 MHz and below, events contain one sample for each channel,
937 * spread 20 ns apart.
938 */
939static int decode_chunk_ts(struct sigma_dram_line *dram_line,
940 uint16_t events_in_line,
941 uint32_t trigger_event,
942 struct sr_dev_inst *sdi)
943{
944 struct sigma_dram_cluster *dram_cluster;
945 struct dev_context *devc;
946 unsigned int clusters_in_line;
947 unsigned int events_in_cluster;
948 unsigned int i;
949 uint32_t trigger_cluster, triggered;
950
951 devc = sdi->priv;
952 clusters_in_line = events_in_line;
953 clusters_in_line += EVENTS_PER_CLUSTER - 1;
954 clusters_in_line /= EVENTS_PER_CLUSTER;
955 trigger_cluster = ~0;
956 triggered = 0;
957
958 /* Check if trigger is in this chunk. */
959 if (trigger_event < (64 * 7)) {
960 if (devc->cur_samplerate <= SR_MHZ(50)) {
961 trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
962 trigger_event);
963 }
964
965 /* Find in which cluster the trigger occurred. */
966 trigger_cluster = trigger_event / EVENTS_PER_CLUSTER;
967 }
968
969 /* For each full DRAM cluster. */
970 for (i = 0; i < clusters_in_line; i++) {
971 dram_cluster = &dram_line->cluster[i];
972
973 /* The last cluster might not be full. */
974 if ((i == clusters_in_line - 1) &&
975 (events_in_line % EVENTS_PER_CLUSTER)) {
976 events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
977 } else {
978 events_in_cluster = EVENTS_PER_CLUSTER;
979 }
980
981 triggered = (i == trigger_cluster);
982 sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
983 triggered, sdi);
984 }
985
986 return SR_OK;
987}
988
989static int download_capture(struct sr_dev_inst *sdi)
990{
991 const uint32_t chunks_per_read = 32;
992
993 struct dev_context *devc;
994 struct sigma_dram_line *dram_line;
995 int bufsz;
996 uint32_t stoppos, triggerpos;
997 uint8_t modestatus;
998 uint32_t i;
999 uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
1000 uint32_t dl_first_line, dl_line;
1001 uint32_t dl_events_in_line;
1002 uint32_t trg_line, trg_event;
1003
1004 devc = sdi->priv;
1005 dl_events_in_line = 64 * 7;
1006
1007 sr_info("Downloading sample data.");
1008 devc->state.state = SIGMA_DOWNLOAD;
1009
1010 /*
1011 * Ask the hardware to stop data acquisition. Reception of the
1012 * FORCESTOP request makes the hardware "disable RLE" (store
1013 * clusters to DRAM regardless of whether pin state changes) and
1014 * raise the POSTTRIGGERED flag.
1015 */
1016 sigma_set_register(WRITE_MODE, WMR_FORCESTOP | WMR_SDRAMWRITEEN, devc);
1017 do {
1018 if (sigma_read_register(READ_MODE, &modestatus, 1, devc) != 1) {
1019 sr_err("failed while waiting for RMR_POSTTRIGGERED bit");
1020 return FALSE;
1021 }
1022 } while (!(modestatus & RMR_POSTTRIGGERED));
1023
1024 /* Set SDRAM Read Enable. */
1025 sigma_set_register(WRITE_MODE, WMR_SDRAMREADEN, devc);
1026
1027 /* Get the current position. */
1028 sigma_read_pos(&stoppos, &triggerpos, devc);
1029
1030 /* Check if trigger has fired. */
1031 if (sigma_read_register(READ_MODE, &modestatus, 1, devc) != 1) {
1032 sr_err("failed to read READ_MODE register");
1033 return FALSE;
1034 }
1035 trg_line = ~0;
1036 trg_event = ~0;
1037 if (modestatus & RMR_TRIGGERED) {
1038 trg_line = triggerpos >> 9;
1039 trg_event = triggerpos & 0x1ff;
1040 }
1041
1042 devc->sent_samples = 0;
1043
1044 /*
1045 * Determine how many "DRAM lines" of 1024 bytes each we need to
1046 * retrieve from the Sigma hardware, so that we have a complete
1047 * set of samples. Note that the last line need not contain 64
1048 * clusters, it might be partially filled only.
1049 *
1050 * When RMR_ROUND is set, the circular buffer in DRAM has wrapped
1051 * around. Since the status of the very next line is uncertain in
1052 * that case, we skip it and start reading from the next line. The
1053 * circular buffer has 32K lines (0x8000).
1054 */
1055 dl_lines_total = (stoppos >> 9) + 1;
1056 if (modestatus & RMR_ROUND) {
1057 dl_first_line = dl_lines_total + 1;
1058 dl_lines_total = 0x8000 - 2;
1059 } else {
1060 dl_first_line = 0;
1061 }
1062 dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
1063 if (!dram_line)
1064 return FALSE;
1065 dl_lines_done = 0;
1066 while (dl_lines_total > dl_lines_done) {
1067 /* We can download only up-to 32 DRAM lines in one go! */
1068 dl_lines_curr = MIN(chunks_per_read, dl_lines_total - dl_lines_done);
1069
1070 dl_line = dl_first_line + dl_lines_done;
1071 dl_line %= 0x8000;
1072 bufsz = sigma_read_dram(dl_line, dl_lines_curr,
1073 (uint8_t *)dram_line, devc);
1074 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1075 (void)bufsz;
1076
1077 /* This is the first DRAM line, so find the initial timestamp. */
1078 if (dl_lines_done == 0) {
1079 devc->state.lastts =
1080 sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
1081 devc->state.lastsample = 0;
1082 }
1083
1084 for (i = 0; i < dl_lines_curr; i++) {
1085 uint32_t trigger_event = ~0;
1086 /* The last "DRAM line" can be only partially full. */
1087 if (dl_lines_done + i == dl_lines_total - 1)
1088 dl_events_in_line = stoppos & 0x1ff;
1089
1090 /* Test if the trigger happened on this line. */
1091 if (dl_lines_done + i == trg_line)
1092 trigger_event = trg_event;
1093
1094 decode_chunk_ts(dram_line + i, dl_events_in_line,
1095 trigger_event, sdi);
1096 }
1097
1098 dl_lines_done += dl_lines_curr;
1099 }
1100 g_free(dram_line);
1101
1102 std_session_send_df_end(sdi);
1103
1104 devc->state.state = SIGMA_IDLE;
1105 sr_dev_acquisition_stop(sdi);
1106
1107 return TRUE;
1108}
1109
1110/*
1111 * Periodically check the Sigma status when in CAPTURE mode. This routine
1112 * checks whether the configured sample count or sample time have passed,
1113 * and will stop acquisition and download the acquired samples.
1114 */
1115static int sigma_capture_mode(struct sr_dev_inst *sdi)
1116{
1117 struct dev_context *devc;
1118 uint64_t running_msec;
1119 uint64_t current_time;
1120
1121 devc = sdi->priv;
1122
1123 /*
1124 * Check if the selected sampling duration passed. Sample count
1125 * limits are covered by this enforced timeout as well.
1126 */
1127 current_time = g_get_monotonic_time();
1128 running_msec = (current_time - devc->start_time) / 1000;
1129 if (running_msec >= devc->limit_msec)
1130 return download_capture(sdi);
1131
1132 return TRUE;
1133}
1134
1135SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data)
1136{
1137 struct sr_dev_inst *sdi;
1138 struct dev_context *devc;
1139
1140 (void)fd;
1141 (void)revents;
1142
1143 sdi = cb_data;
1144 devc = sdi->priv;
1145
1146 if (devc->state.state == SIGMA_IDLE)
1147 return TRUE;
1148
1149 /*
1150 * When the application has requested to stop the acquisition,
1151 * then immediately start downloading sample data. Otherwise
1152 * keep checking configured limits which will terminate the
1153 * acquisition and initiate download.
1154 */
1155 if (devc->state.state == SIGMA_STOPPING)
1156 return download_capture(sdi);
1157 if (devc->state.state == SIGMA_CAPTURE)
1158 return sigma_capture_mode(sdi);
1159
1160 return TRUE;
1161}
1162
1163/* Build a LUT entry used by the trigger functions. */
1164static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1165{
1166 int i, j, k, bit;
1167
1168 /* For each quad channel. */
1169 for (i = 0; i < 4; i++) {
1170 entry[i] = 0xffff;
1171
1172 /* For each bit in LUT. */
1173 for (j = 0; j < 16; j++)
1174
1175 /* For each channel in quad. */
1176 for (k = 0; k < 4; k++) {
1177 bit = 1 << (i * 4 + k);
1178
1179 /* Set bit in entry */
1180 if ((mask & bit) && ((!(value & bit)) !=
1181 (!(j & (1 << k)))))
1182 entry[i] &= ~(1 << j);
1183 }
1184 }
1185}
1186
1187/* Add a logical function to LUT mask. */
1188static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1189 int index, int neg, uint16_t *mask)
1190{
1191 int i, j;
1192 int x[2][2], tmp, a, b, aset, bset, rset;
1193
1194 memset(x, 0, 4 * sizeof(int));
1195
1196 /* Trigger detect condition. */
1197 switch (oper) {
1198 case OP_LEVEL:
1199 x[0][1] = 1;
1200 x[1][1] = 1;
1201 break;
1202 case OP_NOT:
1203 x[0][0] = 1;
1204 x[1][0] = 1;
1205 break;
1206 case OP_RISE:
1207 x[0][1] = 1;
1208 break;
1209 case OP_FALL:
1210 x[1][0] = 1;
1211 break;
1212 case OP_RISEFALL:
1213 x[0][1] = 1;
1214 x[1][0] = 1;
1215 break;
1216 case OP_NOTRISE:
1217 x[1][1] = 1;
1218 x[0][0] = 1;
1219 x[1][0] = 1;
1220 break;
1221 case OP_NOTFALL:
1222 x[1][1] = 1;
1223 x[0][0] = 1;
1224 x[0][1] = 1;
1225 break;
1226 case OP_NOTRISEFALL:
1227 x[1][1] = 1;
1228 x[0][0] = 1;
1229 break;
1230 }
1231
1232 /* Transpose if neg is set. */
1233 if (neg) {
1234 for (i = 0; i < 2; i++) {
1235 for (j = 0; j < 2; j++) {
1236 tmp = x[i][j];
1237 x[i][j] = x[1 - i][1 - j];
1238 x[1 - i][1 - j] = tmp;
1239 }
1240 }
1241 }
1242
1243 /* Update mask with function. */
1244 for (i = 0; i < 16; i++) {
1245 a = (i >> (2 * index + 0)) & 1;
1246 b = (i >> (2 * index + 1)) & 1;
1247
1248 aset = (*mask >> i) & 1;
1249 bset = x[b][a];
1250
1251 rset = 0;
1252 if (func == FUNC_AND || func == FUNC_NAND)
1253 rset = aset & bset;
1254 else if (func == FUNC_OR || func == FUNC_NOR)
1255 rset = aset | bset;
1256 else if (func == FUNC_XOR || func == FUNC_NXOR)
1257 rset = aset ^ bset;
1258
1259 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1260 rset = !rset;
1261
1262 *mask &= ~(1 << i);
1263
1264 if (rset)
1265 *mask |= 1 << i;
1266 }
1267}
1268
1269/*
1270 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1271 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1272 * set at any time, but a full mask and value can be set (0/1).
1273 */
1274SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1275{
1276 int i,j;
1277 uint16_t masks[2] = { 0, 0 };
1278
1279 memset(lut, 0, sizeof(struct triggerlut));
1280
1281 /* Constant for simple triggers. */
1282 lut->m4 = 0xa000;
1283
1284 /* Value/mask trigger support. */
1285 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1286 lut->m2d);
1287
1288 /* Rise/fall trigger support. */
1289 for (i = 0, j = 0; i < 16; i++) {
1290 if (devc->trigger.risingmask & (1 << i) ||
1291 devc->trigger.fallingmask & (1 << i))
1292 masks[j++] = 1 << i;
1293 }
1294
1295 build_lut_entry(masks[0], masks[0], lut->m0d);
1296 build_lut_entry(masks[1], masks[1], lut->m1d);
1297
1298 /* Add glue logic */
1299 if (masks[0] || masks[1]) {
1300 /* Transition trigger. */
1301 if (masks[0] & devc->trigger.risingmask)
1302 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1303 if (masks[0] & devc->trigger.fallingmask)
1304 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1305 if (masks[1] & devc->trigger.risingmask)
1306 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1307 if (masks[1] & devc->trigger.fallingmask)
1308 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1309 } else {
1310 /* Only value/mask trigger. */
1311 lut->m3 = 0xffff;
1312 }
1313
1314 /* Triggertype: event. */
1315 lut->params.selres = 3;
1316
1317 return SR_OK;
1318}