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1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include <unistd.h>
31#include <libsigrok/libsigrok.h>
32#include "libsigrok-internal.h"
33#include "asix-sigma.h"
34
35#define USB_VENDOR 0xa600
36#define USB_PRODUCT 0xa000
37#define USB_DESCRIPTION "ASIX SIGMA"
38#define USB_VENDOR_NAME "ASIX"
39#define USB_MODEL_NAME "SIGMA"
40
41SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
42static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
43
44/*
45 * The ASIX Sigma supports arbitrary integer frequency divider in
46 * the 50MHz mode. The divider is in range 1...256 , allowing for
47 * very precise sampling rate selection. This driver supports only
48 * a subset of the sampling rates.
49 */
50static const uint64_t samplerates[] = {
51 SR_KHZ(200), /* div=250 */
52 SR_KHZ(250), /* div=200 */
53 SR_KHZ(500), /* div=100 */
54 SR_MHZ(1), /* div=50 */
55 SR_MHZ(5), /* div=10 */
56 SR_MHZ(10), /* div=5 */
57 SR_MHZ(25), /* div=2 */
58 SR_MHZ(50), /* div=1 */
59 SR_MHZ(100), /* Special FW needed */
60 SR_MHZ(200), /* Special FW needed */
61};
62
63/*
64 * Channel numbers seem to go from 1-16, according to this image:
65 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
66 * (the cable has two additional GND pins, and a TI and TO pin)
67 */
68static const char *channel_names[] = {
69 "1", "2", "3", "4", "5", "6", "7", "8",
70 "9", "10", "11", "12", "13", "14", "15", "16",
71};
72
73static const uint32_t drvopts[] = {
74 SR_CONF_LOGIC_ANALYZER,
75};
76
77static const uint32_t devopts[] = {
78 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
79 SR_CONF_LIMIT_SAMPLES | SR_CONF_SET,
80 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
81 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
82 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
83};
84
85static const int32_t trigger_matches[] = {
86 SR_TRIGGER_ZERO,
87 SR_TRIGGER_ONE,
88 SR_TRIGGER_RISING,
89 SR_TRIGGER_FALLING,
90};
91
92static const char *sigma_firmware_files[] = {
93 /* 50 MHz, supports 8 bit fractions */
94 FIRMWARE_DIR "/asix-sigma-50.fw",
95 /* 100 MHz */
96 FIRMWARE_DIR "/asix-sigma-100.fw",
97 /* 200 MHz */
98 FIRMWARE_DIR "/asix-sigma-200.fw",
99 /* Synchronous clock from pin */
100 FIRMWARE_DIR "/asix-sigma-50sync.fw",
101 /* Frequency counter */
102 FIRMWARE_DIR "/asix-sigma-phasor.fw",
103};
104
105static int sigma_read(void *buf, size_t size, struct dev_context *devc)
106{
107 int ret;
108
109 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
110 if (ret < 0) {
111 sr_err("ftdi_read_data failed: %s",
112 ftdi_get_error_string(&devc->ftdic));
113 }
114
115 return ret;
116}
117
118static int sigma_write(void *buf, size_t size, struct dev_context *devc)
119{
120 int ret;
121
122 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
123 if (ret < 0) {
124 sr_err("ftdi_write_data failed: %s",
125 ftdi_get_error_string(&devc->ftdic));
126 } else if ((size_t) ret != size) {
127 sr_err("ftdi_write_data did not complete write.");
128 }
129
130 return ret;
131}
132
133/*
134 * NOTE: We chose the buffer size to be large enough to hold any write to the
135 * device. We still print a message just in case.
136 */
137static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
138 struct dev_context *devc)
139{
140 size_t i;
141 uint8_t buf[80];
142 int idx = 0;
143
144 if ((len + 2) > sizeof(buf)) {
145 sr_err("Attempted to write %zu bytes, but buffer is too small.",
146 len + 2);
147 return SR_ERR_BUG;
148 }
149
150 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
151 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
152
153 for (i = 0; i < len; ++i) {
154 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
155 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
156 }
157
158 return sigma_write(buf, idx, devc);
159}
160
161static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
162{
163 return sigma_write_register(reg, &value, 1, devc);
164}
165
166static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
167 struct dev_context *devc)
168{
169 uint8_t buf[3];
170
171 buf[0] = REG_ADDR_LOW | (reg & 0xf);
172 buf[1] = REG_ADDR_HIGH | (reg >> 4);
173 buf[2] = REG_READ_ADDR;
174
175 sigma_write(buf, sizeof(buf), devc);
176
177 return sigma_read(data, len, devc);
178}
179
180static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
181{
182 uint8_t value;
183
184 if (1 != sigma_read_register(reg, &value, 1, devc)) {
185 sr_err("sigma_get_register: 1 byte expected");
186 return 0;
187 }
188
189 return value;
190}
191
192static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
193 struct dev_context *devc)
194{
195 uint8_t buf[] = {
196 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
197
198 REG_READ_ADDR | NEXT_REG,
199 REG_READ_ADDR | NEXT_REG,
200 REG_READ_ADDR | NEXT_REG,
201 REG_READ_ADDR | NEXT_REG,
202 REG_READ_ADDR | NEXT_REG,
203 REG_READ_ADDR | NEXT_REG,
204 };
205 uint8_t result[6];
206
207 sigma_write(buf, sizeof(buf), devc);
208
209 sigma_read(result, sizeof(result), devc);
210
211 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
212 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
213
214 /* Not really sure why this must be done, but according to spec. */
215 if ((--*stoppos & 0x1ff) == 0x1ff)
216 *stoppos -= 64;
217
218 if ((*--triggerpos & 0x1ff) == 0x1ff)
219 *triggerpos -= 64;
220
221 return 1;
222}
223
224static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
225 uint8_t *data, struct dev_context *devc)
226{
227 size_t i;
228 uint8_t buf[4096];
229 int idx = 0;
230
231 /* Send the startchunk. Index start with 1. */
232 buf[0] = startchunk >> 8;
233 buf[1] = startchunk & 0xff;
234 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
235
236 /* Read the DRAM. */
237 buf[idx++] = REG_DRAM_BLOCK;
238 buf[idx++] = REG_DRAM_WAIT_ACK;
239
240 for (i = 0; i < numchunks; ++i) {
241 /* Alternate bit to copy from DRAM to cache. */
242 if (i != (numchunks - 1))
243 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
244
245 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
246
247 if (i != (numchunks - 1))
248 buf[idx++] = REG_DRAM_WAIT_ACK;
249 }
250
251 sigma_write(buf, idx, devc);
252
253 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
254}
255
256/* Upload trigger look-up tables to Sigma. */
257static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
258{
259 int i;
260 uint8_t tmp[2];
261 uint16_t bit;
262
263 /* Transpose the table and send to Sigma. */
264 for (i = 0; i < 16; ++i) {
265 bit = 1 << i;
266
267 tmp[0] = tmp[1] = 0;
268
269 if (lut->m2d[0] & bit)
270 tmp[0] |= 0x01;
271 if (lut->m2d[1] & bit)
272 tmp[0] |= 0x02;
273 if (lut->m2d[2] & bit)
274 tmp[0] |= 0x04;
275 if (lut->m2d[3] & bit)
276 tmp[0] |= 0x08;
277
278 if (lut->m3 & bit)
279 tmp[0] |= 0x10;
280 if (lut->m3s & bit)
281 tmp[0] |= 0x20;
282 if (lut->m4 & bit)
283 tmp[0] |= 0x40;
284
285 if (lut->m0d[0] & bit)
286 tmp[1] |= 0x01;
287 if (lut->m0d[1] & bit)
288 tmp[1] |= 0x02;
289 if (lut->m0d[2] & bit)
290 tmp[1] |= 0x04;
291 if (lut->m0d[3] & bit)
292 tmp[1] |= 0x08;
293
294 if (lut->m1d[0] & bit)
295 tmp[1] |= 0x10;
296 if (lut->m1d[1] & bit)
297 tmp[1] |= 0x20;
298 if (lut->m1d[2] & bit)
299 tmp[1] |= 0x40;
300 if (lut->m1d[3] & bit)
301 tmp[1] |= 0x80;
302
303 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
304 devc);
305 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
306 }
307
308 /* Send the parameters */
309 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
310 sizeof(lut->params), devc);
311
312 return SR_OK;
313}
314
315static void clear_helper(void *priv)
316{
317 struct dev_context *devc;
318
319 devc = priv;
320
321 ftdi_deinit(&devc->ftdic);
322}
323
324static int dev_clear(const struct sr_dev_driver *di)
325{
326 return std_dev_clear(di, clear_helper);
327}
328
329static int init(struct sr_dev_driver *di, struct sr_context *sr_ctx)
330{
331 return std_init(sr_ctx, di, LOG_PREFIX);
332}
333
334static GSList *scan(struct sr_dev_driver *di, GSList *options)
335{
336 struct sr_dev_inst *sdi;
337 struct drv_context *drvc;
338 struct dev_context *devc;
339 GSList *devices;
340 struct ftdi_device_list *devlist;
341 char serial_txt[10];
342 uint32_t serial;
343 int ret;
344 unsigned int i;
345
346 (void)options;
347
348 drvc = di->context;
349
350 devices = NULL;
351
352 devc = g_malloc0(sizeof(struct dev_context));
353
354 ftdi_init(&devc->ftdic);
355
356 /* Look for SIGMAs. */
357
358 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
359 USB_VENDOR, USB_PRODUCT)) <= 0) {
360 if (ret < 0)
361 sr_err("ftdi_usb_find_all(): %d", ret);
362 goto free;
363 }
364
365 /* Make sure it's a version 1 or 2 SIGMA. */
366 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
367 serial_txt, sizeof(serial_txt));
368 sscanf(serial_txt, "%x", &serial);
369
370 if (serial < 0xa6010000 || serial > 0xa602ffff) {
371 sr_err("Only SIGMA and SIGMA2 are supported "
372 "in this version of libsigrok.");
373 goto free;
374 }
375
376 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
377
378 devc->cur_samplerate = samplerates[0];
379 devc->period_ps = 0;
380 devc->limit_msec = 0;
381 devc->cur_firmware = -1;
382 devc->num_channels = 0;
383 devc->samples_per_event = 0;
384 devc->capture_ratio = 50;
385 devc->use_triggers = 0;
386
387 /* Register SIGMA device. */
388 sdi = g_malloc0(sizeof(struct sr_dev_inst));
389 sdi->status = SR_ST_INITIALIZING;
390 sdi->vendor = g_strdup(USB_VENDOR_NAME);
391 sdi->model = g_strdup(USB_MODEL_NAME);
392 sdi->driver = di;
393
394 for (i = 0; i < ARRAY_SIZE(channel_names); i++)
395 sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE, channel_names[i]);
396
397 devices = g_slist_append(devices, sdi);
398 drvc->instances = g_slist_append(drvc->instances, sdi);
399 sdi->priv = devc;
400
401 /* We will open the device again when we need it. */
402 ftdi_list_free(&devlist);
403
404 return devices;
405
406free:
407 ftdi_deinit(&devc->ftdic);
408 g_free(devc);
409 return NULL;
410}
411
412static GSList *dev_list(const struct sr_dev_driver *di)
413{
414 return ((struct drv_context *)(di->context))->instances;
415}
416
417/*
418 * Configure the FPGA for bitbang mode.
419 * This sequence is documented in section 2. of the ASIX Sigma programming
420 * manual. This sequence is necessary to configure the FPGA in the Sigma
421 * into Bitbang mode, in which it can be programmed with the firmware.
422 */
423static int sigma_fpga_init_bitbang(struct dev_context *devc)
424{
425 uint8_t suicide[] = {
426 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
427 };
428 uint8_t init_array[] = {
429 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
430 0x01, 0x01,
431 };
432 int i, ret, timeout = (10 * 1000);
433 uint8_t data;
434
435 /* Section 2. part 1), do the FPGA suicide. */
436 sigma_write(suicide, sizeof(suicide), devc);
437 sigma_write(suicide, sizeof(suicide), devc);
438 sigma_write(suicide, sizeof(suicide), devc);
439 sigma_write(suicide, sizeof(suicide), devc);
440
441 /* Section 2. part 2), do pulse on D1. */
442 sigma_write(init_array, sizeof(init_array), devc);
443 ftdi_usb_purge_buffers(&devc->ftdic);
444
445 /* Wait until the FPGA asserts D6/INIT_B. */
446 for (i = 0; i < timeout; i++) {
447 ret = sigma_read(&data, 1, devc);
448 if (ret < 0)
449 return ret;
450 /* Test if pin D6 got asserted. */
451 if (data & (1 << 5))
452 return 0;
453 /* The D6 was not asserted yet, wait a bit. */
454 g_usleep(10 * 1000);
455 }
456
457 return SR_ERR_TIMEOUT;
458}
459
460/*
461 * Configure the FPGA for logic-analyzer mode.
462 */
463static int sigma_fpga_init_la(struct dev_context *devc)
464{
465 /* Initialize the logic analyzer mode. */
466 uint8_t logic_mode_start[] = {
467 REG_ADDR_LOW | (READ_ID & 0xf),
468 REG_ADDR_HIGH | (READ_ID >> 8),
469 REG_READ_ADDR, /* Read ID register. */
470
471 REG_ADDR_LOW | (WRITE_TEST & 0xf),
472 REG_DATA_LOW | 0x5,
473 REG_DATA_HIGH_WRITE | 0x5,
474 REG_READ_ADDR, /* Read scratch register. */
475
476 REG_DATA_LOW | 0xa,
477 REG_DATA_HIGH_WRITE | 0xa,
478 REG_READ_ADDR, /* Read scratch register. */
479
480 REG_ADDR_LOW | (WRITE_MODE & 0xf),
481 REG_DATA_LOW | 0x0,
482 REG_DATA_HIGH_WRITE | 0x8,
483 };
484
485 uint8_t result[3];
486 int ret;
487
488 /* Initialize the logic analyzer mode. */
489 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
490
491 /* Expect a 3 byte reply since we issued three READ requests. */
492 ret = sigma_read(result, 3, devc);
493 if (ret != 3)
494 goto err;
495
496 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
497 goto err;
498
499 return SR_OK;
500err:
501 sr_err("Configuration failed. Invalid reply received.");
502 return SR_ERR;
503}
504
505/*
506 * Read the firmware from a file and transform it into a series of bitbang
507 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
508 * by the caller of this function.
509 */
510static int sigma_fw_2_bitbang(const char *filename,
511 uint8_t **bb_cmd, gsize *bb_cmd_size)
512{
513 GMappedFile *file;
514 GError *error;
515 gsize i, file_size, bb_size;
516 gchar *firmware;
517 uint8_t *bb_stream, *bbs;
518 uint32_t imm;
519 int bit, v;
520 int ret = SR_OK;
521
522 /*
523 * Map the file and make the mapped buffer writable.
524 * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped
525 * will be modified. It will not be modified until someone uses
526 * g_file_set_contents() on it.
527 */
528 error = NULL;
529 file = g_mapped_file_new(filename, TRUE, &error);
530 g_assert_no_error(error);
531
532 file_size = g_mapped_file_get_length(file);
533 firmware = g_mapped_file_get_contents(file);
534 g_assert(firmware);
535
536 /* Weird magic transformation below, I have no idea what it does. */
537 imm = 0x3f6df2ab;
538 for (i = 0; i < file_size; i++) {
539 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
540 firmware[i] ^= imm & 0xff;
541 }
542
543 /*
544 * Now that the firmware is "transformed", we will transcribe the
545 * firmware blob into a sequence of toggles of the Dx wires. This
546 * sequence will be fed directly into the Sigma, which must be in
547 * the FPGA bitbang programming mode.
548 */
549
550 /* Each bit of firmware is transcribed as two toggles of Dx wires. */
551 bb_size = file_size * 8 * 2;
552 bb_stream = (uint8_t *)g_try_malloc(bb_size);
553 if (!bb_stream) {
554 sr_err("%s: Failed to allocate bitbang stream", __func__);
555 ret = SR_ERR_MALLOC;
556 goto exit;
557 }
558
559 bbs = bb_stream;
560 for (i = 0; i < file_size; i++) {
561 for (bit = 7; bit >= 0; bit--) {
562 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
563 *bbs++ = v | 0x01;
564 *bbs++ = v;
565 }
566 }
567
568 /* The transformation completed successfully, return the result. */
569 *bb_cmd = bb_stream;
570 *bb_cmd_size = bb_size;
571
572exit:
573 g_mapped_file_unref(file);
574 return ret;
575}
576
577static int upload_firmware(int firmware_idx, struct dev_context *devc)
578{
579 int ret;
580 unsigned char *buf;
581 unsigned char pins;
582 size_t buf_size;
583 const char *firmware = sigma_firmware_files[firmware_idx];
584 struct ftdi_context *ftdic = &devc->ftdic;
585
586 /* Make sure it's an ASIX SIGMA. */
587 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
588 USB_DESCRIPTION, NULL);
589 if (ret < 0) {
590 sr_err("ftdi_usb_open failed: %s",
591 ftdi_get_error_string(ftdic));
592 return 0;
593 }
594
595 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
596 if (ret < 0) {
597 sr_err("ftdi_set_bitmode failed: %s",
598 ftdi_get_error_string(ftdic));
599 return 0;
600 }
601
602 /* Four times the speed of sigmalogan - Works well. */
603 ret = ftdi_set_baudrate(ftdic, 750 * 1000);
604 if (ret < 0) {
605 sr_err("ftdi_set_baudrate failed: %s",
606 ftdi_get_error_string(ftdic));
607 return 0;
608 }
609
610 /* Initialize the FPGA for firmware upload. */
611 ret = sigma_fpga_init_bitbang(devc);
612 if (ret)
613 return ret;
614
615 /* Prepare firmware. */
616 ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size);
617 if (ret != SR_OK) {
618 sr_err("An error occurred while reading the firmware: %s",
619 firmware);
620 return ret;
621 }
622
623 /* Upload firmware. */
624 sr_info("Uploading firmware file '%s'.", firmware);
625 sigma_write(buf, buf_size, devc);
626
627 g_free(buf);
628
629 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
630 if (ret < 0) {
631 sr_err("ftdi_set_bitmode failed: %s",
632 ftdi_get_error_string(ftdic));
633 return SR_ERR;
634 }
635
636 ftdi_usb_purge_buffers(ftdic);
637
638 /* Discard garbage. */
639 while (sigma_read(&pins, 1, devc) == 1)
640 ;
641
642 /* Initialize the FPGA for logic-analyzer mode. */
643 ret = sigma_fpga_init_la(devc);
644 if (ret != SR_OK)
645 return ret;
646
647 devc->cur_firmware = firmware_idx;
648
649 sr_info("Firmware uploaded.");
650
651 return SR_OK;
652}
653
654static int dev_open(struct sr_dev_inst *sdi)
655{
656 struct dev_context *devc;
657 int ret;
658
659 devc = sdi->priv;
660
661 /* Make sure it's an ASIX SIGMA. */
662 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
663 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
664
665 sr_err("ftdi_usb_open failed: %s",
666 ftdi_get_error_string(&devc->ftdic));
667
668 return 0;
669 }
670
671 sdi->status = SR_ST_ACTIVE;
672
673 return SR_OK;
674}
675
676static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
677{
678 struct dev_context *devc;
679 unsigned int i;
680 int ret;
681
682 devc = sdi->priv;
683 ret = SR_OK;
684
685 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
686 if (samplerates[i] == samplerate)
687 break;
688 }
689 if (samplerates[i] == 0)
690 return SR_ERR_SAMPLERATE;
691
692 if (samplerate <= SR_MHZ(50)) {
693 ret = upload_firmware(0, devc);
694 devc->num_channels = 16;
695 } else if (samplerate == SR_MHZ(100)) {
696 ret = upload_firmware(1, devc);
697 devc->num_channels = 8;
698 } else if (samplerate == SR_MHZ(200)) {
699 ret = upload_firmware(2, devc);
700 devc->num_channels = 4;
701 }
702
703 if (ret == SR_OK) {
704 devc->cur_samplerate = samplerate;
705 devc->period_ps = 1000000000000ULL / samplerate;
706 devc->samples_per_event = 16 / devc->num_channels;
707 devc->state.state = SIGMA_IDLE;
708 }
709
710 return ret;
711}
712
713/*
714 * In 100 and 200 MHz mode, only a single pin rising/falling can be
715 * set as trigger. In other modes, two rising/falling triggers can be set,
716 * in addition to value/mask trigger for any number of channels.
717 *
718 * The Sigma supports complex triggers using boolean expressions, but this
719 * has not been implemented yet.
720 */
721static int convert_trigger(const struct sr_dev_inst *sdi)
722{
723 struct dev_context *devc;
724 struct sr_trigger *trigger;
725 struct sr_trigger_stage *stage;
726 struct sr_trigger_match *match;
727 const GSList *l, *m;
728 int channelbit, trigger_set;
729
730 devc = sdi->priv;
731 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
732 if (!(trigger = sr_session_trigger_get(sdi->session)))
733 return SR_OK;
734
735 trigger_set = 0;
736 for (l = trigger->stages; l; l = l->next) {
737 stage = l->data;
738 for (m = stage->matches; m; m = m->next) {
739 match = m->data;
740 if (!match->channel->enabled)
741 /* Ignore disabled channels with a trigger. */
742 continue;
743 channelbit = 1 << (match->channel->index);
744 if (devc->cur_samplerate >= SR_MHZ(100)) {
745 /* Fast trigger support. */
746 if (trigger_set) {
747 sr_err("Only a single pin trigger is "
748 "supported in 100 and 200MHz mode.");
749 return SR_ERR;
750 }
751 if (match->match == SR_TRIGGER_FALLING)
752 devc->trigger.fallingmask |= channelbit;
753 else if (match->match == SR_TRIGGER_RISING)
754 devc->trigger.risingmask |= channelbit;
755 else {
756 sr_err("Only rising/falling trigger is "
757 "supported in 100 and 200MHz mode.");
758 return SR_ERR;
759 }
760
761 ++trigger_set;
762 } else {
763 /* Simple trigger support (event). */
764 if (match->match == SR_TRIGGER_ONE) {
765 devc->trigger.simplevalue |= channelbit;
766 devc->trigger.simplemask |= channelbit;
767 }
768 else if (match->match == SR_TRIGGER_ZERO) {
769 devc->trigger.simplevalue &= ~channelbit;
770 devc->trigger.simplemask |= channelbit;
771 }
772 else if (match->match == SR_TRIGGER_FALLING) {
773 devc->trigger.fallingmask |= channelbit;
774 ++trigger_set;
775 }
776 else if (match->match == SR_TRIGGER_RISING) {
777 devc->trigger.risingmask |= channelbit;
778 ++trigger_set;
779 }
780
781 /*
782 * Actually, Sigma supports 2 rising/falling triggers,
783 * but they are ORed and the current trigger syntax
784 * does not permit ORed triggers.
785 */
786 if (trigger_set > 1) {
787 sr_err("Only 1 rising/falling trigger "
788 "is supported.");
789 return SR_ERR;
790 }
791 }
792 }
793 }
794
795 return SR_OK;
796}
797
798static int dev_close(struct sr_dev_inst *sdi)
799{
800 struct dev_context *devc;
801
802 devc = sdi->priv;
803
804 /* TODO */
805 if (sdi->status == SR_ST_ACTIVE)
806 ftdi_usb_close(&devc->ftdic);
807
808 sdi->status = SR_ST_INACTIVE;
809
810 return SR_OK;
811}
812
813static int cleanup(const struct sr_dev_driver *di)
814{
815 return dev_clear(di);
816}
817
818static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
819 const struct sr_channel_group *cg)
820{
821 struct dev_context *devc;
822
823 (void)cg;
824
825 if (!sdi)
826 return SR_ERR;
827 devc = sdi->priv;
828
829 switch (key) {
830 case SR_CONF_SAMPLERATE:
831 *data = g_variant_new_uint64(devc->cur_samplerate);
832 break;
833 case SR_CONF_LIMIT_MSEC:
834 *data = g_variant_new_uint64(devc->limit_msec);
835 break;
836 case SR_CONF_CAPTURE_RATIO:
837 *data = g_variant_new_uint64(devc->capture_ratio);
838 break;
839 default:
840 return SR_ERR_NA;
841 }
842
843 return SR_OK;
844}
845
846static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
847 const struct sr_channel_group *cg)
848{
849 struct dev_context *devc;
850 uint64_t tmp;
851 int ret;
852
853 (void)cg;
854
855 if (sdi->status != SR_ST_ACTIVE)
856 return SR_ERR_DEV_CLOSED;
857
858 devc = sdi->priv;
859
860 ret = SR_OK;
861 switch (key) {
862 case SR_CONF_SAMPLERATE:
863 ret = set_samplerate(sdi, g_variant_get_uint64(data));
864 break;
865 case SR_CONF_LIMIT_MSEC:
866 tmp = g_variant_get_uint64(data);
867 if (tmp > 0)
868 devc->limit_msec = g_variant_get_uint64(data);
869 else
870 ret = SR_ERR;
871 break;
872 case SR_CONF_LIMIT_SAMPLES:
873 tmp = g_variant_get_uint64(data);
874 devc->limit_msec = tmp * 1000 / devc->cur_samplerate;
875 break;
876 case SR_CONF_CAPTURE_RATIO:
877 tmp = g_variant_get_uint64(data);
878 if (tmp <= 100)
879 devc->capture_ratio = tmp;
880 else
881 ret = SR_ERR;
882 break;
883 default:
884 ret = SR_ERR_NA;
885 }
886
887 return ret;
888}
889
890static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
891 const struct sr_channel_group *cg)
892{
893 GVariant *gvar;
894 GVariantBuilder gvb;
895
896 (void)cg;
897
898 switch (key) {
899 case SR_CONF_DEVICE_OPTIONS:
900 if (!sdi)
901 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
902 drvopts, ARRAY_SIZE(drvopts), sizeof(uint32_t));
903 else
904 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
905 devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
906 break;
907 case SR_CONF_SAMPLERATE:
908 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
909 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
910 ARRAY_SIZE(samplerates), sizeof(uint64_t));
911 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
912 *data = g_variant_builder_end(&gvb);
913 break;
914 case SR_CONF_TRIGGER_MATCH:
915 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
916 trigger_matches, ARRAY_SIZE(trigger_matches),
917 sizeof(int32_t));
918 break;
919 default:
920 return SR_ERR_NA;
921 }
922
923 return SR_OK;
924}
925
926/* Software trigger to determine exact trigger position. */
927static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
928 struct sigma_trigger *t)
929{
930 int i;
931 uint16_t sample = 0;
932
933 for (i = 0; i < 8; ++i) {
934 if (i > 0)
935 last_sample = sample;
936 sample = samples[2 * i] | (samples[2 * i + 1] << 8);
937
938 /* Simple triggers. */
939 if ((sample & t->simplemask) != t->simplevalue)
940 continue;
941
942 /* Rising edge. */
943 if (((last_sample & t->risingmask) != 0) ||
944 ((sample & t->risingmask) != t->risingmask))
945 continue;
946
947 /* Falling edge. */
948 if ((last_sample & t->fallingmask) != t->fallingmask ||
949 (sample & t->fallingmask) != 0)
950 continue;
951
952 break;
953 }
954
955 /* If we did not match, return original trigger pos. */
956 return i & 0x7;
957}
958
959/*
960 * Return the timestamp of "DRAM cluster".
961 */
962static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
963{
964 return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
965}
966
967static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
968 unsigned int events_in_cluster,
969 unsigned int triggered,
970 struct sr_dev_inst *sdi)
971{
972 struct dev_context *devc = sdi->priv;
973 struct sigma_state *ss = &devc->state;
974 struct sr_datafeed_packet packet;
975 struct sr_datafeed_logic logic;
976 uint16_t tsdiff, ts;
977 uint8_t samples[2048];
978 unsigned int i;
979
980 ts = sigma_dram_cluster_ts(dram_cluster);
981 tsdiff = ts - ss->lastts;
982 ss->lastts = ts;
983
984 packet.type = SR_DF_LOGIC;
985 packet.payload = &logic;
986 logic.unitsize = 2;
987 logic.data = samples;
988
989 /*
990 * First of all, send Sigrok a copy of the last sample from
991 * previous cluster as many times as needed to make up for
992 * the differential characteristics of data we get from the
993 * Sigma. Sigrok needs one sample of data per period.
994 *
995 * One DRAM cluster contains a timestamp and seven samples,
996 * the units of timestamp are "devc->period_ps" , the first
997 * sample in the cluster happens at the time of the timestamp
998 * and the remaining samples happen at timestamp +1...+6 .
999 */
1000 for (ts = 0; ts < tsdiff - (EVENTS_PER_CLUSTER - 1); ts++) {
1001 i = ts % 1024;
1002 samples[2 * i + 0] = ss->lastsample & 0xff;
1003 samples[2 * i + 1] = ss->lastsample >> 8;
1004
1005 /*
1006 * If we have 1024 samples ready or we're at the
1007 * end of submitting the padding samples, submit
1008 * the packet to Sigrok.
1009 */
1010 if ((i == 1023) || (ts == (tsdiff - EVENTS_PER_CLUSTER))) {
1011 logic.length = (i + 1) * logic.unitsize;
1012 sr_session_send(sdi, &packet);
1013 }
1014 }
1015
1016 /*
1017 * Parse the samples in current cluster and prepare them
1018 * to be submitted to Sigrok.
1019 */
1020 for (i = 0; i < events_in_cluster; i++) {
1021 samples[2 * i + 1] = dram_cluster->samples[i].sample_lo;
1022 samples[2 * i + 0] = dram_cluster->samples[i].sample_hi;
1023 }
1024
1025 /* Send data up to trigger point (if triggered). */
1026 int trigger_offset = 0;
1027 if (triggered) {
1028 /*
1029 * Trigger is not always accurate to sample because of
1030 * pipeline delay. However, it always triggers before
1031 * the actual event. We therefore look at the next
1032 * samples to pinpoint the exact position of the trigger.
1033 */
1034 trigger_offset = get_trigger_offset(samples,
1035 ss->lastsample, &devc->trigger);
1036
1037 if (trigger_offset > 0) {
1038 packet.type = SR_DF_LOGIC;
1039 logic.length = trigger_offset * logic.unitsize;
1040 sr_session_send(sdi, &packet);
1041 events_in_cluster -= trigger_offset;
1042 }
1043
1044 /* Only send trigger if explicitly enabled. */
1045 if (devc->use_triggers) {
1046 packet.type = SR_DF_TRIGGER;
1047 sr_session_send(sdi, &packet);
1048 }
1049 }
1050
1051 if (events_in_cluster > 0) {
1052 packet.type = SR_DF_LOGIC;
1053 logic.length = events_in_cluster * logic.unitsize;
1054 logic.data = samples + (trigger_offset * logic.unitsize);
1055 sr_session_send(sdi, &packet);
1056 }
1057
1058 ss->lastsample =
1059 samples[2 * (events_in_cluster - 1) + 0] |
1060 (samples[2 * (events_in_cluster - 1) + 1] << 8);
1061
1062}
1063
1064/*
1065 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
1066 * Each event is 20ns apart, and can contain multiple samples.
1067 *
1068 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
1069 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
1070 * For 50 MHz and below, events contain one sample for each channel,
1071 * spread 20 ns apart.
1072 */
1073static int decode_chunk_ts(struct sigma_dram_line *dram_line,
1074 uint16_t events_in_line,
1075 uint32_t trigger_event,
1076 struct sr_dev_inst *sdi)
1077{
1078 struct sigma_dram_cluster *dram_cluster;
1079 struct dev_context *devc = sdi->priv;
1080 unsigned int clusters_in_line =
1081 (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER;
1082 unsigned int events_in_cluster;
1083 unsigned int i;
1084 uint32_t trigger_cluster = ~0, triggered = 0;
1085
1086 /* Check if trigger is in this chunk. */
1087 if (trigger_event < (64 * 7)) {
1088 if (devc->cur_samplerate <= SR_MHZ(50)) {
1089 trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
1090 trigger_event);
1091 }
1092
1093 /* Find in which cluster the trigger occurred. */
1094 trigger_cluster = trigger_event / EVENTS_PER_CLUSTER;
1095 }
1096
1097 /* For each full DRAM cluster. */
1098 for (i = 0; i < clusters_in_line; i++) {
1099 dram_cluster = &dram_line->cluster[i];
1100
1101 /* The last cluster might not be full. */
1102 if ((i == clusters_in_line - 1) &&
1103 (events_in_line % EVENTS_PER_CLUSTER)) {
1104 events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
1105 } else {
1106 events_in_cluster = EVENTS_PER_CLUSTER;
1107 }
1108
1109 triggered = (i == trigger_cluster);
1110 sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
1111 triggered, sdi);
1112 }
1113
1114 return SR_OK;
1115}
1116
1117static int download_capture(struct sr_dev_inst *sdi)
1118{
1119 struct dev_context *devc = sdi->priv;
1120 const uint32_t chunks_per_read = 32;
1121 struct sigma_dram_line *dram_line;
1122 int bufsz;
1123 uint32_t stoppos, triggerpos;
1124 struct sr_datafeed_packet packet;
1125 uint8_t modestatus;
1126
1127 uint32_t i;
1128 uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
1129 uint32_t dl_events_in_line = 64 * 7;
1130 uint32_t trg_line = ~0, trg_event = ~0;
1131
1132 dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
1133 if (!dram_line)
1134 return FALSE;
1135
1136 sr_info("Downloading sample data.");
1137
1138 /* Stop acquisition. */
1139 sigma_set_register(WRITE_MODE, 0x11, devc);
1140
1141 /* Set SDRAM Read Enable. */
1142 sigma_set_register(WRITE_MODE, 0x02, devc);
1143
1144 /* Get the current position. */
1145 sigma_read_pos(&stoppos, &triggerpos, devc);
1146
1147 /* Check if trigger has fired. */
1148 modestatus = sigma_get_register(READ_MODE, devc);
1149 if (modestatus & 0x20) {
1150 trg_line = triggerpos >> 9;
1151 trg_event = triggerpos & 0x1ff;
1152 }
1153
1154 /*
1155 * Determine how many 1024b "DRAM lines" do we need to read from the
1156 * Sigma so we have a complete set of samples. Note that the last
1157 * line can be only partial, containing less than 64 clusters.
1158 */
1159 dl_lines_total = (stoppos >> 9) + 1;
1160
1161 dl_lines_done = 0;
1162
1163 while (dl_lines_total > dl_lines_done) {
1164 /* We can download only up-to 32 DRAM lines in one go! */
1165 dl_lines_curr = MIN(chunks_per_read, dl_lines_total);
1166
1167 bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr,
1168 (uint8_t *)dram_line, devc);
1169 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1170 (void)bufsz;
1171
1172 /* This is the first DRAM line, so find the initial timestamp. */
1173 if (dl_lines_done == 0) {
1174 devc->state.lastts =
1175 sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
1176 devc->state.lastsample = 0;
1177 }
1178
1179 for (i = 0; i < dl_lines_curr; i++) {
1180 uint32_t trigger_event = ~0;
1181 /* The last "DRAM line" can be only partially full. */
1182 if (dl_lines_done + i == dl_lines_total - 1)
1183 dl_events_in_line = stoppos & 0x1ff;
1184
1185 /* Test if the trigger happened on this line. */
1186 if (dl_lines_done + i == trg_line)
1187 trigger_event = trg_event;
1188
1189 decode_chunk_ts(dram_line + i, dl_events_in_line,
1190 trigger_event, sdi);
1191 }
1192
1193 dl_lines_done += dl_lines_curr;
1194 }
1195
1196 /* All done. */
1197 packet.type = SR_DF_END;
1198 sr_session_send(sdi, &packet);
1199
1200 dev_acquisition_stop(sdi, sdi);
1201
1202 g_free(dram_line);
1203
1204 return TRUE;
1205}
1206
1207/*
1208 * Handle the Sigma when in CAPTURE mode. This function checks:
1209 * - Sampling time ended
1210 * - DRAM capacity overflow
1211 * This function triggers download of the samples from Sigma
1212 * in case either of the above conditions is true.
1213 */
1214static int sigma_capture_mode(struct sr_dev_inst *sdi)
1215{
1216 struct dev_context *devc = sdi->priv;
1217
1218 uint64_t running_msec;
1219 struct timeval tv;
1220
1221 uint32_t stoppos, triggerpos;
1222
1223 /* Check if the selected sampling duration passed. */
1224 gettimeofday(&tv, 0);
1225 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1226 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1227 if (running_msec >= devc->limit_msec)
1228 return download_capture(sdi);
1229
1230 /* Get the position in DRAM to which the FPGA is writing now. */
1231 sigma_read_pos(&stoppos, &triggerpos, devc);
1232 /* Test if DRAM is full and if so, download the data. */
1233 if ((stoppos >> 9) == 32767)
1234 return download_capture(sdi);
1235
1236 return TRUE;
1237}
1238
1239static int receive_data(int fd, int revents, void *cb_data)
1240{
1241 struct sr_dev_inst *sdi;
1242 struct dev_context *devc;
1243
1244 (void)fd;
1245 (void)revents;
1246
1247 sdi = cb_data;
1248 devc = sdi->priv;
1249
1250 if (devc->state.state == SIGMA_IDLE)
1251 return TRUE;
1252
1253 if (devc->state.state == SIGMA_CAPTURE)
1254 return sigma_capture_mode(sdi);
1255
1256 return TRUE;
1257}
1258
1259/* Build a LUT entry used by the trigger functions. */
1260static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1261{
1262 int i, j, k, bit;
1263
1264 /* For each quad channel. */
1265 for (i = 0; i < 4; ++i) {
1266 entry[i] = 0xffff;
1267
1268 /* For each bit in LUT. */
1269 for (j = 0; j < 16; ++j)
1270
1271 /* For each channel in quad. */
1272 for (k = 0; k < 4; ++k) {
1273 bit = 1 << (i * 4 + k);
1274
1275 /* Set bit in entry */
1276 if ((mask & bit) &&
1277 ((!(value & bit)) !=
1278 (!(j & (1 << k)))))
1279 entry[i] &= ~(1 << j);
1280 }
1281 }
1282}
1283
1284/* Add a logical function to LUT mask. */
1285static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1286 int index, int neg, uint16_t *mask)
1287{
1288 int i, j;
1289 int x[2][2], tmp, a, b, aset, bset, rset;
1290
1291 memset(x, 0, 4 * sizeof(int));
1292
1293 /* Trigger detect condition. */
1294 switch (oper) {
1295 case OP_LEVEL:
1296 x[0][1] = 1;
1297 x[1][1] = 1;
1298 break;
1299 case OP_NOT:
1300 x[0][0] = 1;
1301 x[1][0] = 1;
1302 break;
1303 case OP_RISE:
1304 x[0][1] = 1;
1305 break;
1306 case OP_FALL:
1307 x[1][0] = 1;
1308 break;
1309 case OP_RISEFALL:
1310 x[0][1] = 1;
1311 x[1][0] = 1;
1312 break;
1313 case OP_NOTRISE:
1314 x[1][1] = 1;
1315 x[0][0] = 1;
1316 x[1][0] = 1;
1317 break;
1318 case OP_NOTFALL:
1319 x[1][1] = 1;
1320 x[0][0] = 1;
1321 x[0][1] = 1;
1322 break;
1323 case OP_NOTRISEFALL:
1324 x[1][1] = 1;
1325 x[0][0] = 1;
1326 break;
1327 }
1328
1329 /* Transpose if neg is set. */
1330 if (neg) {
1331 for (i = 0; i < 2; ++i) {
1332 for (j = 0; j < 2; ++j) {
1333 tmp = x[i][j];
1334 x[i][j] = x[1-i][1-j];
1335 x[1-i][1-j] = tmp;
1336 }
1337 }
1338 }
1339
1340 /* Update mask with function. */
1341 for (i = 0; i < 16; ++i) {
1342 a = (i >> (2 * index + 0)) & 1;
1343 b = (i >> (2 * index + 1)) & 1;
1344
1345 aset = (*mask >> i) & 1;
1346 bset = x[b][a];
1347
1348 rset = 0;
1349 if (func == FUNC_AND || func == FUNC_NAND)
1350 rset = aset & bset;
1351 else if (func == FUNC_OR || func == FUNC_NOR)
1352 rset = aset | bset;
1353 else if (func == FUNC_XOR || func == FUNC_NXOR)
1354 rset = aset ^ bset;
1355
1356 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1357 rset = !rset;
1358
1359 *mask &= ~(1 << i);
1360
1361 if (rset)
1362 *mask |= 1 << i;
1363 }
1364}
1365
1366/*
1367 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1368 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1369 * set at any time, but a full mask and value can be set (0/1).
1370 */
1371static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1372{
1373 int i,j;
1374 uint16_t masks[2] = { 0, 0 };
1375
1376 memset(lut, 0, sizeof(struct triggerlut));
1377
1378 /* Constant for simple triggers. */
1379 lut->m4 = 0xa000;
1380
1381 /* Value/mask trigger support. */
1382 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1383 lut->m2d);
1384
1385 /* Rise/fall trigger support. */
1386 for (i = 0, j = 0; i < 16; ++i) {
1387 if (devc->trigger.risingmask & (1 << i) ||
1388 devc->trigger.fallingmask & (1 << i))
1389 masks[j++] = 1 << i;
1390 }
1391
1392 build_lut_entry(masks[0], masks[0], lut->m0d);
1393 build_lut_entry(masks[1], masks[1], lut->m1d);
1394
1395 /* Add glue logic */
1396 if (masks[0] || masks[1]) {
1397 /* Transition trigger. */
1398 if (masks[0] & devc->trigger.risingmask)
1399 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1400 if (masks[0] & devc->trigger.fallingmask)
1401 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1402 if (masks[1] & devc->trigger.risingmask)
1403 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1404 if (masks[1] & devc->trigger.fallingmask)
1405 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1406 } else {
1407 /* Only value/mask trigger. */
1408 lut->m3 = 0xffff;
1409 }
1410
1411 /* Triggertype: event. */
1412 lut->params.selres = 3;
1413
1414 return SR_OK;
1415}
1416
1417static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
1418{
1419 struct dev_context *devc;
1420 struct clockselect_50 clockselect;
1421 int frac, triggerpin, ret;
1422 uint8_t triggerselect = 0;
1423 struct triggerinout triggerinout_conf;
1424 struct triggerlut lut;
1425
1426 if (sdi->status != SR_ST_ACTIVE)
1427 return SR_ERR_DEV_CLOSED;
1428
1429 devc = sdi->priv;
1430
1431 if (convert_trigger(sdi) != SR_OK) {
1432 sr_err("Failed to configure triggers.");
1433 return SR_ERR;
1434 }
1435
1436 /* If the samplerate has not been set, default to 200 kHz. */
1437 if (devc->cur_firmware == -1) {
1438 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1439 return ret;
1440 }
1441
1442 /* Enter trigger programming mode. */
1443 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1444
1445 /* 100 and 200 MHz mode. */
1446 if (devc->cur_samplerate >= SR_MHZ(100)) {
1447 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1448
1449 /* Find which pin to trigger on from mask. */
1450 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1451 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1452 (1 << triggerpin))
1453 break;
1454
1455 /* Set trigger pin and light LED on trigger. */
1456 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1457
1458 /* Default rising edge. */
1459 if (devc->trigger.fallingmask)
1460 triggerselect |= 1 << 3;
1461
1462 /* All other modes. */
1463 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1464 build_basic_trigger(&lut, devc);
1465
1466 sigma_write_trigger_lut(&lut, devc);
1467
1468 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1469 }
1470
1471 /* Setup trigger in and out pins to default values. */
1472 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1473 triggerinout_conf.trgout_bytrigger = 1;
1474 triggerinout_conf.trgout_enable = 1;
1475
1476 sigma_write_register(WRITE_TRIGGER_OPTION,
1477 (uint8_t *) &triggerinout_conf,
1478 sizeof(struct triggerinout), devc);
1479
1480 /* Go back to normal mode. */
1481 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1482
1483 /* Set clock select register. */
1484 if (devc->cur_samplerate == SR_MHZ(200))
1485 /* Enable 4 channels. */
1486 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1487 else if (devc->cur_samplerate == SR_MHZ(100))
1488 /* Enable 8 channels. */
1489 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1490 else {
1491 /*
1492 * 50 MHz mode (or fraction thereof). Any fraction down to
1493 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1494 */
1495 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1496
1497 clockselect.async = 0;
1498 clockselect.fraction = frac;
1499 clockselect.disabled_channels = 0;
1500
1501 sigma_write_register(WRITE_CLOCK_SELECT,
1502 (uint8_t *) &clockselect,
1503 sizeof(clockselect), devc);
1504 }
1505
1506 /* Setup maximum post trigger time. */
1507 sigma_set_register(WRITE_POST_TRIGGER,
1508 (devc->capture_ratio * 255) / 100, devc);
1509
1510 /* Start acqusition. */
1511 gettimeofday(&devc->start_tv, 0);
1512 sigma_set_register(WRITE_MODE, 0x0d, devc);
1513
1514 devc->cb_data = cb_data;
1515
1516 /* Send header packet to the session bus. */
1517 std_session_send_df_header(sdi, LOG_PREFIX);
1518
1519 /* Add capture source. */
1520 sr_session_source_add(sdi->session, 0, G_IO_IN, 10, receive_data, (void *)sdi);
1521
1522 devc->state.state = SIGMA_CAPTURE;
1523
1524 return SR_OK;
1525}
1526
1527static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1528{
1529 struct dev_context *devc;
1530
1531 (void)cb_data;
1532
1533 devc = sdi->priv;
1534 devc->state.state = SIGMA_IDLE;
1535
1536 sr_session_source_remove(sdi->session, 0);
1537
1538 return SR_OK;
1539}
1540
1541SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1542 .name = "asix-sigma",
1543 .longname = "ASIX SIGMA/SIGMA2",
1544 .api_version = 1,
1545 .init = init,
1546 .cleanup = cleanup,
1547 .scan = scan,
1548 .dev_list = dev_list,
1549 .dev_clear = dev_clear,
1550 .config_get = config_get,
1551 .config_set = config_set,
1552 .config_list = config_list,
1553 .dev_open = dev_open,
1554 .dev_close = dev_close,
1555 .dev_acquisition_start = dev_acquisition_start,
1556 .dev_acquisition_stop = dev_acquisition_stop,
1557 .context = NULL,
1558};
Hardware access and backend lib