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Removal of sdi->index, step 4: fix trivial sr_dev_inst_new() calls
[libsigrok.git] / src / hardware / asix-sigma / asix-sigma.c
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1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include <unistd.h>
31#include "libsigrok.h"
32#include "libsigrok-internal.h"
33#include "asix-sigma.h"
34
35#define USB_VENDOR 0xa600
36#define USB_PRODUCT 0xa000
37#define USB_DESCRIPTION "ASIX SIGMA"
38#define USB_VENDOR_NAME "ASIX"
39#define USB_MODEL_NAME "SIGMA"
40
41SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
42static struct sr_dev_driver *di = &asix_sigma_driver_info;
43static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
44
45/*
46 * The ASIX Sigma supports arbitrary integer frequency divider in
47 * the 50MHz mode. The divider is in range 1...256 , allowing for
48 * very precise sampling rate selection. This driver supports only
49 * a subset of the sampling rates.
50 */
51static const uint64_t samplerates[] = {
52 SR_KHZ(200), /* div=250 */
53 SR_KHZ(250), /* div=200 */
54 SR_KHZ(500), /* div=100 */
55 SR_MHZ(1), /* div=50 */
56 SR_MHZ(5), /* div=10 */
57 SR_MHZ(10), /* div=5 */
58 SR_MHZ(25), /* div=2 */
59 SR_MHZ(50), /* div=1 */
60 SR_MHZ(100), /* Special FW needed */
61 SR_MHZ(200), /* Special FW needed */
62};
63
64/*
65 * Channel numbers seem to go from 1-16, according to this image:
66 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
67 * (the cable has two additional GND pins, and a TI and TO pin)
68 */
69static const char *channel_names[] = {
70 "1", "2", "3", "4", "5", "6", "7", "8",
71 "9", "10", "11", "12", "13", "14", "15", "16",
72};
73
74static const uint32_t devopts[] = {
75 SR_CONF_LOGIC_ANALYZER,
76 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
77 SR_CONF_LIMIT_SAMPLES | SR_CONF_SET,
78 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
79 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
80 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
81};
82
83static const int32_t trigger_matches[] = {
84 SR_TRIGGER_ZERO,
85 SR_TRIGGER_ONE,
86 SR_TRIGGER_RISING,
87 SR_TRIGGER_FALLING,
88};
89
90static const char *sigma_firmware_files[] = {
91 /* 50 MHz, supports 8 bit fractions */
92 FIRMWARE_DIR "/asix-sigma-50.fw",
93 /* 100 MHz */
94 FIRMWARE_DIR "/asix-sigma-100.fw",
95 /* 200 MHz */
96 FIRMWARE_DIR "/asix-sigma-200.fw",
97 /* Synchronous clock from pin */
98 FIRMWARE_DIR "/asix-sigma-50sync.fw",
99 /* Frequency counter */
100 FIRMWARE_DIR "/asix-sigma-phasor.fw",
101};
102
103static int sigma_read(void *buf, size_t size, struct dev_context *devc)
104{
105 int ret;
106
107 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
108 if (ret < 0) {
109 sr_err("ftdi_read_data failed: %s",
110 ftdi_get_error_string(&devc->ftdic));
111 }
112
113 return ret;
114}
115
116static int sigma_write(void *buf, size_t size, struct dev_context *devc)
117{
118 int ret;
119
120 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
121 if (ret < 0) {
122 sr_err("ftdi_write_data failed: %s",
123 ftdi_get_error_string(&devc->ftdic));
124 } else if ((size_t) ret != size) {
125 sr_err("ftdi_write_data did not complete write.");
126 }
127
128 return ret;
129}
130
131static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
132 struct dev_context *devc)
133{
134 size_t i;
135 uint8_t buf[len + 2];
136 int idx = 0;
137
138 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
139 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
140
141 for (i = 0; i < len; ++i) {
142 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
143 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
144 }
145
146 return sigma_write(buf, idx, devc);
147}
148
149static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
150{
151 return sigma_write_register(reg, &value, 1, devc);
152}
153
154static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
155 struct dev_context *devc)
156{
157 uint8_t buf[3];
158
159 buf[0] = REG_ADDR_LOW | (reg & 0xf);
160 buf[1] = REG_ADDR_HIGH | (reg >> 4);
161 buf[2] = REG_READ_ADDR;
162
163 sigma_write(buf, sizeof(buf), devc);
164
165 return sigma_read(data, len, devc);
166}
167
168static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
169{
170 uint8_t value;
171
172 if (1 != sigma_read_register(reg, &value, 1, devc)) {
173 sr_err("sigma_get_register: 1 byte expected");
174 return 0;
175 }
176
177 return value;
178}
179
180static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
181 struct dev_context *devc)
182{
183 uint8_t buf[] = {
184 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
185
186 REG_READ_ADDR | NEXT_REG,
187 REG_READ_ADDR | NEXT_REG,
188 REG_READ_ADDR | NEXT_REG,
189 REG_READ_ADDR | NEXT_REG,
190 REG_READ_ADDR | NEXT_REG,
191 REG_READ_ADDR | NEXT_REG,
192 };
193 uint8_t result[6];
194
195 sigma_write(buf, sizeof(buf), devc);
196
197 sigma_read(result, sizeof(result), devc);
198
199 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
200 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
201
202 /* Not really sure why this must be done, but according to spec. */
203 if ((--*stoppos & 0x1ff) == 0x1ff)
204 stoppos -= 64;
205
206 if ((*--triggerpos & 0x1ff) == 0x1ff)
207 triggerpos -= 64;
208
209 return 1;
210}
211
212static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
213 uint8_t *data, struct dev_context *devc)
214{
215 size_t i;
216 uint8_t buf[4096];
217 int idx = 0;
218
219 /* Send the startchunk. Index start with 1. */
220 buf[0] = startchunk >> 8;
221 buf[1] = startchunk & 0xff;
222 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
223
224 /* Read the DRAM. */
225 buf[idx++] = REG_DRAM_BLOCK;
226 buf[idx++] = REG_DRAM_WAIT_ACK;
227
228 for (i = 0; i < numchunks; ++i) {
229 /* Alternate bit to copy from DRAM to cache. */
230 if (i != (numchunks - 1))
231 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
232
233 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
234
235 if (i != (numchunks - 1))
236 buf[idx++] = REG_DRAM_WAIT_ACK;
237 }
238
239 sigma_write(buf, idx, devc);
240
241 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
242}
243
244/* Upload trigger look-up tables to Sigma. */
245static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
246{
247 int i;
248 uint8_t tmp[2];
249 uint16_t bit;
250
251 /* Transpose the table and send to Sigma. */
252 for (i = 0; i < 16; ++i) {
253 bit = 1 << i;
254
255 tmp[0] = tmp[1] = 0;
256
257 if (lut->m2d[0] & bit)
258 tmp[0] |= 0x01;
259 if (lut->m2d[1] & bit)
260 tmp[0] |= 0x02;
261 if (lut->m2d[2] & bit)
262 tmp[0] |= 0x04;
263 if (lut->m2d[3] & bit)
264 tmp[0] |= 0x08;
265
266 if (lut->m3 & bit)
267 tmp[0] |= 0x10;
268 if (lut->m3s & bit)
269 tmp[0] |= 0x20;
270 if (lut->m4 & bit)
271 tmp[0] |= 0x40;
272
273 if (lut->m0d[0] & bit)
274 tmp[1] |= 0x01;
275 if (lut->m0d[1] & bit)
276 tmp[1] |= 0x02;
277 if (lut->m0d[2] & bit)
278 tmp[1] |= 0x04;
279 if (lut->m0d[3] & bit)
280 tmp[1] |= 0x08;
281
282 if (lut->m1d[0] & bit)
283 tmp[1] |= 0x10;
284 if (lut->m1d[1] & bit)
285 tmp[1] |= 0x20;
286 if (lut->m1d[2] & bit)
287 tmp[1] |= 0x40;
288 if (lut->m1d[3] & bit)
289 tmp[1] |= 0x80;
290
291 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
292 devc);
293 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
294 }
295
296 /* Send the parameters */
297 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
298 sizeof(lut->params), devc);
299
300 return SR_OK;
301}
302
303static void clear_helper(void *priv)
304{
305 struct dev_context *devc;
306
307 devc = priv;
308
309 ftdi_deinit(&devc->ftdic);
310}
311
312static int dev_clear(void)
313{
314 return std_dev_clear(di, clear_helper);
315}
316
317static int init(struct sr_context *sr_ctx)
318{
319 return std_init(sr_ctx, di, LOG_PREFIX);
320}
321
322static GSList *scan(GSList *options)
323{
324 struct sr_dev_inst *sdi;
325 struct sr_channel *ch;
326 struct drv_context *drvc;
327 struct dev_context *devc;
328 GSList *devices;
329 struct ftdi_device_list *devlist;
330 char serial_txt[10];
331 uint32_t serial;
332 int ret;
333 unsigned int i;
334
335 (void)options;
336
337 drvc = di->priv;
338
339 devices = NULL;
340
341 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
342 sr_err("%s: devc malloc failed", __func__);
343 return NULL;
344 }
345
346 ftdi_init(&devc->ftdic);
347
348 /* Look for SIGMAs. */
349
350 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
351 USB_VENDOR, USB_PRODUCT)) <= 0) {
352 if (ret < 0)
353 sr_err("ftdi_usb_find_all(): %d", ret);
354 goto free;
355 }
356
357 /* Make sure it's a version 1 or 2 SIGMA. */
358 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
359 serial_txt, sizeof(serial_txt));
360 sscanf(serial_txt, "%x", &serial);
361
362 if (serial < 0xa6010000 || serial > 0xa602ffff) {
363 sr_err("Only SIGMA and SIGMA2 are supported "
364 "in this version of libsigrok.");
365 goto free;
366 }
367
368 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
369
370 devc->cur_samplerate = samplerates[0];
371 devc->period_ps = 0;
372 devc->limit_msec = 0;
373 devc->cur_firmware = -1;
374 devc->num_channels = 0;
375 devc->samples_per_event = 0;
376 devc->capture_ratio = 50;
377 devc->use_triggers = 0;
378
379 /* Register SIGMA device. */
380 if (!(sdi = sr_dev_inst_new(SR_ST_INITIALIZING, USB_VENDOR_NAME,
381 USB_MODEL_NAME, NULL))) {
382 sr_err("%s: sdi was NULL", __func__);
383 goto free;
384 }
385 sdi->driver = di;
386
387 for (i = 0; i < ARRAY_SIZE(channel_names); i++) {
388 ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE,
389 channel_names[i]);
390 if (!ch)
391 return NULL;
392 sdi->channels = g_slist_append(sdi->channels, ch);
393 }
394
395 devices = g_slist_append(devices, sdi);
396 drvc->instances = g_slist_append(drvc->instances, sdi);
397 sdi->priv = devc;
398
399 /* We will open the device again when we need it. */
400 ftdi_list_free(&devlist);
401
402 return devices;
403
404free:
405 ftdi_deinit(&devc->ftdic);
406 g_free(devc);
407 return NULL;
408}
409
410static GSList *dev_list(void)
411{
412 return ((struct drv_context *)(di->priv))->instances;
413}
414
415/*
416 * Configure the FPGA for bitbang mode.
417 * This sequence is documented in section 2. of the ASIX Sigma programming
418 * manual. This sequence is necessary to configure the FPGA in the Sigma
419 * into Bitbang mode, in which it can be programmed with the firmware.
420 */
421static int sigma_fpga_init_bitbang(struct dev_context *devc)
422{
423 uint8_t suicide[] = {
424 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
425 };
426 uint8_t init_array[] = {
427 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
428 0x01, 0x01,
429 };
430 int i, ret, timeout = 10000;
431 uint8_t data;
432
433 /* Section 2. part 1), do the FPGA suicide. */
434 sigma_write(suicide, sizeof(suicide), devc);
435 sigma_write(suicide, sizeof(suicide), devc);
436 sigma_write(suicide, sizeof(suicide), devc);
437 sigma_write(suicide, sizeof(suicide), devc);
438
439 /* Section 2. part 2), do pulse on D1. */
440 sigma_write(init_array, sizeof(init_array), devc);
441 ftdi_usb_purge_buffers(&devc->ftdic);
442
443 /* Wait until the FPGA asserts D6/INIT_B. */
444 for (i = 0; i < timeout; i++) {
445 ret = sigma_read(&data, 1, devc);
446 if (ret < 0)
447 return ret;
448 /* Test if pin D6 got asserted. */
449 if (data & (1 << 5))
450 return 0;
451 /* The D6 was not asserted yet, wait a bit. */
452 usleep(10000);
453 }
454
455 return SR_ERR_TIMEOUT;
456}
457
458/*
459 * Configure the FPGA for logic-analyzer mode.
460 */
461static int sigma_fpga_init_la(struct dev_context *devc)
462{
463 /* Initialize the logic analyzer mode. */
464 uint8_t logic_mode_start[] = {
465 REG_ADDR_LOW | (READ_ID & 0xf),
466 REG_ADDR_HIGH | (READ_ID >> 8),
467 REG_READ_ADDR, /* Read ID register. */
468
469 REG_ADDR_LOW | (WRITE_TEST & 0xf),
470 REG_DATA_LOW | 0x5,
471 REG_DATA_HIGH_WRITE | 0x5,
472 REG_READ_ADDR, /* Read scratch register. */
473
474 REG_DATA_LOW | 0xa,
475 REG_DATA_HIGH_WRITE | 0xa,
476 REG_READ_ADDR, /* Read scratch register. */
477
478 REG_ADDR_LOW | (WRITE_MODE & 0xf),
479 REG_DATA_LOW | 0x0,
480 REG_DATA_HIGH_WRITE | 0x8,
481 };
482
483 uint8_t result[3];
484 int ret;
485
486 /* Initialize the logic analyzer mode. */
487 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
488
489 /* Expect a 3 byte reply since we issued three READ requests. */
490 ret = sigma_read(result, 3, devc);
491 if (ret != 3)
492 goto err;
493
494 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
495 goto err;
496
497 return SR_OK;
498err:
499 sr_err("Configuration failed. Invalid reply received.");
500 return SR_ERR;
501}
502
503/*
504 * Read the firmware from a file and transform it into a series of bitbang
505 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
506 * by the caller of this function.
507 */
508static int sigma_fw_2_bitbang(const char *filename,
509 uint8_t **bb_cmd, gsize *bb_cmd_size)
510{
511 GMappedFile *file;
512 GError *error;
513 gsize i, file_size, bb_size;
514 gchar *firmware;
515 uint8_t *bb_stream, *bbs;
516 uint32_t imm;
517 int bit, v;
518 int ret = SR_OK;
519
520 /*
521 * Map the file and make the mapped buffer writable.
522 * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped
523 * will be modified. It will not be modified until someone uses
524 * g_file_set_contents() on it.
525 */
526 error = NULL;
527 file = g_mapped_file_new(filename, TRUE, &error);
528 g_assert_no_error(error);
529
530 file_size = g_mapped_file_get_length(file);
531 firmware = g_mapped_file_get_contents(file);
532 g_assert(firmware);
533
534 /* Weird magic transformation below, I have no idea what it does. */
535 imm = 0x3f6df2ab;
536 for (i = 0; i < file_size; i++) {
537 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
538 firmware[i] ^= imm & 0xff;
539 }
540
541 /*
542 * Now that the firmware is "transformed", we will transcribe the
543 * firmware blob into a sequence of toggles of the Dx wires. This
544 * sequence will be fed directly into the Sigma, which must be in
545 * the FPGA bitbang programming mode.
546 */
547
548 /* Each bit of firmware is transcribed as two toggles of Dx wires. */
549 bb_size = file_size * 8 * 2;
550 bb_stream = (uint8_t *)g_try_malloc(bb_size);
551 if (!bb_stream) {
552 sr_err("%s: Failed to allocate bitbang stream", __func__);
553 ret = SR_ERR_MALLOC;
554 goto exit;
555 }
556
557 bbs = bb_stream;
558 for (i = 0; i < file_size; i++) {
559 for (bit = 7; bit >= 0; bit--) {
560 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
561 *bbs++ = v | 0x01;
562 *bbs++ = v;
563 }
564 }
565
566 /* The transformation completed successfully, return the result. */
567 *bb_cmd = bb_stream;
568 *bb_cmd_size = bb_size;
569
570exit:
571 g_mapped_file_unref(file);
572 return ret;
573}
574
575static int upload_firmware(int firmware_idx, struct dev_context *devc)
576{
577 int ret;
578 unsigned char *buf;
579 unsigned char pins;
580 size_t buf_size;
581 const char *firmware = sigma_firmware_files[firmware_idx];
582 struct ftdi_context *ftdic = &devc->ftdic;
583
584 /* Make sure it's an ASIX SIGMA. */
585 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
586 USB_DESCRIPTION, NULL);
587 if (ret < 0) {
588 sr_err("ftdi_usb_open failed: %s",
589 ftdi_get_error_string(ftdic));
590 return 0;
591 }
592
593 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
594 if (ret < 0) {
595 sr_err("ftdi_set_bitmode failed: %s",
596 ftdi_get_error_string(ftdic));
597 return 0;
598 }
599
600 /* Four times the speed of sigmalogan - Works well. */
601 ret = ftdi_set_baudrate(ftdic, 750000);
602 if (ret < 0) {
603 sr_err("ftdi_set_baudrate failed: %s",
604 ftdi_get_error_string(ftdic));
605 return 0;
606 }
607
608 /* Initialize the FPGA for firmware upload. */
609 ret = sigma_fpga_init_bitbang(devc);
610 if (ret)
611 return ret;
612
613 /* Prepare firmware. */
614 ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size);
615 if (ret != SR_OK) {
616 sr_err("An error occured while reading the firmware: %s",
617 firmware);
618 return ret;
619 }
620
621 /* Upload firmare. */
622 sr_info("Uploading firmware file '%s'.", firmware);
623 sigma_write(buf, buf_size, devc);
624
625 g_free(buf);
626
627 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
628 if (ret < 0) {
629 sr_err("ftdi_set_bitmode failed: %s",
630 ftdi_get_error_string(ftdic));
631 return SR_ERR;
632 }
633
634 ftdi_usb_purge_buffers(ftdic);
635
636 /* Discard garbage. */
637 while (sigma_read(&pins, 1, devc) == 1)
638 ;
639
640 /* Initialize the FPGA for logic-analyzer mode. */
641 ret = sigma_fpga_init_la(devc);
642 if (ret != SR_OK)
643 return ret;
644
645 devc->cur_firmware = firmware_idx;
646
647 sr_info("Firmware uploaded.");
648
649 return SR_OK;
650}
651
652static int dev_open(struct sr_dev_inst *sdi)
653{
654 struct dev_context *devc;
655 int ret;
656
657 devc = sdi->priv;
658
659 /* Make sure it's an ASIX SIGMA. */
660 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
661 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
662
663 sr_err("ftdi_usb_open failed: %s",
664 ftdi_get_error_string(&devc->ftdic));
665
666 return 0;
667 }
668
669 sdi->status = SR_ST_ACTIVE;
670
671 return SR_OK;
672}
673
674static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
675{
676 struct dev_context *devc;
677 unsigned int i;
678 int ret;
679
680 devc = sdi->priv;
681 ret = SR_OK;
682
683 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
684 if (samplerates[i] == samplerate)
685 break;
686 }
687 if (samplerates[i] == 0)
688 return SR_ERR_SAMPLERATE;
689
690 if (samplerate <= SR_MHZ(50)) {
691 ret = upload_firmware(0, devc);
692 devc->num_channels = 16;
693 } else if (samplerate == SR_MHZ(100)) {
694 ret = upload_firmware(1, devc);
695 devc->num_channels = 8;
696 } else if (samplerate == SR_MHZ(200)) {
697 ret = upload_firmware(2, devc);
698 devc->num_channels = 4;
699 }
700
701 if (ret == SR_OK) {
702 devc->cur_samplerate = samplerate;
703 devc->period_ps = 1000000000000ULL / samplerate;
704 devc->samples_per_event = 16 / devc->num_channels;
705 devc->state.state = SIGMA_IDLE;
706 }
707
708 return ret;
709}
710
711/*
712 * In 100 and 200 MHz mode, only a single pin rising/falling can be
713 * set as trigger. In other modes, two rising/falling triggers can be set,
714 * in addition to value/mask trigger for any number of channels.
715 *
716 * The Sigma supports complex triggers using boolean expressions, but this
717 * has not been implemented yet.
718 */
719static int convert_trigger(const struct sr_dev_inst *sdi)
720{
721 struct dev_context *devc;
722 struct sr_trigger *trigger;
723 struct sr_trigger_stage *stage;
724 struct sr_trigger_match *match;
725 const GSList *l, *m;
726 int channelbit, trigger_set;
727
728 devc = sdi->priv;
729 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
730 if (!(trigger = sr_session_trigger_get(sdi->session)))
731 return SR_OK;
732
733 trigger_set = 0;
734 for (l = trigger->stages; l; l = l->next) {
735 stage = l->data;
736 for (m = stage->matches; m; m = m->next) {
737 match = m->data;
738 if (!match->channel->enabled)
739 /* Ignore disabled channels with a trigger. */
740 continue;
741 channelbit = 1 << (match->channel->index);
742 if (devc->cur_samplerate >= SR_MHZ(100)) {
743 /* Fast trigger support. */
744 if (trigger_set) {
745 sr_err("Only a single pin trigger is "
746 "supported in 100 and 200MHz mode.");
747 return SR_ERR;
748 }
749 if (match->match == SR_TRIGGER_FALLING)
750 devc->trigger.fallingmask |= channelbit;
751 else if (match->match == SR_TRIGGER_RISING)
752 devc->trigger.risingmask |= channelbit;
753 else {
754 sr_err("Only rising/falling trigger is "
755 "supported in 100 and 200MHz mode.");
756 return SR_ERR;
757 }
758
759 ++trigger_set;
760 } else {
761 /* Simple trigger support (event). */
762 if (match->match == SR_TRIGGER_ONE) {
763 devc->trigger.simplevalue |= channelbit;
764 devc->trigger.simplemask |= channelbit;
765 }
766 else if (match->match == SR_TRIGGER_ZERO) {
767 devc->trigger.simplevalue &= ~channelbit;
768 devc->trigger.simplemask |= channelbit;
769 }
770 else if (match->match == SR_TRIGGER_FALLING) {
771 devc->trigger.fallingmask |= channelbit;
772 ++trigger_set;
773 }
774 else if (match->match == SR_TRIGGER_RISING) {
775 devc->trigger.risingmask |= channelbit;
776 ++trigger_set;
777 }
778
779 /*
780 * Actually, Sigma supports 2 rising/falling triggers,
781 * but they are ORed and the current trigger syntax
782 * does not permit ORed triggers.
783 */
784 if (trigger_set > 1) {
785 sr_err("Only 1 rising/falling trigger "
786 "is supported.");
787 return SR_ERR;
788 }
789 }
790 }
791 }
792
793
794 return SR_OK;
795}
796
797static int dev_close(struct sr_dev_inst *sdi)
798{
799 struct dev_context *devc;
800
801 devc = sdi->priv;
802
803 /* TODO */
804 if (sdi->status == SR_ST_ACTIVE)
805 ftdi_usb_close(&devc->ftdic);
806
807 sdi->status = SR_ST_INACTIVE;
808
809 return SR_OK;
810}
811
812static int cleanup(void)
813{
814 return dev_clear();
815}
816
817static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
818 const struct sr_channel_group *cg)
819{
820 struct dev_context *devc;
821
822 (void)cg;
823
824 if (!sdi)
825 return SR_ERR;
826 devc = sdi->priv;
827
828 switch (key) {
829 case SR_CONF_SAMPLERATE:
830 *data = g_variant_new_uint64(devc->cur_samplerate);
831 break;
832 case SR_CONF_LIMIT_MSEC:
833 *data = g_variant_new_uint64(devc->limit_msec);
834 break;
835 case SR_CONF_CAPTURE_RATIO:
836 *data = g_variant_new_uint64(devc->capture_ratio);
837 break;
838 default:
839 return SR_ERR_NA;
840 }
841
842 return SR_OK;
843}
844
845static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
846 const struct sr_channel_group *cg)
847{
848 struct dev_context *devc;
849 uint64_t tmp;
850 int ret;
851
852 (void)cg;
853
854 if (sdi->status != SR_ST_ACTIVE)
855 return SR_ERR_DEV_CLOSED;
856
857 devc = sdi->priv;
858
859 ret = SR_OK;
860 switch (key) {
861 case SR_CONF_SAMPLERATE:
862 ret = set_samplerate(sdi, g_variant_get_uint64(data));
863 break;
864 case SR_CONF_LIMIT_MSEC:
865 tmp = g_variant_get_uint64(data);
866 if (tmp > 0)
867 devc->limit_msec = g_variant_get_uint64(data);
868 else
869 ret = SR_ERR;
870 break;
871 case SR_CONF_LIMIT_SAMPLES:
872 tmp = g_variant_get_uint64(data);
873 devc->limit_msec = tmp * 1000 / devc->cur_samplerate;
874 break;
875 case SR_CONF_CAPTURE_RATIO:
876 tmp = g_variant_get_uint64(data);
877 if (tmp <= 100)
878 devc->capture_ratio = tmp;
879 else
880 ret = SR_ERR;
881 break;
882 default:
883 ret = SR_ERR_NA;
884 }
885
886 return ret;
887}
888
889static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
890 const struct sr_channel_group *cg)
891{
892 GVariant *gvar;
893 GVariantBuilder gvb;
894
895 (void)sdi;
896 (void)cg;
897
898 switch (key) {
899 case SR_CONF_DEVICE_OPTIONS:
900 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
901 devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
902 break;
903 case SR_CONF_SAMPLERATE:
904 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
905 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
906 ARRAY_SIZE(samplerates), sizeof(uint64_t));
907 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
908 *data = g_variant_builder_end(&gvb);
909 break;
910 case SR_CONF_TRIGGER_MATCH:
911 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
912 trigger_matches, ARRAY_SIZE(trigger_matches),
913 sizeof(int32_t));
914 break;
915 default:
916 return SR_ERR_NA;
917 }
918
919 return SR_OK;
920}
921
922/* Software trigger to determine exact trigger position. */
923static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
924 struct sigma_trigger *t)
925{
926 int i;
927 uint16_t sample = 0;
928
929 for (i = 0; i < 8; ++i) {
930 if (i > 0)
931 last_sample = sample;
932 sample = samples[2 * i] | (samples[2 * i + 1] << 8);
933
934 /* Simple triggers. */
935 if ((sample & t->simplemask) != t->simplevalue)
936 continue;
937
938 /* Rising edge. */
939 if (((last_sample & t->risingmask) != 0) ||
940 ((sample & t->risingmask) != t->risingmask))
941 continue;
942
943 /* Falling edge. */
944 if ((last_sample & t->fallingmask) != t->fallingmask ||
945 (sample & t->fallingmask) != 0)
946 continue;
947
948 break;
949 }
950
951 /* If we did not match, return original trigger pos. */
952 return i & 0x7;
953}
954
955
956/*
957 * Return the timestamp of "DRAM cluster".
958 */
959static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
960{
961 return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
962}
963
964static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
965 unsigned int events_in_cluster,
966 unsigned int triggered,
967 struct sr_dev_inst *sdi)
968{
969 struct dev_context *devc = sdi->priv;
970 struct sigma_state *ss = &devc->state;
971 struct sr_datafeed_packet packet;
972 struct sr_datafeed_logic logic;
973 uint16_t tsdiff, ts;
974 uint8_t samples[2048];
975 unsigned int i;
976
977 ts = sigma_dram_cluster_ts(dram_cluster);
978 tsdiff = ts - ss->lastts;
979 ss->lastts = ts;
980
981 packet.type = SR_DF_LOGIC;
982 packet.payload = &logic;
983 logic.unitsize = 2;
984 logic.data = samples;
985
986 /*
987 * First of all, send Sigrok a copy of the last sample from
988 * previous cluster as many times as needed to make up for
989 * the differential characteristics of data we get from the
990 * Sigma. Sigrok needs one sample of data per period.
991 *
992 * One DRAM cluster contains a timestamp and seven samples,
993 * the units of timestamp are "devc->period_ps" , the first
994 * sample in the cluster happens at the time of the timestamp
995 * and the remaining samples happen at timestamp +1...+6 .
996 */
997 for (ts = 0; ts < tsdiff - (EVENTS_PER_CLUSTER - 1); ts++) {
998 i = ts % 1024;
999 samples[2 * i + 0] = ss->lastsample & 0xff;
1000 samples[2 * i + 1] = ss->lastsample >> 8;
1001
1002 /*
1003 * If we have 1024 samples ready or we're at the
1004 * end of submitting the padding samples, submit
1005 * the packet to Sigrok.
1006 */
1007 if ((i == 1023) || (ts == (tsdiff - EVENTS_PER_CLUSTER))) {
1008 logic.length = (i + 1) * logic.unitsize;
1009 sr_session_send(sdi, &packet);
1010 }
1011 }
1012
1013 /*
1014 * Parse the samples in current cluster and prepare them
1015 * to be submitted to Sigrok.
1016 */
1017 for (i = 0; i < events_in_cluster; i++) {
1018 samples[2 * i + 1] = dram_cluster->samples[i].sample_lo;
1019 samples[2 * i + 0] = dram_cluster->samples[i].sample_hi;
1020 }
1021
1022 /* Send data up to trigger point (if triggered). */
1023 int trigger_offset = 0;
1024 if (triggered) {
1025 /*
1026 * Trigger is not always accurate to sample because of
1027 * pipeline delay. However, it always triggers before
1028 * the actual event. We therefore look at the next
1029 * samples to pinpoint the exact position of the trigger.
1030 */
1031 trigger_offset = get_trigger_offset(samples,
1032 ss->lastsample, &devc->trigger);
1033
1034 if (trigger_offset > 0) {
1035 packet.type = SR_DF_LOGIC;
1036 logic.length = trigger_offset * logic.unitsize;
1037 sr_session_send(sdi, &packet);
1038 events_in_cluster -= trigger_offset;
1039 }
1040
1041 /* Only send trigger if explicitly enabled. */
1042 if (devc->use_triggers) {
1043 packet.type = SR_DF_TRIGGER;
1044 sr_session_send(sdi, &packet);
1045 }
1046 }
1047
1048 if (events_in_cluster > 0) {
1049 packet.type = SR_DF_LOGIC;
1050 logic.length = events_in_cluster * logic.unitsize;
1051 logic.data = samples + (trigger_offset * logic.unitsize);
1052 sr_session_send(sdi, &packet);
1053 }
1054
1055 ss->lastsample =
1056 samples[2 * (events_in_cluster - 1) + 0] |
1057 (samples[2 * (events_in_cluster - 1) + 1] << 8);
1058
1059}
1060
1061/*
1062 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
1063 * Each event is 20ns apart, and can contain multiple samples.
1064 *
1065 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
1066 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
1067 * For 50 MHz and below, events contain one sample for each channel,
1068 * spread 20 ns apart.
1069 */
1070static int decode_chunk_ts(struct sigma_dram_line *dram_line,
1071 uint16_t events_in_line,
1072 uint32_t trigger_event,
1073 struct sr_dev_inst *sdi)
1074{
1075 struct sigma_dram_cluster *dram_cluster;
1076 struct dev_context *devc = sdi->priv;
1077 unsigned int clusters_in_line =
1078 (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER;
1079 unsigned int events_in_cluster;
1080 unsigned int i;
1081 uint32_t trigger_cluster = ~0, triggered = 0;
1082
1083 /* Check if trigger is in this chunk. */
1084 if (trigger_event < (64 * 7)) {
1085 if (devc->cur_samplerate <= SR_MHZ(50)) {
1086 trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
1087 trigger_event);
1088 }
1089
1090 /* Find in which cluster the trigger occured. */
1091 trigger_cluster = trigger_event / EVENTS_PER_CLUSTER;
1092 }
1093
1094 /* For each full DRAM cluster. */
1095 for (i = 0; i < clusters_in_line; i++) {
1096 dram_cluster = &dram_line->cluster[i];
1097
1098 /* The last cluster might not be full. */
1099 if ((i == clusters_in_line - 1) &&
1100 (events_in_line % EVENTS_PER_CLUSTER)) {
1101 events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
1102 } else {
1103 events_in_cluster = EVENTS_PER_CLUSTER;
1104 }
1105
1106 triggered = (i == trigger_cluster);
1107 sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
1108 triggered, sdi);
1109 }
1110
1111 return SR_OK;
1112}
1113
1114static int download_capture(struct sr_dev_inst *sdi)
1115{
1116 struct dev_context *devc = sdi->priv;
1117 const uint32_t chunks_per_read = 32;
1118 struct sigma_dram_line *dram_line;
1119 int bufsz;
1120 uint32_t stoppos, triggerpos;
1121 struct sr_datafeed_packet packet;
1122 uint8_t modestatus;
1123
1124 uint32_t i;
1125 uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
1126 uint32_t dl_events_in_line = 64 * 7;
1127 uint32_t trg_line = ~0, trg_event = ~0;
1128
1129 dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
1130 if (!dram_line)
1131 return FALSE;
1132
1133 sr_info("Downloading sample data.");
1134
1135 /* Stop acquisition. */
1136 sigma_set_register(WRITE_MODE, 0x11, devc);
1137
1138 /* Set SDRAM Read Enable. */
1139 sigma_set_register(WRITE_MODE, 0x02, devc);
1140
1141 /* Get the current position. */
1142 sigma_read_pos(&stoppos, &triggerpos, devc);
1143
1144 /* Check if trigger has fired. */
1145 modestatus = sigma_get_register(READ_MODE, devc);
1146 if (modestatus & 0x20) {
1147 trg_line = triggerpos >> 9;
1148 trg_event = triggerpos & 0x1ff;
1149 }
1150
1151 /*
1152 * Determine how many 1024b "DRAM lines" do we need to read from the
1153 * Sigma so we have a complete set of samples. Note that the last
1154 * line can be only partial, containing less than 64 clusters.
1155 */
1156 dl_lines_total = (stoppos >> 9) + 1;
1157
1158 dl_lines_done = 0;
1159
1160 while (dl_lines_total > dl_lines_done) {
1161 /* We can download only up-to 32 DRAM lines in one go! */
1162 dl_lines_curr = MIN(chunks_per_read, dl_lines_total);
1163
1164 bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr,
1165 (uint8_t *)dram_line, devc);
1166 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1167 (void)bufsz;
1168
1169 /* This is the first DRAM line, so find the initial timestamp. */
1170 if (dl_lines_done == 0) {
1171 devc->state.lastts =
1172 sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
1173 devc->state.lastsample = 0;
1174 }
1175
1176 for (i = 0; i < dl_lines_curr; i++) {
1177 uint32_t trigger_event = ~0;
1178 /* The last "DRAM line" can be only partially full. */
1179 if (dl_lines_done + i == dl_lines_total - 1)
1180 dl_events_in_line = stoppos & 0x1ff;
1181
1182 /* Test if the trigger happened on this line. */
1183 if (dl_lines_done + i == trg_line)
1184 trigger_event = trg_event;
1185
1186 decode_chunk_ts(dram_line + i, dl_events_in_line,
1187 trigger_event, sdi);
1188 }
1189
1190 dl_lines_done += dl_lines_curr;
1191 }
1192
1193 /* All done. */
1194 packet.type = SR_DF_END;
1195 sr_session_send(sdi, &packet);
1196
1197 dev_acquisition_stop(sdi, sdi);
1198
1199 g_free(dram_line);
1200
1201 return TRUE;
1202}
1203
1204/*
1205 * Handle the Sigma when in CAPTURE mode. This function checks:
1206 * - Sampling time ended
1207 * - DRAM capacity overflow
1208 * This function triggers download of the samples from Sigma
1209 * in case either of the above conditions is true.
1210 */
1211static int sigma_capture_mode(struct sr_dev_inst *sdi)
1212{
1213 struct dev_context *devc = sdi->priv;
1214
1215 uint64_t running_msec;
1216 struct timeval tv;
1217
1218 uint32_t stoppos, triggerpos;
1219
1220 /* Check if the selected sampling duration passed. */
1221 gettimeofday(&tv, 0);
1222 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1223 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1224 if (running_msec >= devc->limit_msec)
1225 return download_capture(sdi);
1226
1227 /* Get the position in DRAM to which the FPGA is writing now. */
1228 sigma_read_pos(&stoppos, &triggerpos, devc);
1229 /* Test if DRAM is full and if so, download the data. */
1230 if ((stoppos >> 9) == 32767)
1231 return download_capture(sdi);
1232
1233 return TRUE;
1234}
1235
1236static int receive_data(int fd, int revents, void *cb_data)
1237{
1238 struct sr_dev_inst *sdi;
1239 struct dev_context *devc;
1240
1241 (void)fd;
1242 (void)revents;
1243
1244 sdi = cb_data;
1245 devc = sdi->priv;
1246
1247 if (devc->state.state == SIGMA_IDLE)
1248 return TRUE;
1249
1250 if (devc->state.state == SIGMA_CAPTURE)
1251 return sigma_capture_mode(sdi);
1252
1253 return TRUE;
1254}
1255
1256/* Build a LUT entry used by the trigger functions. */
1257static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1258{
1259 int i, j, k, bit;
1260
1261 /* For each quad channel. */
1262 for (i = 0; i < 4; ++i) {
1263 entry[i] = 0xffff;
1264
1265 /* For each bit in LUT. */
1266 for (j = 0; j < 16; ++j)
1267
1268 /* For each channel in quad. */
1269 for (k = 0; k < 4; ++k) {
1270 bit = 1 << (i * 4 + k);
1271
1272 /* Set bit in entry */
1273 if ((mask & bit) &&
1274 ((!(value & bit)) !=
1275 (!(j & (1 << k)))))
1276 entry[i] &= ~(1 << j);
1277 }
1278 }
1279}
1280
1281/* Add a logical function to LUT mask. */
1282static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1283 int index, int neg, uint16_t *mask)
1284{
1285 int i, j;
1286 int x[2][2], tmp, a, b, aset, bset, rset;
1287
1288 memset(x, 0, 4 * sizeof(int));
1289
1290 /* Trigger detect condition. */
1291 switch (oper) {
1292 case OP_LEVEL:
1293 x[0][1] = 1;
1294 x[1][1] = 1;
1295 break;
1296 case OP_NOT:
1297 x[0][0] = 1;
1298 x[1][0] = 1;
1299 break;
1300 case OP_RISE:
1301 x[0][1] = 1;
1302 break;
1303 case OP_FALL:
1304 x[1][0] = 1;
1305 break;
1306 case OP_RISEFALL:
1307 x[0][1] = 1;
1308 x[1][0] = 1;
1309 break;
1310 case OP_NOTRISE:
1311 x[1][1] = 1;
1312 x[0][0] = 1;
1313 x[1][0] = 1;
1314 break;
1315 case OP_NOTFALL:
1316 x[1][1] = 1;
1317 x[0][0] = 1;
1318 x[0][1] = 1;
1319 break;
1320 case OP_NOTRISEFALL:
1321 x[1][1] = 1;
1322 x[0][0] = 1;
1323 break;
1324 }
1325
1326 /* Transpose if neg is set. */
1327 if (neg) {
1328 for (i = 0; i < 2; ++i) {
1329 for (j = 0; j < 2; ++j) {
1330 tmp = x[i][j];
1331 x[i][j] = x[1-i][1-j];
1332 x[1-i][1-j] = tmp;
1333 }
1334 }
1335 }
1336
1337 /* Update mask with function. */
1338 for (i = 0; i < 16; ++i) {
1339 a = (i >> (2 * index + 0)) & 1;
1340 b = (i >> (2 * index + 1)) & 1;
1341
1342 aset = (*mask >> i) & 1;
1343 bset = x[b][a];
1344
1345 if (func == FUNC_AND || func == FUNC_NAND)
1346 rset = aset & bset;
1347 else if (func == FUNC_OR || func == FUNC_NOR)
1348 rset = aset | bset;
1349 else if (func == FUNC_XOR || func == FUNC_NXOR)
1350 rset = aset ^ bset;
1351
1352 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1353 rset = !rset;
1354
1355 *mask &= ~(1 << i);
1356
1357 if (rset)
1358 *mask |= 1 << i;
1359 }
1360}
1361
1362/*
1363 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1364 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1365 * set at any time, but a full mask and value can be set (0/1).
1366 */
1367static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1368{
1369 int i,j;
1370 uint16_t masks[2] = { 0, 0 };
1371
1372 memset(lut, 0, sizeof(struct triggerlut));
1373
1374 /* Contant for simple triggers. */
1375 lut->m4 = 0xa000;
1376
1377 /* Value/mask trigger support. */
1378 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1379 lut->m2d);
1380
1381 /* Rise/fall trigger support. */
1382 for (i = 0, j = 0; i < 16; ++i) {
1383 if (devc->trigger.risingmask & (1 << i) ||
1384 devc->trigger.fallingmask & (1 << i))
1385 masks[j++] = 1 << i;
1386 }
1387
1388 build_lut_entry(masks[0], masks[0], lut->m0d);
1389 build_lut_entry(masks[1], masks[1], lut->m1d);
1390
1391 /* Add glue logic */
1392 if (masks[0] || masks[1]) {
1393 /* Transition trigger. */
1394 if (masks[0] & devc->trigger.risingmask)
1395 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1396 if (masks[0] & devc->trigger.fallingmask)
1397 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1398 if (masks[1] & devc->trigger.risingmask)
1399 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1400 if (masks[1] & devc->trigger.fallingmask)
1401 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1402 } else {
1403 /* Only value/mask trigger. */
1404 lut->m3 = 0xffff;
1405 }
1406
1407 /* Triggertype: event. */
1408 lut->params.selres = 3;
1409
1410 return SR_OK;
1411}
1412
1413static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
1414{
1415 struct dev_context *devc;
1416 struct clockselect_50 clockselect;
1417 int frac, triggerpin, ret;
1418 uint8_t triggerselect = 0;
1419 struct triggerinout triggerinout_conf;
1420 struct triggerlut lut;
1421
1422 if (sdi->status != SR_ST_ACTIVE)
1423 return SR_ERR_DEV_CLOSED;
1424
1425 devc = sdi->priv;
1426
1427 if (convert_trigger(sdi) != SR_OK) {
1428 sr_err("Failed to configure triggers.");
1429 return SR_ERR;
1430 }
1431
1432 /* If the samplerate has not been set, default to 200 kHz. */
1433 if (devc->cur_firmware == -1) {
1434 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1435 return ret;
1436 }
1437
1438 /* Enter trigger programming mode. */
1439 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1440
1441 /* 100 and 200 MHz mode. */
1442 if (devc->cur_samplerate >= SR_MHZ(100)) {
1443 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1444
1445 /* Find which pin to trigger on from mask. */
1446 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1447 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1448 (1 << triggerpin))
1449 break;
1450
1451 /* Set trigger pin and light LED on trigger. */
1452 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1453
1454 /* Default rising edge. */
1455 if (devc->trigger.fallingmask)
1456 triggerselect |= 1 << 3;
1457
1458 /* All other modes. */
1459 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1460 build_basic_trigger(&lut, devc);
1461
1462 sigma_write_trigger_lut(&lut, devc);
1463
1464 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1465 }
1466
1467 /* Setup trigger in and out pins to default values. */
1468 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1469 triggerinout_conf.trgout_bytrigger = 1;
1470 triggerinout_conf.trgout_enable = 1;
1471
1472 sigma_write_register(WRITE_TRIGGER_OPTION,
1473 (uint8_t *) &triggerinout_conf,
1474 sizeof(struct triggerinout), devc);
1475
1476 /* Go back to normal mode. */
1477 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1478
1479 /* Set clock select register. */
1480 if (devc->cur_samplerate == SR_MHZ(200))
1481 /* Enable 4 channels. */
1482 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1483 else if (devc->cur_samplerate == SR_MHZ(100))
1484 /* Enable 8 channels. */
1485 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1486 else {
1487 /*
1488 * 50 MHz mode (or fraction thereof). Any fraction down to
1489 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1490 */
1491 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1492
1493 clockselect.async = 0;
1494 clockselect.fraction = frac;
1495 clockselect.disabled_channels = 0;
1496
1497 sigma_write_register(WRITE_CLOCK_SELECT,
1498 (uint8_t *) &clockselect,
1499 sizeof(clockselect), devc);
1500 }
1501
1502 /* Setup maximum post trigger time. */
1503 sigma_set_register(WRITE_POST_TRIGGER,
1504 (devc->capture_ratio * 255) / 100, devc);
1505
1506 /* Start acqusition. */
1507 gettimeofday(&devc->start_tv, 0);
1508 sigma_set_register(WRITE_MODE, 0x0d, devc);
1509
1510 devc->cb_data = cb_data;
1511
1512 /* Send header packet to the session bus. */
1513 std_session_send_df_header(sdi, LOG_PREFIX);
1514
1515 /* Add capture source. */
1516 sr_session_source_add(sdi->session, 0, G_IO_IN, 10, receive_data, (void *)sdi);
1517
1518 devc->state.state = SIGMA_CAPTURE;
1519
1520 return SR_OK;
1521}
1522
1523static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1524{
1525 struct dev_context *devc;
1526
1527 (void)cb_data;
1528
1529 devc = sdi->priv;
1530 devc->state.state = SIGMA_IDLE;
1531
1532 sr_session_source_remove(sdi->session, 0);
1533
1534 return SR_OK;
1535}
1536
1537SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1538 .name = "asix-sigma",
1539 .longname = "ASIX SIGMA/SIGMA2",
1540 .api_version = 1,
1541 .init = init,
1542 .cleanup = cleanup,
1543 .scan = scan,
1544 .dev_list = dev_list,
1545 .dev_clear = dev_clear,
1546 .config_get = config_get,
1547 .config_set = config_set,
1548 .config_list = config_list,
1549 .dev_open = dev_open,
1550 .dev_close = dev_close,
1551 .dev_acquisition_start = dev_acquisition_start,
1552 .dev_acquisition_stop = dev_acquisition_stop,
1553 .priv = NULL,
1554};
Hardware access and backend lib