[libsigrok.git] / hardware / link-mso19 / protocol.c

/*
 * This file is part of the sigrok project.
 *
 * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
 * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
 * Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "protocol.h"

/* serial protocol */
#define mso_trans(a, v) \
	(((v) & 0x3f) | (((v) & 0xc0) << 6) | (((a) & 0xf) << 8) | \
	((~(v) & 0x20) << 1) | ((~(v) & 0x80) << 7))

static const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
static const char mso_foot[] = { 0x7e };

extern SR_PRIV struct sr_dev_driver link_mso19_driver_info;
static struct sr_dev_driver *di = &link_mso19_driver_info;

SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial,
				     uint16_t payload[], int n)
{
	int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
	char *p, *buf;

	ret = SR_ERR;

	if (serial->fd < 0)
		goto ret;

	if (!(buf = g_try_malloc(s))) {
		sr_err("Failed to malloc message buffer.");
		ret = SR_ERR_MALLOC;
		goto ret;
	}

	p = buf;
	memcpy(p, mso_head, sizeof(mso_head));
	p += sizeof(mso_head);

	for (i = 0; i < n; i++) {
		*(uint16_t *) p = g_htons(payload[i]);
		p += 2;
	}
	memcpy(p, mso_foot, sizeof(mso_foot));

	w = 0;
	while (w < s) {
		ret = serial_write(serial, buf + w, s - w);
		if (ret < 0) {
			ret = SR_ERR;
			goto free;
		}
		w += ret;
	}
	ret = SR_OK;
free:
	g_free(buf);
ret:
	return ret;
}

SR_PRIV int mso_configure_trigger(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t threshold_value = mso_calc_raw_from_mv(devc);

	threshold_value = 0x153C;
	uint8_t trigger_config = 0;

	if (devc->trigger_slope)
		trigger_config |= 0x04;	//Trigger on falling edge

	switch (devc->trigger_outsrc) {
	case 1:
		trigger_config |= 0x00;	//Trigger pulse output
		break;
	case 2:
		trigger_config |= 0x08;	//PWM DAC from the pattern generator buffer
		break;
	case 3:
		trigger_config |= 0x18;	//White noise
		break;
	}

	switch (devc->trigger_chan) {
	case 0:
		trigger_config |= 0x00;	//DSO level trigger //b00000000
		break;
	case 1:
		trigger_config |= 0x20;	//DSO level trigger & width < trigger_width
		break;
	case 2:
		trigger_config |= 0x40;	//DSO level trigger & width >= trigger_width 
		break;
	case 3:
		trigger_config |= 0x60;	//LA combination trigger
		break;
	}

	//Last bit of trigger config reg 4 needs to be 1 for trigger enable,
	//otherwise the trigger is not enabled
	if (devc->use_trigger)
		trigger_config |= 0x80;

	uint16_t ops[18];
	ops[0] = mso_trans(3, threshold_value & 0xff);
	//The trigger_config also holds the 2 MSB bits from the threshold value
	ops[1] = mso_trans(4, trigger_config | ((threshold_value >> 8) & 0x03));
	ops[2] = mso_trans(5, devc->la_trigger);
	ops[3] = mso_trans(6, devc->la_trigger_mask);
	ops[4] = mso_trans(7, devc->trigger_holdoff[0]);
	ops[5] = mso_trans(8, devc->trigger_holdoff[1]);

	ops[6] = mso_trans(11,
			   devc->dso_trigger_width /
			   SR_HZ_TO_NS(devc->cur_rate));

	/* Select the SPI/I2C trigger config bank */
	ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2)));
	/* Configure the SPI/I2C protocol trigger */
	ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
	ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
	ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
	ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
	ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
	ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
	ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
	ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
	ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
	/* Select the default config bank */
	ops[17] = mso_trans(REG_CTL2, devc->ctlbase2);

	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_configure_threshold_level(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;

	return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
}

SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
{
	uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
	struct dev_context *devc = sdi->priv;

	sr_dbg("Requesting buffer dump.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_arm(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETFSM),
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_ARM),
		mso_trans(REG_CTL1, devc->ctlbase1),
	};

	sr_dbg("Requesting trigger arm.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_CTL1, devc->ctlbase1 | 8),
		mso_trans(REG_CTL1, devc->ctlbase1),
	};

	sr_dbg("Requesting forced capture.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_dac_out(const struct sr_dev_inst *sdi, uint16_t val)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_DAC1, (val >> 8) & 0xff),
		mso_trans(REG_DAC2, val & 0xff),
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETADC),
	};

	sr_dbg("Setting dac word to 0x%x.", val);
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context * devc)
{
	return (uint16_t) (0x200 -
			   ((devc->dso_trigger_voltage / devc->dso_probe_attn) /
			    devc->vbit));
}

SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct,
			     struct dev_context *devc)
{
	unsigned int u1, u2, u3, u4, u5, u6;

	iProduct = iProduct;
	/* FIXME: This code is in the original app, but I think its
	 * used only for the GUI */
	/*    if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03"))
	   devc->num_sample_rates = 0x16;
	   else
	   devc->num_sample_rates = 0x10; */

	/* parse iSerial */
	if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
					&u1, &u2, &u3, &u4, &u5, &u6) != 6)
		return SR_ERR;
	devc->hwmodel = u4;
	devc->hwrev = u5;
	devc->vbit = u1 / 10000;
	if (devc->vbit == 0)
		devc->vbit = 4.19195;
	devc->dac_offset = u2;
	if (devc->dac_offset == 0)
		devc->dac_offset = 0x1ff;
	devc->offset_range = u3;
	if (devc->offset_range == 0)
		devc->offset_range = 0x17d;

	/*
	 * FIXME: There is more code on the original software to handle
	 * bigger iSerial strings, but as I can't test on my device
	 * I will not implement it yet
	 */

	return SR_OK;
}

SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[2];

	ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 | BIT_CTL1_RESETADC));
	ops[1] = mso_trans(REG_CTL1, devc->ctlbase1);
	devc->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4;

	sr_dbg("Requesting ADC reset.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[1];

	devc->ctlbase1 |= BIT_CTL1_RESETFSM;
	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);

	sr_dbg("Requesting ADC reset.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[1];

	devc->ctlbase1 &= ~BIT_CTL1_LED;
	if (state)
		devc->ctlbase1 |= BIT_CTL1_LED;
	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);

	sr_dbg("Requesting LED toggle.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi)
{
	struct sr_datafeed_packet packet;
	struct dev_context *devc;

	devc = sdi->priv;
	sr_source_remove(devc->serial->fd);

	/* Terminate session */
	packet.type = SR_DF_END;
	sr_session_send(sdi, &packet);
}

SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val)
{
	uint16_t ops[] = {
		mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
		mso_trans(REG_CLKRATE2, val & 0xff),
	};

	sr_dbg("Setting clkrate word to 0x%x.", val);
	return mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_configure_rate(const struct sr_dev_inst *sdi, uint32_t rate)
{
	struct dev_context *devc = sdi->priv;
	unsigned int i;
	int ret = SR_ERR;

	for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
		if (rate_map[i].rate == rate) {
			devc->ctlbase2 = rate_map[i].slowmode;
			ret = mso_clkrate_out(devc->serial, rate_map[i].val);
			if (ret == SR_OK)
				devc->cur_rate = rate;
			return ret;
		}
	}

	if (ret != SR_OK)
		sr_err("Unsupported rate.");

	return ret;
}

SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t *info)
{
	uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
	int ret;

	sr_dbg("Requesting trigger state.");
	ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
	if (info == NULL || ret != SR_OK)
		return ret;

	uint8_t buf = 0;
	if (serial_read(serial, &buf, 1) != 1)	/* FIXME: Need timeout */
		ret = SR_ERR;
	if (!info)
		*info = buf;

	sr_dbg("Trigger state is: 0x%x.", *info);
	return ret;
}

SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
{
	struct sr_datafeed_packet packet;
	struct sr_datafeed_logic logic;
	struct sr_dev_inst *sdi;
	GSList *l;
	int i;

	struct drv_context *drvc = di->priv;

	/* Find this device's devc struct by its fd. */
	struct dev_context *devc = NULL;
	for (l = drvc->instances; l; l = l->next) {
		sdi = l->data;
		devc = sdi->priv;
		if (devc->serial->fd == fd)
			break;
		devc = NULL;
	}
	if (!devc)
		/* Shouldn't happen. */
		return TRUE;

	(void)revents;

	uint8_t in[1024];
	size_t s = serial_read(devc->serial, in, sizeof(in));

	if (s <= 0)
		return FALSE;

	/* Check if we triggered, then send a command that we are ready
	 * to read the data */
	if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
		devc->trigger_state = in[0];
		if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
			mso_read_buffer(sdi);
			devc->buffer_n = 0;
		} else {
			mso_check_trigger(devc->serial, NULL);
		}
		return TRUE;
	}

	/* the hardware always dumps 1024 samples, 24bits each */
	if (devc->buffer_n < 3072) {
		memcpy(devc->buffer + devc->buffer_n, in, s);
		devc->buffer_n += s;
	}
	if (devc->buffer_n < 3072)
		return TRUE;

	/* do the conversion */
	uint8_t logic_out[1024];
	double analog_out[1024];
	for (i = 0; i < 1024; i++) {
		/* FIXME: Need to do conversion to mV */
		analog_out[i] = (devc->buffer[i * 3] & 0x3f) |
		    ((devc->buffer[i * 3 + 1] & 0xf) << 6);
		logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) |
		    ((devc->buffer[i * 3 + 2] & 0x3f) << 2);
	}

	packet.type = SR_DF_LOGIC;
	packet.payload = &logic;
	logic.length = 1024;
	logic.unitsize = 1;
	logic.data = logic_out;
	sr_session_send(cb_data, &packet);

	devc->num_samples += 1024;

	if (devc->limit_samples && devc->num_samples >= devc->limit_samples) {
		sr_info("Requested number of samples reached.");
		sdi->driver->dev_acquisition_stop(sdi, cb_data);
	}

	return TRUE;
}

SR_PRIV int mso_configure_probes(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_probe *probe;
	GSList *l;
	char *tc;

	devc = sdi->priv;

	devc->la_trigger_mask = 0xFF;	//the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored).
	devc->la_trigger = 0x00;	//The value of the LA byte that generates a trigger event (in that mode).
	devc->dso_trigger_voltage = 3;
	devc->dso_probe_attn = 1;
	devc->trigger_outsrc = 0;
	devc->trigger_chan = 3;	//LA combination trigger
	devc->use_trigger = FALSE;

	for (l = sdi->probes; l; l = l->next) {
		probe = (struct sr_probe *)l->data;
		if (probe->enabled == FALSE)
			continue;

		int probe_bit = 1 << (probe->index);
		if (!(probe->trigger))
			continue;

		devc->use_trigger = TRUE;
		//Configure trigger mask and value.
		for (tc = probe->trigger; *tc; tc++) {
			devc->la_trigger_mask &= ~probe_bit;
			if (*tc == '1')
				devc->la_trigger |= probe_bit;
		}
	}

	return SR_OK;
}
Commit	Line	Data
	1	/*
	2	* This file is part of the sigrok project.
	3	*
	4	* Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
	5	* Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
	6	* Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com>
	7	*
	8	* This program is free software: you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation, either version 3 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#include "protocol.h"
	23
	24	/* serial protocol */
	25	#define mso_trans(a, v) \
	26	(((v) & 0x3f) \| (((v) & 0xc0) << 6) \| (((a) & 0xf) << 8) \| \
	27	((~(v) & 0x20) << 1) \| ((~(v) & 0x80) << 7))
	28
	29	static const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
	30	static const char mso_foot[] = { 0x7e };
	31
	32	extern SR_PRIV struct sr_dev_driver link_mso19_driver_info;
	33	static struct sr_dev_driver *di = &link_mso19_driver_info;
	34
	35	SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial,
	36	uint16_t payload[], int n)
	37	{
	38	int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
	39	char p, buf;
	40
	41	ret = SR_ERR;
	42
	43	if (serial->fd < 0)
	44	goto ret;
	45
	46	if (!(buf = g_try_malloc(s))) {
	47	sr_err("Failed to malloc message buffer.");
	48	ret = SR_ERR_MALLOC;
	49	goto ret;
	50	}
	51
	52	p = buf;
	53	memcpy(p, mso_head, sizeof(mso_head));
	54	p += sizeof(mso_head);
	55
	56	for (i = 0; i < n; i++) {
	57	(uint16_t ) p = g_htons(payload[i]);
	58	p += 2;
	59	}
	60	memcpy(p, mso_foot, sizeof(mso_foot));
	61
	62	w = 0;
	63	while (w < s) {
	64	ret = serial_write(serial, buf + w, s - w);
	65	if (ret < 0) {
	66	ret = SR_ERR;
	67	goto free;
	68	}
	69	w += ret;
	70	}
	71	ret = SR_OK;
	72	free:
	73	g_free(buf);
	74	ret:
	75	return ret;
	76	}
	77
	78	SR_PRIV int mso_configure_trigger(const struct sr_dev_inst *sdi)
	79	{
	80	struct dev_context *devc = sdi->priv;
	81	uint16_t threshold_value = mso_calc_raw_from_mv(devc);
	82
	83	threshold_value = 0x153C;
	84	uint8_t trigger_config = 0;
	85
	86	if (devc->trigger_slope)
	87	trigger_config \|= 0x04; //Trigger on falling edge
	88
	89	switch (devc->trigger_outsrc) {
	90	case 1:
	91	trigger_config \|= 0x00; //Trigger pulse output
	92	break;
	93	case 2:
	94	trigger_config \|= 0x08; //PWM DAC from the pattern generator buffer
	95	break;
	96	case 3:
	97	trigger_config \|= 0x18; //White noise
	98	break;
	99	}
	100
	101	switch (devc->trigger_chan) {
	102	case 0:
	103	trigger_config \|= 0x00; //DSO level trigger //b00000000
	104	break;
	105	case 1:
	106	trigger_config \|= 0x20; //DSO level trigger & width < trigger_width
	107	break;
	108	case 2:
	109	trigger_config \|= 0x40; //DSO level trigger & width >= trigger_width
	110	break;
	111	case 3:
	112	trigger_config \|= 0x60; //LA combination trigger
	113	break;
	114	}
	115
	116	//Last bit of trigger config reg 4 needs to be 1 for trigger enable,
	117	//otherwise the trigger is not enabled
	118	if (devc->use_trigger)
	119	trigger_config \|= 0x80;
	120
	121	uint16_t ops[18];
	122	ops[0] = mso_trans(3, threshold_value & 0xff);
	123	//The trigger_config also holds the 2 MSB bits from the threshold value
	124	ops[1] = mso_trans(4, trigger_config \| ((threshold_value >> 8) & 0x03));
	125	ops[2] = mso_trans(5, devc->la_trigger);
	126	ops[3] = mso_trans(6, devc->la_trigger_mask);
	127	ops[4] = mso_trans(7, devc->trigger_holdoff[0]);
	128	ops[5] = mso_trans(8, devc->trigger_holdoff[1]);
	129
	130	ops[6] = mso_trans(11,
	131	devc->dso_trigger_width /
	132	SR_HZ_TO_NS(devc->cur_rate));
	133
	134	/* Select the SPI/I2C trigger config bank */
	135	ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 \| BITS_CTL2_BANK(2)));
	136	/* Configure the SPI/I2C protocol trigger */
	137	ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
	138	ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
	139	ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
	140	ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
	141	ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
	142	ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
	143	ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
	144	ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
	145	ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
	146	/* Select the default config bank */
	147	ops[17] = mso_trans(REG_CTL2, devc->ctlbase2);
	148
	149	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	150	}
	151
	152	SR_PRIV int mso_configure_threshold_level(const struct sr_dev_inst *sdi)
	153	{
	154	struct dev_context *devc = sdi->priv;
	155
	156	return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
	157	}
	158
	159	SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
	160	{
	161	uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
	162	struct dev_context *devc = sdi->priv;
	163
	164	sr_dbg("Requesting buffer dump.");
	165	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	166	}
	167
	168	SR_PRIV int mso_arm(const struct sr_dev_inst *sdi)
	169	{
	170	struct dev_context *devc = sdi->priv;
	171	uint16_t ops[] = {
	172	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_RESETFSM),
	173	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_ARM),
	174	mso_trans(REG_CTL1, devc->ctlbase1),
	175	};
	176
	177	sr_dbg("Requesting trigger arm.");
	178	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	179	}
	180
	181	SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
	182	{
	183	struct dev_context *devc = sdi->priv;
	184	uint16_t ops[] = {
	185	mso_trans(REG_CTL1, devc->ctlbase1 \| 8),
	186	mso_trans(REG_CTL1, devc->ctlbase1),
	187	};
	188
	189	sr_dbg("Requesting forced capture.");
	190	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	191	}
	192
	193	SR_PRIV int mso_dac_out(const struct sr_dev_inst *sdi, uint16_t val)
	194	{
	195	struct dev_context *devc = sdi->priv;
	196	uint16_t ops[] = {
	197	mso_trans(REG_DAC1, (val >> 8) & 0xff),
	198	mso_trans(REG_DAC2, val & 0xff),
	199	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_RESETADC),
	200	};
	201
	202	sr_dbg("Setting dac word to 0x%x.", val);
	203	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	204	}
	205
	206	SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context * devc)
	207	{
	208	return (uint16_t) (0x200 -
	209	((devc->dso_trigger_voltage / devc->dso_probe_attn) /
	210	devc->vbit));
	211	}
	212
	213	SR_PRIV int mso_parse_serial(const char iSerial, const char iProduct,
	214	struct dev_context *devc)
	215	{
	216	unsigned int u1, u2, u3, u4, u5, u6;
	217
	218	iProduct = iProduct;
	219	/* FIXME: This code is in the original app, but I think its
	220	* used only for the GUI */
	221	/* if (strstr(iProduct, "REV_02") \|\| strstr(iProduct, "REV_03"))
	222	devc->num_sample_rates = 0x16;
	223	else
	224	devc->num_sample_rates = 0x10; */
	225
	226	/* parse iSerial */
	227	if (iSerial[0] != '4' \|\| sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
	228	&u1, &u2, &u3, &u4, &u5, &u6) != 6)
	229	return SR_ERR;
	230	devc->hwmodel = u4;
	231	devc->hwrev = u5;
	232	devc->vbit = u1 / 10000;
	233	if (devc->vbit == 0)
	234	devc->vbit = 4.19195;
	235	devc->dac_offset = u2;
	236	if (devc->dac_offset == 0)
	237	devc->dac_offset = 0x1ff;
	238	devc->offset_range = u3;
	239	if (devc->offset_range == 0)
	240	devc->offset_range = 0x17d;
	241
	242	/*
	243	* FIXME: There is more code on the original software to handle
	244	* bigger iSerial strings, but as I can't test on my device
	245	* I will not implement it yet
	246	*/
	247
	248	return SR_OK;
	249	}
	250
	251	SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi)
	252	{
	253	struct dev_context *devc = sdi->priv;
	254	uint16_t ops[2];
	255
	256	ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 \| BIT_CTL1_RESETADC));
	257	ops[1] = mso_trans(REG_CTL1, devc->ctlbase1);
	258	devc->ctlbase1 \|= BIT_CTL1_ADC_UNKNOWN4;
	259
	260	sr_dbg("Requesting ADC reset.");
	261	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	262	}
	263
	264	SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi)
	265	{
	266	struct dev_context *devc = sdi->priv;
	267	uint16_t ops[1];
	268
	269	devc->ctlbase1 \|= BIT_CTL1_RESETFSM;
	270	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);
	271
	272	sr_dbg("Requesting ADC reset.");
	273	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	274	}
	275
	276	SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state)
	277	{
	278	struct dev_context *devc = sdi->priv;
	279	uint16_t ops[1];
	280
	281	devc->ctlbase1 &= ~BIT_CTL1_LED;
	282	if (state)
	283	devc->ctlbase1 \|= BIT_CTL1_LED;
	284	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);
	285
	286	sr_dbg("Requesting LED toggle.");
	287	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	288	}
	289
	290	SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi)
	291	{
	292	struct sr_datafeed_packet packet;
	293	struct dev_context *devc;
	294
	295	devc = sdi->priv;
	296	sr_source_remove(devc->serial->fd);
	297
	298	/* Terminate session */
	299	packet.type = SR_DF_END;
	300	sr_session_send(sdi, &packet);
	301	}
	302
	303	SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val)
	304	{
	305	uint16_t ops[] = {
	306	mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
	307	mso_trans(REG_CLKRATE2, val & 0xff),
	308	};
	309
	310	sr_dbg("Setting clkrate word to 0x%x.", val);
	311	return mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
	312	}
	313
	314	SR_PRIV int mso_configure_rate(const struct sr_dev_inst *sdi, uint32_t rate)
	315	{
	316	struct dev_context *devc = sdi->priv;
	317	unsigned int i;
	318	int ret = SR_ERR;
	319
	320	for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
	321	if (rate_map[i].rate == rate) {
	322	devc->ctlbase2 = rate_map[i].slowmode;
	323	ret = mso_clkrate_out(devc->serial, rate_map[i].val);
	324	if (ret == SR_OK)
	325	devc->cur_rate = rate;
	326	return ret;
	327	}
	328	}
	329
	330	if (ret != SR_OK)
	331	sr_err("Unsupported rate.");
	332
	333	return ret;
	334	}
	335
	336	SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst serial, uint8_t info)
	337	{
	338	uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
	339	int ret;
	340
	341	sr_dbg("Requesting trigger state.");
	342	ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
	343	if (info == NULL \|\| ret != SR_OK)
	344	return ret;
	345
	346	uint8_t buf = 0;
	347	if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */
	348	ret = SR_ERR;
	349	if (!info)
	350	*info = buf;
	351
	352	sr_dbg("Trigger state is: 0x%x.", *info);
	353	return ret;
	354	}
	355
	356	SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
	357	{
	358	struct sr_datafeed_packet packet;
	359	struct sr_datafeed_logic logic;
	360	struct sr_dev_inst *sdi;
	361	GSList *l;
	362	int i;
	363
	364	struct drv_context *drvc = di->priv;
	365
	366	/* Find this device's devc struct by its fd. */
	367	struct dev_context *devc = NULL;
	368	for (l = drvc->instances; l; l = l->next) {
	369	sdi = l->data;
	370	devc = sdi->priv;
	371	if (devc->serial->fd == fd)
	372	break;
	373	devc = NULL;
	374	}
	375	if (!devc)
	376	/* Shouldn't happen. */
	377	return TRUE;
	378
	379	(void)revents;
	380
	381	uint8_t in[1024];
	382	size_t s = serial_read(devc->serial, in, sizeof(in));
	383
	384	if (s <= 0)
	385	return FALSE;
	386
	387	/* Check if we triggered, then send a command that we are ready
	388	* to read the data */
	389	if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
	390	devc->trigger_state = in[0];
	391	if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
	392	mso_read_buffer(sdi);
	393	devc->buffer_n = 0;
	394	} else {
	395	mso_check_trigger(devc->serial, NULL);
	396	}
	397	return TRUE;
	398	}
	399
	400	/* the hardware always dumps 1024 samples, 24bits each */
	401	if (devc->buffer_n < 3072) {
	402	memcpy(devc->buffer + devc->buffer_n, in, s);
	403	devc->buffer_n += s;
	404	}
	405	if (devc->buffer_n < 3072)
	406	return TRUE;
	407
	408	/* do the conversion */
	409	uint8_t logic_out[1024];
	410	double analog_out[1024];
	411	for (i = 0; i < 1024; i++) {
	412	/* FIXME: Need to do conversion to mV */
	413	analog_out[i] = (devc->buffer[i * 3] & 0x3f) \|
	414	((devc->buffer[i * 3 + 1] & 0xf) << 6);
	415	logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) \|
	416	((devc->buffer[i * 3 + 2] & 0x3f) << 2);
	417	}
	418
	419	packet.type = SR_DF_LOGIC;
	420	packet.payload = &logic;
	421	logic.length = 1024;
	422	logic.unitsize = 1;
	423	logic.data = logic_out;
	424	sr_session_send(cb_data, &packet);
	425
	426	devc->num_samples += 1024;
	427
	428	if (devc->limit_samples && devc->num_samples >= devc->limit_samples) {
	429	sr_info("Requested number of samples reached.");
	430	sdi->driver->dev_acquisition_stop(sdi, cb_data);
	431	}
	432
	433	return TRUE;
	434	}
	435
	436	SR_PRIV int mso_configure_probes(const struct sr_dev_inst *sdi)
	437	{
	438	struct dev_context *devc;
	439	struct sr_probe *probe;
	440	GSList *l;
	441	char *tc;
	442
	443	devc = sdi->priv;
	444
	445	devc->la_trigger_mask = 0xFF; //the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored).
	446	devc->la_trigger = 0x00; //The value of the LA byte that generates a trigger event (in that mode).
	447	devc->dso_trigger_voltage = 3;
	448	devc->dso_probe_attn = 1;
	449	devc->trigger_outsrc = 0;
	450	devc->trigger_chan = 3; //LA combination trigger
	451	devc->use_trigger = FALSE;
	452
	453	for (l = sdi->probes; l; l = l->next) {
	454	probe = (struct sr_probe *)l->data;
	455	if (probe->enabled == FALSE)
	456	continue;
	457
	458	int probe_bit = 1 << (probe->index);
	459	if (!(probe->trigger))
	460	continue;
	461
	462	devc->use_trigger = TRUE;
	463	//Configure trigger mask and value.
	464	for (tc = probe->trigger; *tc; tc++) {
	465	devc->la_trigger_mask &= ~probe_bit;
	466	if (*tc == '1')
	467	devc->la_trigger \|= probe_bit;
	468	}
	469	}
	470
	471	return SR_OK;
	472	}