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1 | /* | |
2 | * This file is part of the sigrok project. | |
3 | * | |
4 | * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>, | |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * ASIX SIGMA Logic Analyzer Driver | |
24 | */ | |
25 | ||
26 | #include <glib.h> | |
27 | #include <glib/gstdio.h> | |
28 | #include <ftdi.h> | |
29 | #include <string.h> | |
30 | #include <zlib.h> | |
31 | #include "sigrok.h" | |
32 | #include "sigrok-internal.h" | |
33 | #include "asix-sigma.h" | |
34 | ||
35 | #define USB_VENDOR 0xa600 | |
36 | #define USB_PRODUCT 0xa000 | |
37 | #define USB_DESCRIPTION "ASIX SIGMA" | |
38 | #define USB_VENDOR_NAME "ASIX" | |
39 | #define USB_MODEL_NAME "SIGMA" | |
40 | #define USB_MODEL_VERSION "" | |
41 | #define TRIGGER_TYPES "rf10" | |
42 | #define NUM_PROBES 16 | |
43 | ||
44 | static GSList *dev_insts = NULL; | |
45 | ||
46 | static uint64_t supported_samplerates[] = { | |
47 | SR_KHZ(200), | |
48 | SR_KHZ(250), | |
49 | SR_KHZ(500), | |
50 | SR_MHZ(1), | |
51 | SR_MHZ(5), | |
52 | SR_MHZ(10), | |
53 | SR_MHZ(25), | |
54 | SR_MHZ(50), | |
55 | SR_MHZ(100), | |
56 | SR_MHZ(200), | |
57 | 0, | |
58 | }; | |
59 | ||
60 | /* | |
61 | * Probe numbers seem to go from 1-16, according to this image: | |
62 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
63 | * (the cable has two additional GND pins, and a TI and TO pin) | |
64 | */ | |
65 | static const char *probe_names[NUM_PROBES + 1] = { | |
66 | "1", | |
67 | "2", | |
68 | "3", | |
69 | "4", | |
70 | "5", | |
71 | "6", | |
72 | "7", | |
73 | "8", | |
74 | "9", | |
75 | "10", | |
76 | "11", | |
77 | "12", | |
78 | "13", | |
79 | "14", | |
80 | "15", | |
81 | "16", | |
82 | NULL, | |
83 | }; | |
84 | ||
85 | static struct sr_samplerates samplerates = { | |
86 | SR_KHZ(200), | |
87 | SR_MHZ(200), | |
88 | SR_HZ(0), | |
89 | supported_samplerates, | |
90 | }; | |
91 | ||
92 | static int hwcaps[] = { | |
93 | SR_HWCAP_LOGIC_ANALYZER, | |
94 | SR_HWCAP_SAMPLERATE, | |
95 | SR_HWCAP_CAPTURE_RATIO, | |
96 | SR_HWCAP_PROBECONFIG, | |
97 | ||
98 | SR_HWCAP_LIMIT_MSEC, | |
99 | 0, | |
100 | }; | |
101 | ||
102 | /* Force the FPGA to reboot. */ | |
103 | static uint8_t suicide[] = { | |
104 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
105 | }; | |
106 | ||
107 | /* Prepare to upload firmware (FPGA specific). */ | |
108 | static uint8_t init[] = { | |
109 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
110 | }; | |
111 | ||
112 | /* Initialize the logic analyzer mode. */ | |
113 | static uint8_t logic_mode_start[] = { | |
114 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
115 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
116 | }; | |
117 | ||
118 | static const char *firmware_files[] = { | |
119 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ | |
120 | "asix-sigma-100.fw", /* 100 MHz */ | |
121 | "asix-sigma-200.fw", /* 200 MHz */ | |
122 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ | |
123 | "asix-sigma-phasor.fw", /* Frequency counter */ | |
124 | }; | |
125 | ||
126 | static int hw_dev_acquisition_stop(int dev_index, gpointer session_data); | |
127 | ||
128 | static int sigma_read(void *buf, size_t size, struct context *ctx) | |
129 | { | |
130 | int ret; | |
131 | ||
132 | ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size); | |
133 | if (ret < 0) { | |
134 | sr_err("sigma: ftdi_read_data failed: %s", | |
135 | ftdi_get_error_string(&ctx->ftdic)); | |
136 | } | |
137 | ||
138 | return ret; | |
139 | } | |
140 | ||
141 | static int sigma_write(void *buf, size_t size, struct context *ctx) | |
142 | { | |
143 | int ret; | |
144 | ||
145 | ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size); | |
146 | if (ret < 0) { | |
147 | sr_err("sigma: ftdi_write_data failed: %s", | |
148 | ftdi_get_error_string(&ctx->ftdic)); | |
149 | } else if ((size_t) ret != size) { | |
150 | sr_err("sigma: ftdi_write_data did not complete write\n"); | |
151 | } | |
152 | ||
153 | return ret; | |
154 | } | |
155 | ||
156 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, | |
157 | struct context *ctx) | |
158 | { | |
159 | size_t i; | |
160 | uint8_t buf[len + 2]; | |
161 | int idx = 0; | |
162 | ||
163 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
164 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
165 | ||
166 | for (i = 0; i < len; ++i) { | |
167 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); | |
168 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
169 | } | |
170 | ||
171 | return sigma_write(buf, idx, ctx); | |
172 | } | |
173 | ||
174 | static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx) | |
175 | { | |
176 | return sigma_write_register(reg, &value, 1, ctx); | |
177 | } | |
178 | ||
179 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, | |
180 | struct context *ctx) | |
181 | { | |
182 | uint8_t buf[3]; | |
183 | ||
184 | buf[0] = REG_ADDR_LOW | (reg & 0xf); | |
185 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
186 | buf[2] = REG_READ_ADDR; | |
187 | ||
188 | sigma_write(buf, sizeof(buf), ctx); | |
189 | ||
190 | return sigma_read(data, len, ctx); | |
191 | } | |
192 | ||
193 | static uint8_t sigma_get_register(uint8_t reg, struct context *ctx) | |
194 | { | |
195 | uint8_t value; | |
196 | ||
197 | if (1 != sigma_read_register(reg, &value, 1, ctx)) { | |
198 | sr_err("sigma: sigma_get_register: 1 byte expected"); | |
199 | return 0; | |
200 | } | |
201 | ||
202 | return value; | |
203 | } | |
204 | ||
205 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, | |
206 | struct context *ctx) | |
207 | { | |
208 | uint8_t buf[] = { | |
209 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
210 | ||
211 | REG_READ_ADDR | NEXT_REG, | |
212 | REG_READ_ADDR | NEXT_REG, | |
213 | REG_READ_ADDR | NEXT_REG, | |
214 | REG_READ_ADDR | NEXT_REG, | |
215 | REG_READ_ADDR | NEXT_REG, | |
216 | REG_READ_ADDR | NEXT_REG, | |
217 | }; | |
218 | uint8_t result[6]; | |
219 | ||
220 | sigma_write(buf, sizeof(buf), ctx); | |
221 | ||
222 | sigma_read(result, sizeof(result), ctx); | |
223 | ||
224 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
225 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
226 | ||
227 | /* Not really sure why this must be done, but according to spec. */ | |
228 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
229 | stoppos -= 64; | |
230 | ||
231 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
232 | triggerpos -= 64; | |
233 | ||
234 | return 1; | |
235 | } | |
236 | ||
237 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, | |
238 | uint8_t *data, struct context *ctx) | |
239 | { | |
240 | size_t i; | |
241 | uint8_t buf[4096]; | |
242 | int idx = 0; | |
243 | ||
244 | /* Send the startchunk. Index start with 1. */ | |
245 | buf[0] = startchunk >> 8; | |
246 | buf[1] = startchunk & 0xff; | |
247 | sigma_write_register(WRITE_MEMROW, buf, 2, ctx); | |
248 | ||
249 | /* Read the DRAM. */ | |
250 | buf[idx++] = REG_DRAM_BLOCK; | |
251 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
252 | ||
253 | for (i = 0; i < numchunks; ++i) { | |
254 | /* Alternate bit to copy from DRAM to cache. */ | |
255 | if (i != (numchunks - 1)) | |
256 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
257 | ||
258 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
259 | ||
260 | if (i != (numchunks - 1)) | |
261 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
262 | } | |
263 | ||
264 | sigma_write(buf, idx, ctx); | |
265 | ||
266 | return sigma_read(data, numchunks * CHUNK_SIZE, ctx); | |
267 | } | |
268 | ||
269 | /* Upload trigger look-up tables to Sigma. */ | |
270 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx) | |
271 | { | |
272 | int i; | |
273 | uint8_t tmp[2]; | |
274 | uint16_t bit; | |
275 | ||
276 | /* Transpose the table and send to Sigma. */ | |
277 | for (i = 0; i < 16; ++i) { | |
278 | bit = 1 << i; | |
279 | ||
280 | tmp[0] = tmp[1] = 0; | |
281 | ||
282 | if (lut->m2d[0] & bit) | |
283 | tmp[0] |= 0x01; | |
284 | if (lut->m2d[1] & bit) | |
285 | tmp[0] |= 0x02; | |
286 | if (lut->m2d[2] & bit) | |
287 | tmp[0] |= 0x04; | |
288 | if (lut->m2d[3] & bit) | |
289 | tmp[0] |= 0x08; | |
290 | ||
291 | if (lut->m3 & bit) | |
292 | tmp[0] |= 0x10; | |
293 | if (lut->m3s & bit) | |
294 | tmp[0] |= 0x20; | |
295 | if (lut->m4 & bit) | |
296 | tmp[0] |= 0x40; | |
297 | ||
298 | if (lut->m0d[0] & bit) | |
299 | tmp[1] |= 0x01; | |
300 | if (lut->m0d[1] & bit) | |
301 | tmp[1] |= 0x02; | |
302 | if (lut->m0d[2] & bit) | |
303 | tmp[1] |= 0x04; | |
304 | if (lut->m0d[3] & bit) | |
305 | tmp[1] |= 0x08; | |
306 | ||
307 | if (lut->m1d[0] & bit) | |
308 | tmp[1] |= 0x10; | |
309 | if (lut->m1d[1] & bit) | |
310 | tmp[1] |= 0x20; | |
311 | if (lut->m1d[2] & bit) | |
312 | tmp[1] |= 0x40; | |
313 | if (lut->m1d[3] & bit) | |
314 | tmp[1] |= 0x80; | |
315 | ||
316 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), | |
317 | ctx); | |
318 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx); | |
319 | } | |
320 | ||
321 | /* Send the parameters */ | |
322 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
323 | sizeof(lut->params), ctx); | |
324 | ||
325 | return SR_OK; | |
326 | } | |
327 | ||
328 | /* Generate the bitbang stream for programming the FPGA. */ | |
329 | static int bin2bitbang(const char *filename, | |
330 | unsigned char **buf, size_t *buf_size) | |
331 | { | |
332 | FILE *f; | |
333 | long file_size; | |
334 | unsigned long offset = 0; | |
335 | unsigned char *p; | |
336 | uint8_t *compressed_buf, *firmware; | |
337 | uLongf csize, fwsize; | |
338 | const int buffer_size = 65536; | |
339 | size_t i; | |
340 | int c, ret, bit, v; | |
341 | uint32_t imm = 0x3f6df2ab; | |
342 | ||
343 | f = g_fopen(filename, "rb"); | |
344 | if (!f) { | |
345 | sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename); | |
346 | return SR_ERR; | |
347 | } | |
348 | ||
349 | if (-1 == fseek(f, 0, SEEK_END)) { | |
350 | sr_err("sigma: fseek on %s failed", filename); | |
351 | fclose(f); | |
352 | return SR_ERR; | |
353 | } | |
354 | ||
355 | file_size = ftell(f); | |
356 | ||
357 | fseek(f, 0, SEEK_SET); | |
358 | ||
359 | if (!(compressed_buf = g_try_malloc(file_size))) { | |
360 | sr_err("sigma: %s: compressed_buf malloc failed", __func__); | |
361 | fclose(f); | |
362 | return SR_ERR_MALLOC; | |
363 | } | |
364 | ||
365 | if (!(firmware = g_try_malloc(buffer_size))) { | |
366 | sr_err("sigma: %s: firmware malloc failed", __func__); | |
367 | fclose(f); | |
368 | g_free(compressed_buf); | |
369 | return SR_ERR_MALLOC; | |
370 | } | |
371 | ||
372 | csize = 0; | |
373 | while ((c = getc(f)) != EOF) { | |
374 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
375 | compressed_buf[csize++] = c ^ imm; | |
376 | } | |
377 | fclose(f); | |
378 | ||
379 | fwsize = buffer_size; | |
380 | ret = uncompress(firmware, &fwsize, compressed_buf, csize); | |
381 | if (ret < 0) { | |
382 | g_free(compressed_buf); | |
383 | g_free(firmware); | |
384 | sr_err("sigma: Could not unpack Sigma firmware. " | |
385 | "(Error %d)\n", ret); | |
386 | return SR_ERR; | |
387 | } | |
388 | ||
389 | g_free(compressed_buf); | |
390 | ||
391 | *buf_size = fwsize * 2 * 8; | |
392 | ||
393 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); | |
394 | if (!p) { | |
395 | sr_err("sigma: %s: buf/p malloc failed", __func__); | |
396 | g_free(compressed_buf); | |
397 | g_free(firmware); | |
398 | return SR_ERR_MALLOC; | |
399 | } | |
400 | ||
401 | for (i = 0; i < fwsize; ++i) { | |
402 | for (bit = 7; bit >= 0; --bit) { | |
403 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; | |
404 | p[offset++] = v | 0x01; | |
405 | p[offset++] = v; | |
406 | } | |
407 | } | |
408 | ||
409 | g_free(firmware); | |
410 | ||
411 | if (offset != *buf_size) { | |
412 | g_free(*buf); | |
413 | sr_err("sigma: Error reading firmware %s " | |
414 | "offset=%ld, file_size=%ld, buf_size=%zd\n", | |
415 | filename, offset, file_size, *buf_size); | |
416 | ||
417 | return SR_ERR; | |
418 | } | |
419 | ||
420 | return SR_OK; | |
421 | } | |
422 | ||
423 | static int hw_init(const char *devinfo) | |
424 | { | |
425 | struct sr_dev_inst *sdi; | |
426 | struct context *ctx; | |
427 | ||
428 | /* Avoid compiler warnings. */ | |
429 | (void)devinfo; | |
430 | ||
431 | if (!(ctx = g_try_malloc(sizeof(struct context)))) { | |
432 | sr_err("sigma: %s: ctx malloc failed", __func__); | |
433 | return 0; /* FIXME: Should be SR_ERR_MALLOC. */ | |
434 | } | |
435 | ||
436 | ftdi_init(&ctx->ftdic); | |
437 | ||
438 | /* Look for SIGMAs. */ | |
439 | if (ftdi_usb_open_desc(&ctx->ftdic, USB_VENDOR, USB_PRODUCT, | |
440 | USB_DESCRIPTION, NULL) < 0) | |
441 | goto free; | |
442 | ||
443 | ctx->cur_samplerate = 0; | |
444 | ctx->period_ps = 0; | |
445 | ctx->limit_msec = 0; | |
446 | ctx->cur_firmware = -1; | |
447 | ctx->num_probes = 0; | |
448 | ctx->samples_per_event = 0; | |
449 | ctx->capture_ratio = 50; | |
450 | ctx->use_triggers = 0; | |
451 | ||
452 | /* Register SIGMA device. */ | |
453 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, | |
454 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
455 | sr_err("sigma: %s: sdi was NULL", __func__); | |
456 | goto free; | |
457 | } | |
458 | ||
459 | sdi->priv = ctx; | |
460 | ||
461 | dev_insts = g_slist_append(dev_insts, sdi); | |
462 | ||
463 | /* We will open the device again when we need it. */ | |
464 | ftdi_usb_close(&ctx->ftdic); | |
465 | ||
466 | return 1; | |
467 | ||
468 | free: | |
469 | g_free(ctx); | |
470 | return 0; | |
471 | } | |
472 | ||
473 | static int upload_firmware(int firmware_idx, struct context *ctx) | |
474 | { | |
475 | int ret; | |
476 | unsigned char *buf; | |
477 | unsigned char pins; | |
478 | size_t buf_size; | |
479 | unsigned char result[32]; | |
480 | char firmware_path[128]; | |
481 | ||
482 | /* Make sure it's an ASIX SIGMA. */ | |
483 | if ((ret = ftdi_usb_open_desc(&ctx->ftdic, | |
484 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
485 | sr_err("sigma: ftdi_usb_open failed: %s", | |
486 | ftdi_get_error_string(&ctx->ftdic)); | |
487 | return 0; | |
488 | } | |
489 | ||
490 | if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { | |
491 | sr_err("sigma: ftdi_set_bitmode failed: %s", | |
492 | ftdi_get_error_string(&ctx->ftdic)); | |
493 | return 0; | |
494 | } | |
495 | ||
496 | /* Four times the speed of sigmalogan - Works well. */ | |
497 | if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) { | |
498 | sr_err("sigma: ftdi_set_baudrate failed: %s", | |
499 | ftdi_get_error_string(&ctx->ftdic)); | |
500 | return 0; | |
501 | } | |
502 | ||
503 | /* Force the FPGA to reboot. */ | |
504 | sigma_write(suicide, sizeof(suicide), ctx); | |
505 | sigma_write(suicide, sizeof(suicide), ctx); | |
506 | sigma_write(suicide, sizeof(suicide), ctx); | |
507 | sigma_write(suicide, sizeof(suicide), ctx); | |
508 | ||
509 | /* Prepare to upload firmware (FPGA specific). */ | |
510 | sigma_write(init, sizeof(init), ctx); | |
511 | ||
512 | ftdi_usb_purge_buffers(&ctx->ftdic); | |
513 | ||
514 | /* Wait until the FPGA asserts INIT_B. */ | |
515 | while (1) { | |
516 | ret = sigma_read(result, 1, ctx); | |
517 | if (result[0] & 0x20) | |
518 | break; | |
519 | } | |
520 | ||
521 | /* Prepare firmware. */ | |
522 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, | |
523 | firmware_files[firmware_idx]); | |
524 | ||
525 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { | |
526 | sr_err("sigma: An error occured while reading the firmware: %s", | |
527 | firmware_path); | |
528 | return ret; | |
529 | } | |
530 | ||
531 | /* Upload firmare. */ | |
532 | sigma_write(buf, buf_size, ctx); | |
533 | ||
534 | g_free(buf); | |
535 | ||
536 | if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) { | |
537 | sr_err("sigma: ftdi_set_bitmode failed: %s", | |
538 | ftdi_get_error_string(&ctx->ftdic)); | |
539 | return SR_ERR; | |
540 | } | |
541 | ||
542 | ftdi_usb_purge_buffers(&ctx->ftdic); | |
543 | ||
544 | /* Discard garbage. */ | |
545 | while (1 == sigma_read(&pins, 1, ctx)) | |
546 | ; | |
547 | ||
548 | /* Initialize the logic analyzer mode. */ | |
549 | sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx); | |
550 | ||
551 | /* Expect a 3 byte reply. */ | |
552 | ret = sigma_read(result, 3, ctx); | |
553 | if (ret != 3 || | |
554 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
555 | sr_err("sigma: Configuration failed. Invalid reply received."); | |
556 | return SR_ERR; | |
557 | } | |
558 | ||
559 | ctx->cur_firmware = firmware_idx; | |
560 | ||
561 | return SR_OK; | |
562 | } | |
563 | ||
564 | static int hw_dev_open(int dev_index) | |
565 | { | |
566 | struct sr_dev_inst *sdi; | |
567 | struct context *ctx; | |
568 | int ret; | |
569 | ||
570 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) | |
571 | return SR_ERR; | |
572 | ||
573 | ctx = sdi->priv; | |
574 | ||
575 | /* Make sure it's an ASIX SIGMA. */ | |
576 | if ((ret = ftdi_usb_open_desc(&ctx->ftdic, | |
577 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
578 | ||
579 | sr_err("sigma: ftdi_usb_open failed: %s", | |
580 | ftdi_get_error_string(&ctx->ftdic)); | |
581 | ||
582 | return 0; | |
583 | } | |
584 | ||
585 | sdi->status = SR_ST_ACTIVE; | |
586 | ||
587 | return SR_OK; | |
588 | } | |
589 | ||
590 | static int set_samplerate(struct sr_dev_inst *sdi, uint64_t samplerate) | |
591 | { | |
592 | int i, ret; | |
593 | struct context *ctx = sdi->priv; | |
594 | ||
595 | for (i = 0; supported_samplerates[i]; i++) { | |
596 | if (supported_samplerates[i] == samplerate) | |
597 | break; | |
598 | } | |
599 | if (supported_samplerates[i] == 0) | |
600 | return SR_ERR_SAMPLERATE; | |
601 | ||
602 | if (samplerate <= SR_MHZ(50)) { | |
603 | ret = upload_firmware(0, ctx); | |
604 | ctx->num_probes = 16; | |
605 | } | |
606 | if (samplerate == SR_MHZ(100)) { | |
607 | ret = upload_firmware(1, ctx); | |
608 | ctx->num_probes = 8; | |
609 | } | |
610 | else if (samplerate == SR_MHZ(200)) { | |
611 | ret = upload_firmware(2, ctx); | |
612 | ctx->num_probes = 4; | |
613 | } | |
614 | ||
615 | ctx->cur_samplerate = samplerate; | |
616 | ctx->period_ps = 1000000000000 / samplerate; | |
617 | ctx->samples_per_event = 16 / ctx->num_probes; | |
618 | ctx->state.state = SIGMA_IDLE; | |
619 | ||
620 | sr_info("sigma: Firmware uploaded"); | |
621 | ||
622 | return ret; | |
623 | } | |
624 | ||
625 | /* | |
626 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
627 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
628 | * in addition to value/mask trigger for any number of probes. | |
629 | * | |
630 | * The Sigma supports complex triggers using boolean expressions, but this | |
631 | * has not been implemented yet. | |
632 | */ | |
633 | static int configure_probes(struct sr_dev_inst *sdi, GSList *probes) | |
634 | { | |
635 | struct context *ctx = sdi->priv; | |
636 | struct sr_probe *probe; | |
637 | GSList *l; | |
638 | int trigger_set = 0; | |
639 | int probebit; | |
640 | ||
641 | memset(&ctx->trigger, 0, sizeof(struct sigma_trigger)); | |
642 | ||
643 | for (l = probes; l; l = l->next) { | |
644 | probe = (struct sr_probe *)l->data; | |
645 | probebit = 1 << (probe->index - 1); | |
646 | ||
647 | if (!probe->enabled || !probe->trigger) | |
648 | continue; | |
649 | ||
650 | if (ctx->cur_samplerate >= SR_MHZ(100)) { | |
651 | /* Fast trigger support. */ | |
652 | if (trigger_set) { | |
653 | sr_err("sigma: ASIX SIGMA only supports a single " | |
654 | "pin trigger in 100 and 200MHz mode."); | |
655 | return SR_ERR; | |
656 | } | |
657 | if (probe->trigger[0] == 'f') | |
658 | ctx->trigger.fallingmask |= probebit; | |
659 | else if (probe->trigger[0] == 'r') | |
660 | ctx->trigger.risingmask |= probebit; | |
661 | else { | |
662 | sr_err("sigma: ASIX SIGMA only supports " | |
663 | "rising/falling trigger in 100 " | |
664 | "and 200MHz mode."); | |
665 | return SR_ERR; | |
666 | } | |
667 | ||
668 | ++trigger_set; | |
669 | } else { | |
670 | /* Simple trigger support (event). */ | |
671 | if (probe->trigger[0] == '1') { | |
672 | ctx->trigger.simplevalue |= probebit; | |
673 | ctx->trigger.simplemask |= probebit; | |
674 | } | |
675 | else if (probe->trigger[0] == '0') { | |
676 | ctx->trigger.simplevalue &= ~probebit; | |
677 | ctx->trigger.simplemask |= probebit; | |
678 | } | |
679 | else if (probe->trigger[0] == 'f') { | |
680 | ctx->trigger.fallingmask |= probebit; | |
681 | ++trigger_set; | |
682 | } | |
683 | else if (probe->trigger[0] == 'r') { | |
684 | ctx->trigger.risingmask |= probebit; | |
685 | ++trigger_set; | |
686 | } | |
687 | ||
688 | /* | |
689 | * Actually, Sigma supports 2 rising/falling triggers, | |
690 | * but they are ORed and the current trigger syntax | |
691 | * does not permit ORed triggers. | |
692 | */ | |
693 | if (trigger_set > 1) { | |
694 | sr_err("sigma: ASIX SIGMA only supports 1 " | |
695 | "rising/falling triggers."); | |
696 | return SR_ERR; | |
697 | } | |
698 | } | |
699 | ||
700 | if (trigger_set) | |
701 | ctx->use_triggers = 1; | |
702 | } | |
703 | ||
704 | return SR_OK; | |
705 | } | |
706 | ||
707 | static int hw_dev_close(int dev_index) | |
708 | { | |
709 | struct sr_dev_inst *sdi; | |
710 | struct context *ctx; | |
711 | ||
712 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { | |
713 | sr_err("sigma: %s: sdi was NULL", __func__); | |
714 | return SR_ERR; /* TODO: SR_ERR_ARG? */ | |
715 | } | |
716 | ||
717 | if (!(ctx = sdi->priv)) { | |
718 | sr_err("sigma: %s: sdi->priv was NULL", __func__); | |
719 | return SR_ERR; /* TODO: SR_ERR_ARG? */ | |
720 | } | |
721 | ||
722 | /* TODO */ | |
723 | if (sdi->status == SR_ST_ACTIVE) | |
724 | ftdi_usb_close(&ctx->ftdic); | |
725 | ||
726 | sdi->status = SR_ST_INACTIVE; | |
727 | ||
728 | return SR_OK; | |
729 | } | |
730 | ||
731 | static int hw_cleanup(void) | |
732 | { | |
733 | GSList *l; | |
734 | struct sr_dev_inst *sdi; | |
735 | int ret = SR_OK; | |
736 | ||
737 | /* Properly close all devices. */ | |
738 | for (l = dev_insts; l; l = l->next) { | |
739 | if (!(sdi = l->data)) { | |
740 | /* Log error, but continue cleaning up the rest. */ | |
741 | sr_err("sigma: %s: sdi was NULL, continuing", __func__); | |
742 | ret = SR_ERR_BUG; | |
743 | continue; | |
744 | } | |
745 | sr_dev_inst_free(sdi); | |
746 | } | |
747 | g_slist_free(dev_insts); | |
748 | dev_insts = NULL; | |
749 | ||
750 | return ret; | |
751 | } | |
752 | ||
753 | static void *hw_dev_info_get(int dev_index, int dev_info_id) | |
754 | { | |
755 | struct sr_dev_inst *sdi; | |
756 | struct context *ctx; | |
757 | void *info = NULL; | |
758 | ||
759 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { | |
760 | sr_err("sigma: %s: sdi was NULL", __func__); | |
761 | return NULL; | |
762 | } | |
763 | ||
764 | ctx = sdi->priv; | |
765 | ||
766 | switch (dev_info_id) { | |
767 | case SR_DI_INST: | |
768 | info = sdi; | |
769 | break; | |
770 | case SR_DI_NUM_PROBES: | |
771 | info = GINT_TO_POINTER(NUM_PROBES); | |
772 | break; | |
773 | case SR_DI_PROBE_NAMES: | |
774 | info = probe_names; | |
775 | break; | |
776 | case SR_DI_SAMPLERATES: | |
777 | info = &samplerates; | |
778 | break; | |
779 | case SR_DI_TRIGGER_TYPES: | |
780 | info = (char *)TRIGGER_TYPES; | |
781 | break; | |
782 | case SR_DI_CUR_SAMPLERATE: | |
783 | info = &ctx->cur_samplerate; | |
784 | break; | |
785 | } | |
786 | ||
787 | return info; | |
788 | } | |
789 | ||
790 | static int hw_dev_status_get(int dev_index) | |
791 | { | |
792 | struct sr_dev_inst *sdi; | |
793 | ||
794 | sdi = sr_dev_inst_get(dev_insts, dev_index); | |
795 | if (sdi) | |
796 | return sdi->status; | |
797 | else | |
798 | return SR_ST_NOT_FOUND; | |
799 | } | |
800 | ||
801 | static int *hw_hwcap_get_all(void) | |
802 | { | |
803 | return hwcaps; | |
804 | } | |
805 | ||
806 | static int hw_dev_config_set(int dev_index, int hwcap, void *value) | |
807 | { | |
808 | struct sr_dev_inst *sdi; | |
809 | struct context *ctx; | |
810 | int ret; | |
811 | ||
812 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) | |
813 | return SR_ERR; | |
814 | ||
815 | ctx = sdi->priv; | |
816 | ||
817 | if (hwcap == SR_HWCAP_SAMPLERATE) { | |
818 | ret = set_samplerate(sdi, *(uint64_t *)value); | |
819 | } else if (hwcap == SR_HWCAP_PROBECONFIG) { | |
820 | ret = configure_probes(sdi, value); | |
821 | } else if (hwcap == SR_HWCAP_LIMIT_MSEC) { | |
822 | ctx->limit_msec = *(uint64_t *)value; | |
823 | if (ctx->limit_msec > 0) | |
824 | ret = SR_OK; | |
825 | else | |
826 | ret = SR_ERR; | |
827 | } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) { | |
828 | ctx->capture_ratio = *(uint64_t *)value; | |
829 | if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100) | |
830 | ret = SR_ERR; | |
831 | else | |
832 | ret = SR_OK; | |
833 | } else { | |
834 | ret = SR_ERR; | |
835 | } | |
836 | ||
837 | return ret; | |
838 | } | |
839 | ||
840 | /* Software trigger to determine exact trigger position. */ | |
841 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
842 | struct sigma_trigger *t) | |
843 | { | |
844 | int i; | |
845 | ||
846 | for (i = 0; i < 8; ++i) { | |
847 | if (i > 0) | |
848 | last_sample = samples[i-1]; | |
849 | ||
850 | /* Simple triggers. */ | |
851 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
852 | continue; | |
853 | ||
854 | /* Rising edge. */ | |
855 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
856 | t->risingmask) != t->risingmask) | |
857 | continue; | |
858 | ||
859 | /* Falling edge. */ | |
860 | if ((last_sample & t->fallingmask) != t->fallingmask || | |
861 | (samples[i] & t->fallingmask) != 0) | |
862 | continue; | |
863 | ||
864 | break; | |
865 | } | |
866 | ||
867 | /* If we did not match, return original trigger pos. */ | |
868 | return i & 0x7; | |
869 | } | |
870 | ||
871 | /* | |
872 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. | |
873 | * Each event is 20ns apart, and can contain multiple samples. | |
874 | * | |
875 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
876 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
877 | * For 50 MHz and below, events contain one sample for each channel, | |
878 | * spread 20 ns apart. | |
879 | */ | |
880 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
881 | uint16_t *lastsample, int triggerpos, | |
882 | uint16_t limit_chunk, void *session_data) | |
883 | { | |
884 | struct sr_dev_inst *sdi = session_data; | |
885 | struct context *ctx = sdi->priv; | |
886 | uint16_t tsdiff, ts; | |
887 | uint16_t samples[65536 * ctx->samples_per_event]; | |
888 | struct sr_datafeed_packet packet; | |
889 | struct sr_datafeed_logic logic; | |
890 | int i, j, k, l, numpad, tosend; | |
891 | size_t n = 0, sent = 0; | |
892 | int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event; | |
893 | uint16_t *event; | |
894 | uint16_t cur_sample; | |
895 | int triggerts = -1; | |
896 | ||
897 | /* Check if trigger is in this chunk. */ | |
898 | if (triggerpos != -1) { | |
899 | if (ctx->cur_samplerate <= SR_MHZ(50)) | |
900 | triggerpos -= EVENTS_PER_CLUSTER - 1; | |
901 | ||
902 | if (triggerpos < 0) | |
903 | triggerpos = 0; | |
904 | ||
905 | /* Find in which cluster the trigger occured. */ | |
906 | triggerts = triggerpos / 7; | |
907 | } | |
908 | ||
909 | /* For each ts. */ | |
910 | for (i = 0; i < 64; ++i) { | |
911 | ts = *(uint16_t *) &buf[i * 16]; | |
912 | tsdiff = ts - *lastts; | |
913 | *lastts = ts; | |
914 | ||
915 | /* Decode partial chunk. */ | |
916 | if (limit_chunk && ts > limit_chunk) | |
917 | return SR_OK; | |
918 | ||
919 | /* Pad last sample up to current point. */ | |
920 | numpad = tsdiff * ctx->samples_per_event - clustersize; | |
921 | if (numpad > 0) { | |
922 | for (j = 0; j < numpad; ++j) | |
923 | samples[j] = *lastsample; | |
924 | ||
925 | n = numpad; | |
926 | } | |
927 | ||
928 | /* Send samples between previous and this timestamp to sigrok. */ | |
929 | sent = 0; | |
930 | while (sent < n) { | |
931 | tosend = MIN(2048, n - sent); | |
932 | ||
933 | packet.type = SR_DF_LOGIC; | |
934 | packet.payload = &logic; | |
935 | logic.length = tosend * sizeof(uint16_t); | |
936 | logic.unitsize = 2; | |
937 | logic.data = samples + sent; | |
938 | sr_session_bus(ctx->session_id, &packet); | |
939 | ||
940 | sent += tosend; | |
941 | } | |
942 | n = 0; | |
943 | ||
944 | event = (uint16_t *) &buf[i * 16 + 2]; | |
945 | cur_sample = 0; | |
946 | ||
947 | /* For each event in cluster. */ | |
948 | for (j = 0; j < 7; ++j) { | |
949 | ||
950 | /* For each sample in event. */ | |
951 | for (k = 0; k < ctx->samples_per_event; ++k) { | |
952 | cur_sample = 0; | |
953 | ||
954 | /* For each probe. */ | |
955 | for (l = 0; l < ctx->num_probes; ++l) | |
956 | cur_sample |= (!!(event[j] & (1 << (l * | |
957 | ctx->samples_per_event + k)))) << l; | |
958 | ||
959 | samples[n++] = cur_sample; | |
960 | } | |
961 | } | |
962 | ||
963 | /* Send data up to trigger point (if triggered). */ | |
964 | sent = 0; | |
965 | if (i == triggerts) { | |
966 | /* | |
967 | * Trigger is not always accurate to sample because of | |
968 | * pipeline delay. However, it always triggers before | |
969 | * the actual event. We therefore look at the next | |
970 | * samples to pinpoint the exact position of the trigger. | |
971 | */ | |
972 | tosend = get_trigger_offset(samples, *lastsample, | |
973 | &ctx->trigger); | |
974 | ||
975 | if (tosend > 0) { | |
976 | packet.type = SR_DF_LOGIC; | |
977 | packet.payload = &logic; | |
978 | logic.length = tosend * sizeof(uint16_t); | |
979 | logic.unitsize = 2; | |
980 | logic.data = samples; | |
981 | sr_session_bus(ctx->session_id, &packet); | |
982 | ||
983 | sent += tosend; | |
984 | } | |
985 | ||
986 | /* Only send trigger if explicitly enabled. */ | |
987 | if (ctx->use_triggers) { | |
988 | packet.type = SR_DF_TRIGGER; | |
989 | sr_session_bus(ctx->session_id, &packet); | |
990 | } | |
991 | } | |
992 | ||
993 | /* Send rest of the chunk to sigrok. */ | |
994 | tosend = n - sent; | |
995 | ||
996 | if (tosend > 0) { | |
997 | packet.type = SR_DF_LOGIC; | |
998 | packet.payload = &logic; | |
999 | logic.length = tosend * sizeof(uint16_t); | |
1000 | logic.unitsize = 2; | |
1001 | logic.data = samples + sent; | |
1002 | sr_session_bus(ctx->session_id, &packet); | |
1003 | } | |
1004 | ||
1005 | *lastsample = samples[n - 1]; | |
1006 | } | |
1007 | ||
1008 | return SR_OK; | |
1009 | } | |
1010 | ||
1011 | static int receive_data(int fd, int revents, void *session_data) | |
1012 | { | |
1013 | struct sr_dev_inst *sdi = session_data; | |
1014 | struct context *ctx = sdi->priv; | |
1015 | struct sr_datafeed_packet packet; | |
1016 | const int chunks_per_read = 32; | |
1017 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
1018 | int bufsz, numchunks, i, newchunks; | |
1019 | uint64_t running_msec; | |
1020 | struct timeval tv; | |
1021 | ||
1022 | /* Avoid compiler warnings. */ | |
1023 | (void)fd; | |
1024 | (void)revents; | |
1025 | ||
1026 | numchunks = (ctx->state.stoppos + 511) / 512; | |
1027 | ||
1028 | if (ctx->state.state == SIGMA_IDLE) | |
1029 | return FALSE; | |
1030 | ||
1031 | if (ctx->state.state == SIGMA_CAPTURE) { | |
1032 | /* Check if the timer has expired, or memory is full. */ | |
1033 | gettimeofday(&tv, 0); | |
1034 | running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 + | |
1035 | (tv.tv_usec - ctx->start_tv.tv_usec) / 1000; | |
1036 | ||
1037 | if (running_msec < ctx->limit_msec && numchunks < 32767) | |
1038 | return FALSE; | |
1039 | ||
1040 | hw_dev_acquisition_stop(sdi->index, session_data); | |
1041 | ||
1042 | return FALSE; | |
1043 | } else if (ctx->state.state == SIGMA_DOWNLOAD) { | |
1044 | if (ctx->state.chunks_downloaded >= numchunks) { | |
1045 | /* End of samples. */ | |
1046 | packet.type = SR_DF_END; | |
1047 | sr_session_bus(ctx->session_id, &packet); | |
1048 | ||
1049 | ctx->state.state = SIGMA_IDLE; | |
1050 | ||
1051 | return TRUE; | |
1052 | } | |
1053 | ||
1054 | newchunks = MIN(chunks_per_read, | |
1055 | numchunks - ctx->state.chunks_downloaded); | |
1056 | ||
1057 | sr_info("sigma: Downloading sample data: %.0f %%", | |
1058 | 100.0 * ctx->state.chunks_downloaded / numchunks); | |
1059 | ||
1060 | bufsz = sigma_read_dram(ctx->state.chunks_downloaded, | |
1061 | newchunks, buf, ctx); | |
1062 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ | |
1063 | (void)bufsz; | |
1064 | ||
1065 | /* Find first ts. */ | |
1066 | if (ctx->state.chunks_downloaded == 0) { | |
1067 | ctx->state.lastts = *(uint16_t *) buf - 1; | |
1068 | ctx->state.lastsample = 0; | |
1069 | } | |
1070 | ||
1071 | /* Decode chunks and send them to sigrok. */ | |
1072 | for (i = 0; i < newchunks; ++i) { | |
1073 | int limit_chunk = 0; | |
1074 | ||
1075 | /* The last chunk may potentially be only in part. */ | |
1076 | if (ctx->state.chunks_downloaded == numchunks - 1) { | |
1077 | /* Find the last valid timestamp */ | |
1078 | limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts; | |
1079 | } | |
1080 | ||
1081 | if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk) | |
1082 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1083 | &ctx->state.lastts, | |
1084 | &ctx->state.lastsample, | |
1085 | ctx->state.triggerpos & 0x1ff, | |
1086 | limit_chunk, session_data); | |
1087 | else | |
1088 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1089 | &ctx->state.lastts, | |
1090 | &ctx->state.lastsample, | |
1091 | -1, limit_chunk, session_data); | |
1092 | ||
1093 | ++ctx->state.chunks_downloaded; | |
1094 | } | |
1095 | } | |
1096 | ||
1097 | return TRUE; | |
1098 | } | |
1099 | ||
1100 | /* Build a LUT entry used by the trigger functions. */ | |
1101 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
1102 | { | |
1103 | int i, j, k, bit; | |
1104 | ||
1105 | /* For each quad probe. */ | |
1106 | for (i = 0; i < 4; ++i) { | |
1107 | entry[i] = 0xffff; | |
1108 | ||
1109 | /* For each bit in LUT. */ | |
1110 | for (j = 0; j < 16; ++j) | |
1111 | ||
1112 | /* For each probe in quad. */ | |
1113 | for (k = 0; k < 4; ++k) { | |
1114 | bit = 1 << (i * 4 + k); | |
1115 | ||
1116 | /* Set bit in entry */ | |
1117 | if ((mask & bit) && | |
1118 | ((!(value & bit)) != | |
1119 | (!(j & (1 << k))))) | |
1120 | entry[i] &= ~(1 << j); | |
1121 | } | |
1122 | } | |
1123 | } | |
1124 | ||
1125 | /* Add a logical function to LUT mask. */ | |
1126 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1127 | int index, int neg, uint16_t *mask) | |
1128 | { | |
1129 | int i, j; | |
1130 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1131 | ||
1132 | memset(x, 0, 4 * sizeof(int)); | |
1133 | ||
1134 | /* Trigger detect condition. */ | |
1135 | switch (oper) { | |
1136 | case OP_LEVEL: | |
1137 | x[0][1] = 1; | |
1138 | x[1][1] = 1; | |
1139 | break; | |
1140 | case OP_NOT: | |
1141 | x[0][0] = 1; | |
1142 | x[1][0] = 1; | |
1143 | break; | |
1144 | case OP_RISE: | |
1145 | x[0][1] = 1; | |
1146 | break; | |
1147 | case OP_FALL: | |
1148 | x[1][0] = 1; | |
1149 | break; | |
1150 | case OP_RISEFALL: | |
1151 | x[0][1] = 1; | |
1152 | x[1][0] = 1; | |
1153 | break; | |
1154 | case OP_NOTRISE: | |
1155 | x[1][1] = 1; | |
1156 | x[0][0] = 1; | |
1157 | x[1][0] = 1; | |
1158 | break; | |
1159 | case OP_NOTFALL: | |
1160 | x[1][1] = 1; | |
1161 | x[0][0] = 1; | |
1162 | x[0][1] = 1; | |
1163 | break; | |
1164 | case OP_NOTRISEFALL: | |
1165 | x[1][1] = 1; | |
1166 | x[0][0] = 1; | |
1167 | break; | |
1168 | } | |
1169 | ||
1170 | /* Transpose if neg is set. */ | |
1171 | if (neg) { | |
1172 | for (i = 0; i < 2; ++i) { | |
1173 | for (j = 0; j < 2; ++j) { | |
1174 | tmp = x[i][j]; | |
1175 | x[i][j] = x[1-i][1-j]; | |
1176 | x[1-i][1-j] = tmp; | |
1177 | } | |
1178 | } | |
1179 | } | |
1180 | ||
1181 | /* Update mask with function. */ | |
1182 | for (i = 0; i < 16; ++i) { | |
1183 | a = (i >> (2 * index + 0)) & 1; | |
1184 | b = (i >> (2 * index + 1)) & 1; | |
1185 | ||
1186 | aset = (*mask >> i) & 1; | |
1187 | bset = x[b][a]; | |
1188 | ||
1189 | if (func == FUNC_AND || func == FUNC_NAND) | |
1190 | rset = aset & bset; | |
1191 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1192 | rset = aset | bset; | |
1193 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1194 | rset = aset ^ bset; | |
1195 | ||
1196 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1197 | rset = !rset; | |
1198 | ||
1199 | *mask &= ~(1 << i); | |
1200 | ||
1201 | if (rset) | |
1202 | *mask |= 1 << i; | |
1203 | } | |
1204 | } | |
1205 | ||
1206 | /* | |
1207 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1208 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1209 | * set at any time, but a full mask and value can be set (0/1). | |
1210 | */ | |
1211 | static int build_basic_trigger(struct triggerlut *lut, struct context *ctx) | |
1212 | { | |
1213 | int i,j; | |
1214 | uint16_t masks[2] = { 0, 0 }; | |
1215 | ||
1216 | memset(lut, 0, sizeof(struct triggerlut)); | |
1217 | ||
1218 | /* Contant for simple triggers. */ | |
1219 | lut->m4 = 0xa000; | |
1220 | ||
1221 | /* Value/mask trigger support. */ | |
1222 | build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask, | |
1223 | lut->m2d); | |
1224 | ||
1225 | /* Rise/fall trigger support. */ | |
1226 | for (i = 0, j = 0; i < 16; ++i) { | |
1227 | if (ctx->trigger.risingmask & (1 << i) || | |
1228 | ctx->trigger.fallingmask & (1 << i)) | |
1229 | masks[j++] = 1 << i; | |
1230 | } | |
1231 | ||
1232 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1233 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1234 | ||
1235 | /* Add glue logic */ | |
1236 | if (masks[0] || masks[1]) { | |
1237 | /* Transition trigger. */ | |
1238 | if (masks[0] & ctx->trigger.risingmask) | |
1239 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); | |
1240 | if (masks[0] & ctx->trigger.fallingmask) | |
1241 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); | |
1242 | if (masks[1] & ctx->trigger.risingmask) | |
1243 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); | |
1244 | if (masks[1] & ctx->trigger.fallingmask) | |
1245 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); | |
1246 | } else { | |
1247 | /* Only value/mask trigger. */ | |
1248 | lut->m3 = 0xffff; | |
1249 | } | |
1250 | ||
1251 | /* Triggertype: event. */ | |
1252 | lut->params.selres = 3; | |
1253 | ||
1254 | return SR_OK; | |
1255 | } | |
1256 | ||
1257 | static int hw_dev_acquisition_start(int dev_index, gpointer session_data) | |
1258 | { | |
1259 | struct sr_dev_inst *sdi; | |
1260 | struct context *ctx; | |
1261 | struct sr_datafeed_packet packet; | |
1262 | struct sr_datafeed_header header; | |
1263 | struct clockselect_50 clockselect; | |
1264 | int frac, triggerpin, ret; | |
1265 | uint8_t triggerselect; | |
1266 | struct triggerinout triggerinout_conf; | |
1267 | struct triggerlut lut; | |
1268 | ||
1269 | /* Avoid compiler warnings. */ | |
1270 | (void)session_data; | |
1271 | ||
1272 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) | |
1273 | return SR_ERR; | |
1274 | ||
1275 | ctx = sdi->priv; | |
1276 | ||
1277 | /* If the samplerate has not been set, default to 200 kHz. */ | |
1278 | if (ctx->cur_firmware == -1) { | |
1279 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) | |
1280 | return ret; | |
1281 | } | |
1282 | ||
1283 | /* Enter trigger programming mode. */ | |
1284 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx); | |
1285 | ||
1286 | /* 100 and 200 MHz mode. */ | |
1287 | if (ctx->cur_samplerate >= SR_MHZ(100)) { | |
1288 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx); | |
1289 | ||
1290 | /* Find which pin to trigger on from mask. */ | |
1291 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
1292 | if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) & | |
1293 | (1 << triggerpin)) | |
1294 | break; | |
1295 | ||
1296 | /* Set trigger pin and light LED on trigger. */ | |
1297 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1298 | ||
1299 | /* Default rising edge. */ | |
1300 | if (ctx->trigger.fallingmask) | |
1301 | triggerselect |= 1 << 3; | |
1302 | ||
1303 | /* All other modes. */ | |
1304 | } else if (ctx->cur_samplerate <= SR_MHZ(50)) { | |
1305 | build_basic_trigger(&lut, ctx); | |
1306 | ||
1307 | sigma_write_trigger_lut(&lut, ctx); | |
1308 | ||
1309 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1310 | } | |
1311 | ||
1312 | /* Setup trigger in and out pins to default values. */ | |
1313 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); | |
1314 | triggerinout_conf.trgout_bytrigger = 1; | |
1315 | triggerinout_conf.trgout_enable = 1; | |
1316 | ||
1317 | sigma_write_register(WRITE_TRIGGER_OPTION, | |
1318 | (uint8_t *) &triggerinout_conf, | |
1319 | sizeof(struct triggerinout), ctx); | |
1320 | ||
1321 | /* Go back to normal mode. */ | |
1322 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx); | |
1323 | ||
1324 | /* Set clock select register. */ | |
1325 | if (ctx->cur_samplerate == SR_MHZ(200)) | |
1326 | /* Enable 4 probes. */ | |
1327 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx); | |
1328 | else if (ctx->cur_samplerate == SR_MHZ(100)) | |
1329 | /* Enable 8 probes. */ | |
1330 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx); | |
1331 | else { | |
1332 | /* | |
1333 | * 50 MHz mode (or fraction thereof). Any fraction down to | |
1334 | * 50 MHz / 256 can be used, but is not supported by sigrok API. | |
1335 | */ | |
1336 | frac = SR_MHZ(50) / ctx->cur_samplerate - 1; | |
1337 | ||
1338 | clockselect.async = 0; | |
1339 | clockselect.fraction = frac; | |
1340 | clockselect.disabled_probes = 0; | |
1341 | ||
1342 | sigma_write_register(WRITE_CLOCK_SELECT, | |
1343 | (uint8_t *) &clockselect, | |
1344 | sizeof(clockselect), ctx); | |
1345 | } | |
1346 | ||
1347 | /* Setup maximum post trigger time. */ | |
1348 | sigma_set_register(WRITE_POST_TRIGGER, | |
1349 | (ctx->capture_ratio * 255) / 100, ctx); | |
1350 | ||
1351 | /* Start acqusition. */ | |
1352 | gettimeofday(&ctx->start_tv, 0); | |
1353 | sigma_set_register(WRITE_MODE, 0x0d, ctx); | |
1354 | ||
1355 | ctx->session_id = session_data; | |
1356 | ||
1357 | /* Send header packet to the session bus. */ | |
1358 | packet.type = SR_DF_HEADER; | |
1359 | packet.payload = &header; | |
1360 | header.feed_version = 1; | |
1361 | gettimeofday(&header.starttime, NULL); | |
1362 | header.samplerate = ctx->cur_samplerate; | |
1363 | header.num_logic_probes = ctx->num_probes; | |
1364 | sr_session_bus(session_data, &packet); | |
1365 | ||
1366 | /* Add capture source. */ | |
1367 | sr_source_add(0, G_IO_IN, 10, receive_data, sdi); | |
1368 | ||
1369 | ctx->state.state = SIGMA_CAPTURE; | |
1370 | ||
1371 | return SR_OK; | |
1372 | } | |
1373 | ||
1374 | static int hw_dev_acquisition_stop(int dev_index, gpointer session_data) | |
1375 | { | |
1376 | struct sr_dev_inst *sdi; | |
1377 | struct context *ctx; | |
1378 | uint8_t modestatus; | |
1379 | ||
1380 | /* Avoid compiler warnings. */ | |
1381 | (void)session_data; | |
1382 | ||
1383 | if (!(sdi = sr_dev_inst_get(dev_insts, dev_index))) { | |
1384 | sr_err("sigma: %s: sdi was NULL", __func__); | |
1385 | return SR_ERR_BUG; | |
1386 | } | |
1387 | ||
1388 | if (!(ctx = sdi->priv)) { | |
1389 | sr_err("sigma: %s: sdi->priv was NULL", __func__); | |
1390 | return SR_ERR_BUG; | |
1391 | } | |
1392 | ||
1393 | /* Stop acquisition. */ | |
1394 | sigma_set_register(WRITE_MODE, 0x11, ctx); | |
1395 | ||
1396 | /* Set SDRAM Read Enable. */ | |
1397 | sigma_set_register(WRITE_MODE, 0x02, ctx); | |
1398 | ||
1399 | /* Get the current position. */ | |
1400 | sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx); | |
1401 | ||
1402 | /* Check if trigger has fired. */ | |
1403 | modestatus = sigma_get_register(READ_MODE, ctx); | |
1404 | if (modestatus & 0x20) | |
1405 | ctx->state.triggerchunk = ctx->state.triggerpos / 512; | |
1406 | else | |
1407 | ctx->state.triggerchunk = -1; | |
1408 | ||
1409 | ctx->state.chunks_downloaded = 0; | |
1410 | ||
1411 | ctx->state.state = SIGMA_DOWNLOAD; | |
1412 | ||
1413 | return SR_OK; | |
1414 | } | |
1415 | ||
1416 | SR_PRIV struct sr_dev_plugin asix_sigma_plugin_info = { | |
1417 | .name = "asix-sigma", | |
1418 | .longname = "ASIX SIGMA", | |
1419 | .api_version = 1, | |
1420 | .init = hw_init, | |
1421 | .cleanup = hw_cleanup, | |
1422 | .dev_open = hw_dev_open, | |
1423 | .dev_close = hw_dev_close, | |
1424 | .dev_info_get = hw_dev_info_get, | |
1425 | .dev_status_get = hw_dev_status_get, | |
1426 | .hwcap_get_all = hw_hwcap_get_all, | |
1427 | .dev_config_set = hw_dev_config_set, | |
1428 | .dev_acquisition_start = hw_dev_acquisition_start, | |
1429 | .dev_acquisition_stop = hw_dev_acquisition_stop, | |
1430 | }; |