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1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include "libsigrok.h"
31#include "libsigrok-internal.h"
32#include "asix-sigma.h"
33
34#define USB_VENDOR 0xa600
35#define USB_PRODUCT 0xa000
36#define USB_DESCRIPTION "ASIX SIGMA"
37#define USB_VENDOR_NAME "ASIX"
38#define USB_MODEL_NAME "SIGMA"
39#define USB_MODEL_VERSION ""
40#define TRIGGER_TYPE "rf10"
41#define NUM_PROBES 16
42
43SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44static struct sr_dev_driver *di = &asix_sigma_driver_info;
45static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
46
47static const uint64_t samplerates[] = {
48 SR_KHZ(200),
49 SR_KHZ(250),
50 SR_KHZ(500),
51 SR_MHZ(1),
52 SR_MHZ(5),
53 SR_MHZ(10),
54 SR_MHZ(25),
55 SR_MHZ(50),
56 SR_MHZ(100),
57 SR_MHZ(200),
58};
59
60/*
61 * Channel numbers seem to go from 1-16, according to this image:
62 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
63 * (the cable has two additional GND pins, and a TI and TO pin)
64 */
65static const char *channel_names[NUM_PROBES + 1] = {
66 "1", "2", "3", "4", "5", "6", "7", "8",
67 "9", "10", "11", "12", "13", "14", "15", "16",
68 NULL,
69};
70
71static const int32_t hwcaps[] = {
72 SR_CONF_LOGIC_ANALYZER,
73 SR_CONF_SAMPLERATE,
74 SR_CONF_CAPTURE_RATIO,
75 SR_CONF_LIMIT_MSEC,
76};
77
78/* Force the FPGA to reboot. */
79static uint8_t suicide[] = {
80 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
81};
82
83/* Prepare to upload firmware (FPGA specific). */
84static uint8_t init_array[] = {
85 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
86};
87
88/* Initialize the logic analyzer mode. */
89static uint8_t logic_mode_start[] = {
90 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
91 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
92};
93
94static const char *firmware_files[] = {
95 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
96 "asix-sigma-100.fw", /* 100 MHz */
97 "asix-sigma-200.fw", /* 200 MHz */
98 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
99 "asix-sigma-phasor.fw", /* Frequency counter */
100};
101
102static int sigma_read(void *buf, size_t size, struct dev_context *devc)
103{
104 int ret;
105
106 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
107 if (ret < 0) {
108 sr_err("ftdi_read_data failed: %s",
109 ftdi_get_error_string(&devc->ftdic));
110 }
111
112 return ret;
113}
114
115static int sigma_write(void *buf, size_t size, struct dev_context *devc)
116{
117 int ret;
118
119 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
120 if (ret < 0) {
121 sr_err("ftdi_write_data failed: %s",
122 ftdi_get_error_string(&devc->ftdic));
123 } else if ((size_t) ret != size) {
124 sr_err("ftdi_write_data did not complete write.");
125 }
126
127 return ret;
128}
129
130static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
131 struct dev_context *devc)
132{
133 size_t i;
134 uint8_t buf[len + 2];
135 int idx = 0;
136
137 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
138 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
139
140 for (i = 0; i < len; ++i) {
141 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
142 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
143 }
144
145 return sigma_write(buf, idx, devc);
146}
147
148static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
149{
150 return sigma_write_register(reg, &value, 1, devc);
151}
152
153static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
154 struct dev_context *devc)
155{
156 uint8_t buf[3];
157
158 buf[0] = REG_ADDR_LOW | (reg & 0xf);
159 buf[1] = REG_ADDR_HIGH | (reg >> 4);
160 buf[2] = REG_READ_ADDR;
161
162 sigma_write(buf, sizeof(buf), devc);
163
164 return sigma_read(data, len, devc);
165}
166
167static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
168{
169 uint8_t value;
170
171 if (1 != sigma_read_register(reg, &value, 1, devc)) {
172 sr_err("sigma_get_register: 1 byte expected");
173 return 0;
174 }
175
176 return value;
177}
178
179static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
180 struct dev_context *devc)
181{
182 uint8_t buf[] = {
183 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
184
185 REG_READ_ADDR | NEXT_REG,
186 REG_READ_ADDR | NEXT_REG,
187 REG_READ_ADDR | NEXT_REG,
188 REG_READ_ADDR | NEXT_REG,
189 REG_READ_ADDR | NEXT_REG,
190 REG_READ_ADDR | NEXT_REG,
191 };
192 uint8_t result[6];
193
194 sigma_write(buf, sizeof(buf), devc);
195
196 sigma_read(result, sizeof(result), devc);
197
198 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
199 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
200
201 /* Not really sure why this must be done, but according to spec. */
202 if ((--*stoppos & 0x1ff) == 0x1ff)
203 stoppos -= 64;
204
205 if ((*--triggerpos & 0x1ff) == 0x1ff)
206 triggerpos -= 64;
207
208 return 1;
209}
210
211static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
212 uint8_t *data, struct dev_context *devc)
213{
214 size_t i;
215 uint8_t buf[4096];
216 int idx = 0;
217
218 /* Send the startchunk. Index start with 1. */
219 buf[0] = startchunk >> 8;
220 buf[1] = startchunk & 0xff;
221 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
222
223 /* Read the DRAM. */
224 buf[idx++] = REG_DRAM_BLOCK;
225 buf[idx++] = REG_DRAM_WAIT_ACK;
226
227 for (i = 0; i < numchunks; ++i) {
228 /* Alternate bit to copy from DRAM to cache. */
229 if (i != (numchunks - 1))
230 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
231
232 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
233
234 if (i != (numchunks - 1))
235 buf[idx++] = REG_DRAM_WAIT_ACK;
236 }
237
238 sigma_write(buf, idx, devc);
239
240 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
241}
242
243/* Upload trigger look-up tables to Sigma. */
244static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
245{
246 int i;
247 uint8_t tmp[2];
248 uint16_t bit;
249
250 /* Transpose the table and send to Sigma. */
251 for (i = 0; i < 16; ++i) {
252 bit = 1 << i;
253
254 tmp[0] = tmp[1] = 0;
255
256 if (lut->m2d[0] & bit)
257 tmp[0] |= 0x01;
258 if (lut->m2d[1] & bit)
259 tmp[0] |= 0x02;
260 if (lut->m2d[2] & bit)
261 tmp[0] |= 0x04;
262 if (lut->m2d[3] & bit)
263 tmp[0] |= 0x08;
264
265 if (lut->m3 & bit)
266 tmp[0] |= 0x10;
267 if (lut->m3s & bit)
268 tmp[0] |= 0x20;
269 if (lut->m4 & bit)
270 tmp[0] |= 0x40;
271
272 if (lut->m0d[0] & bit)
273 tmp[1] |= 0x01;
274 if (lut->m0d[1] & bit)
275 tmp[1] |= 0x02;
276 if (lut->m0d[2] & bit)
277 tmp[1] |= 0x04;
278 if (lut->m0d[3] & bit)
279 tmp[1] |= 0x08;
280
281 if (lut->m1d[0] & bit)
282 tmp[1] |= 0x10;
283 if (lut->m1d[1] & bit)
284 tmp[1] |= 0x20;
285 if (lut->m1d[2] & bit)
286 tmp[1] |= 0x40;
287 if (lut->m1d[3] & bit)
288 tmp[1] |= 0x80;
289
290 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
291 devc);
292 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
293 }
294
295 /* Send the parameters */
296 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
297 sizeof(lut->params), devc);
298
299 return SR_OK;
300}
301
302/* Generate the bitbang stream for programming the FPGA. */
303static int bin2bitbang(const char *filename,
304 unsigned char **buf, size_t *buf_size)
305{
306 FILE *f;
307 unsigned long file_size;
308 unsigned long offset = 0;
309 unsigned char *p;
310 uint8_t *firmware;
311 unsigned long fwsize = 0;
312 const int buffer_size = 65536;
313 size_t i;
314 int c, bit, v;
315 uint32_t imm = 0x3f6df2ab;
316
317 f = g_fopen(filename, "rb");
318 if (!f) {
319 sr_err("g_fopen(\"%s\", \"rb\")", filename);
320 return SR_ERR;
321 }
322
323 if (-1 == fseek(f, 0, SEEK_END)) {
324 sr_err("fseek on %s failed", filename);
325 fclose(f);
326 return SR_ERR;
327 }
328
329 file_size = ftell(f);
330
331 fseek(f, 0, SEEK_SET);
332
333 if (!(firmware = g_try_malloc(buffer_size))) {
334 sr_err("%s: firmware malloc failed", __func__);
335 fclose(f);
336 return SR_ERR_MALLOC;
337 }
338
339 while ((c = getc(f)) != EOF) {
340 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
341 firmware[fwsize++] = c ^ imm;
342 }
343 fclose(f);
344
345 if(fwsize != file_size) {
346 sr_err("%s: Error reading firmware", filename);
347 fclose(f);
348 g_free(firmware);
349 return SR_ERR;
350 }
351
352 *buf_size = fwsize * 2 * 8;
353
354 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
355 if (!p) {
356 sr_err("%s: buf/p malloc failed", __func__);
357 g_free(firmware);
358 return SR_ERR_MALLOC;
359 }
360
361 for (i = 0; i < fwsize; ++i) {
362 for (bit = 7; bit >= 0; --bit) {
363 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
364 p[offset++] = v | 0x01;
365 p[offset++] = v;
366 }
367 }
368
369 g_free(firmware);
370
371 if (offset != *buf_size) {
372 g_free(*buf);
373 sr_err("Error reading firmware %s "
374 "offset=%ld, file_size=%ld, buf_size=%zd.",
375 filename, offset, file_size, *buf_size);
376
377 return SR_ERR;
378 }
379
380 return SR_OK;
381}
382
383static void clear_helper(void *priv)
384{
385 struct dev_context *devc;
386
387 devc = priv;
388
389 ftdi_deinit(&devc->ftdic);
390}
391
392static int dev_clear(void)
393{
394 return std_dev_clear(di, clear_helper);
395}
396
397static int init(struct sr_context *sr_ctx)
398{
399 return std_init(sr_ctx, di, LOG_PREFIX);
400}
401
402static GSList *scan(GSList *options)
403{
404 struct sr_dev_inst *sdi;
405 struct sr_channel *ch;
406 struct drv_context *drvc;
407 struct dev_context *devc;
408 GSList *devices;
409 struct ftdi_device_list *devlist;
410 char serial_txt[10];
411 uint32_t serial;
412 int ret, i;
413
414 (void)options;
415
416 drvc = di->priv;
417
418 devices = NULL;
419
420 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
421 sr_err("%s: devc malloc failed", __func__);
422 return NULL;
423 }
424
425 ftdi_init(&devc->ftdic);
426
427 /* Look for SIGMAs. */
428
429 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
430 USB_VENDOR, USB_PRODUCT)) <= 0) {
431 if (ret < 0)
432 sr_err("ftdi_usb_find_all(): %d", ret);
433 goto free;
434 }
435
436 /* Make sure it's a version 1 or 2 SIGMA. */
437 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
438 serial_txt, sizeof(serial_txt));
439 sscanf(serial_txt, "%x", &serial);
440
441 if (serial < 0xa6010000 || serial > 0xa602ffff) {
442 sr_err("Only SIGMA and SIGMA2 are supported "
443 "in this version of libsigrok.");
444 goto free;
445 }
446
447 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
448
449 devc->cur_samplerate = 0;
450 devc->period_ps = 0;
451 devc->limit_msec = 0;
452 devc->cur_firmware = -1;
453 devc->num_channels = 0;
454 devc->samples_per_event = 0;
455 devc->capture_ratio = 50;
456 devc->use_triggers = 0;
457
458 /* Register SIGMA device. */
459 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
460 USB_MODEL_NAME, USB_MODEL_VERSION))) {
461 sr_err("%s: sdi was NULL", __func__);
462 goto free;
463 }
464 sdi->driver = di;
465
466 for (i = 0; channel_names[i]; i++) {
467 if (!(ch = sr_probe_new(i, SR_PROBE_LOGIC, TRUE,
468 channel_names[i])))
469 return NULL;
470 sdi->channels = g_slist_append(sdi->channels, ch);
471 }
472
473 devices = g_slist_append(devices, sdi);
474 drvc->instances = g_slist_append(drvc->instances, sdi);
475 sdi->priv = devc;
476
477 /* We will open the device again when we need it. */
478 ftdi_list_free(&devlist);
479
480 return devices;
481
482free:
483 ftdi_deinit(&devc->ftdic);
484 g_free(devc);
485 return NULL;
486}
487
488static GSList *dev_list(void)
489{
490 return ((struct drv_context *)(di->priv))->instances;
491}
492
493static int upload_firmware(int firmware_idx, struct dev_context *devc)
494{
495 int ret;
496 unsigned char *buf;
497 unsigned char pins;
498 size_t buf_size;
499 unsigned char result[32];
500 char firmware_path[128];
501
502 /* Make sure it's an ASIX SIGMA. */
503 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
504 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
505 sr_err("ftdi_usb_open failed: %s",
506 ftdi_get_error_string(&devc->ftdic));
507 return 0;
508 }
509
510 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
511 sr_err("ftdi_set_bitmode failed: %s",
512 ftdi_get_error_string(&devc->ftdic));
513 return 0;
514 }
515
516 /* Four times the speed of sigmalogan - Works well. */
517 if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
518 sr_err("ftdi_set_baudrate failed: %s",
519 ftdi_get_error_string(&devc->ftdic));
520 return 0;
521 }
522
523 /* Force the FPGA to reboot. */
524 sigma_write(suicide, sizeof(suicide), devc);
525 sigma_write(suicide, sizeof(suicide), devc);
526 sigma_write(suicide, sizeof(suicide), devc);
527 sigma_write(suicide, sizeof(suicide), devc);
528
529 /* Prepare to upload firmware (FPGA specific). */
530 sigma_write(init_array, sizeof(init_array), devc);
531
532 ftdi_usb_purge_buffers(&devc->ftdic);
533
534 /* Wait until the FPGA asserts INIT_B. */
535 while (1) {
536 ret = sigma_read(result, 1, devc);
537 if (result[0] & 0x20)
538 break;
539 }
540
541 /* Prepare firmware. */
542 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
543 firmware_files[firmware_idx]);
544
545 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
546 sr_err("An error occured while reading the firmware: %s",
547 firmware_path);
548 return ret;
549 }
550
551 /* Upload firmare. */
552 sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]);
553 sigma_write(buf, buf_size, devc);
554
555 g_free(buf);
556
557 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
558 sr_err("ftdi_set_bitmode failed: %s",
559 ftdi_get_error_string(&devc->ftdic));
560 return SR_ERR;
561 }
562
563 ftdi_usb_purge_buffers(&devc->ftdic);
564
565 /* Discard garbage. */
566 while (1 == sigma_read(&pins, 1, devc))
567 ;
568
569 /* Initialize the logic analyzer mode. */
570 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
571
572 /* Expect a 3 byte reply. */
573 ret = sigma_read(result, 3, devc);
574 if (ret != 3 ||
575 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
576 sr_err("Configuration failed. Invalid reply received.");
577 return SR_ERR;
578 }
579
580 devc->cur_firmware = firmware_idx;
581
582 sr_info("Firmware uploaded.");
583
584 return SR_OK;
585}
586
587static int dev_open(struct sr_dev_inst *sdi)
588{
589 struct dev_context *devc;
590 int ret;
591
592 devc = sdi->priv;
593
594 /* Make sure it's an ASIX SIGMA. */
595 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
596 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
597
598 sr_err("ftdi_usb_open failed: %s",
599 ftdi_get_error_string(&devc->ftdic));
600
601 return 0;
602 }
603
604 sdi->status = SR_ST_ACTIVE;
605
606 return SR_OK;
607}
608
609static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
610{
611 struct dev_context *devc;
612 unsigned int i;
613 int ret;
614
615 devc = sdi->priv;
616 ret = SR_OK;
617
618 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
619 if (samplerates[i] == samplerate)
620 break;
621 }
622 if (samplerates[i] == 0)
623 return SR_ERR_SAMPLERATE;
624
625 if (samplerate <= SR_MHZ(50)) {
626 ret = upload_firmware(0, devc);
627 devc->num_channels = 16;
628 }
629 if (samplerate == SR_MHZ(100)) {
630 ret = upload_firmware(1, devc);
631 devc->num_channels = 8;
632 }
633 else if (samplerate == SR_MHZ(200)) {
634 ret = upload_firmware(2, devc);
635 devc->num_channels = 4;
636 }
637
638 devc->cur_samplerate = samplerate;
639 devc->period_ps = 1000000000000ULL / samplerate;
640 devc->samples_per_event = 16 / devc->num_channels;
641 devc->state.state = SIGMA_IDLE;
642
643 return ret;
644}
645
646/*
647 * In 100 and 200 MHz mode, only a single pin rising/falling can be
648 * set as trigger. In other modes, two rising/falling triggers can be set,
649 * in addition to value/mask trigger for any number of channels.
650 *
651 * The Sigma supports complex triggers using boolean expressions, but this
652 * has not been implemented yet.
653 */
654static int configure_channels(const struct sr_dev_inst *sdi)
655{
656 struct dev_context *devc = sdi->priv;
657 const struct sr_channel *ch;
658 const GSList *l;
659 int trigger_set = 0;
660 int channelbit;
661
662 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
663
664 for (l = sdi->channels; l; l = l->next) {
665 ch = (struct sr_channel *)l->data;
666 channelbit = 1 << (ch->index);
667
668 if (!ch->enabled || !ch->trigger)
669 continue;
670
671 if (devc->cur_samplerate >= SR_MHZ(100)) {
672 /* Fast trigger support. */
673 if (trigger_set) {
674 sr_err("Only a single pin trigger in 100 and "
675 "200MHz mode is supported.");
676 return SR_ERR;
677 }
678 if (ch->trigger[0] == 'f')
679 devc->trigger.fallingmask |= channelbit;
680 else if (ch->trigger[0] == 'r')
681 devc->trigger.risingmask |= channelbit;
682 else {
683 sr_err("Only rising/falling trigger in 100 "
684 "and 200MHz mode is supported.");
685 return SR_ERR;
686 }
687
688 ++trigger_set;
689 } else {
690 /* Simple trigger support (event). */
691 if (ch->trigger[0] == '1') {
692 devc->trigger.simplevalue |= channelbit;
693 devc->trigger.simplemask |= channelbit;
694 }
695 else if (ch->trigger[0] == '0') {
696 devc->trigger.simplevalue &= ~channelbit;
697 devc->trigger.simplemask |= channelbit;
698 }
699 else if (ch->trigger[0] == 'f') {
700 devc->trigger.fallingmask |= channelbit;
701 ++trigger_set;
702 }
703 else if (ch->trigger[0] == 'r') {
704 devc->trigger.risingmask |= channelbit;
705 ++trigger_set;
706 }
707
708 /*
709 * Actually, Sigma supports 2 rising/falling triggers,
710 * but they are ORed and the current trigger syntax
711 * does not permit ORed triggers.
712 */
713 if (trigger_set > 1) {
714 sr_err("Only 1 rising/falling trigger "
715 "is supported.");
716 return SR_ERR;
717 }
718 }
719
720 if (trigger_set)
721 devc->use_triggers = 1;
722 }
723
724 return SR_OK;
725}
726
727static int dev_close(struct sr_dev_inst *sdi)
728{
729 struct dev_context *devc;
730
731 devc = sdi->priv;
732
733 /* TODO */
734 if (sdi->status == SR_ST_ACTIVE)
735 ftdi_usb_close(&devc->ftdic);
736
737 sdi->status = SR_ST_INACTIVE;
738
739 return SR_OK;
740}
741
742static int cleanup(void)
743{
744 return dev_clear();
745}
746
747static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
748 const struct sr_channel_group *cg)
749{
750 struct dev_context *devc;
751
752 (void)cg;
753
754 switch (id) {
755 case SR_CONF_SAMPLERATE:
756 if (sdi) {
757 devc = sdi->priv;
758 *data = g_variant_new_uint64(devc->cur_samplerate);
759 } else
760 return SR_ERR;
761 break;
762 default:
763 return SR_ERR_NA;
764 }
765
766 return SR_OK;
767}
768
769static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi,
770 const struct sr_channel_group *cg)
771{
772 struct dev_context *devc;
773 int ret;
774
775 (void)cg;
776
777 if (sdi->status != SR_ST_ACTIVE)
778 return SR_ERR_DEV_CLOSED;
779
780 devc = sdi->priv;
781
782 if (id == SR_CONF_SAMPLERATE) {
783 ret = set_samplerate(sdi, g_variant_get_uint64(data));
784 } else if (id == SR_CONF_LIMIT_MSEC) {
785 devc->limit_msec = g_variant_get_uint64(data);
786 if (devc->limit_msec > 0)
787 ret = SR_OK;
788 else
789 ret = SR_ERR;
790 } else if (id == SR_CONF_CAPTURE_RATIO) {
791 devc->capture_ratio = g_variant_get_uint64(data);
792 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
793 ret = SR_ERR;
794 else
795 ret = SR_OK;
796 } else {
797 ret = SR_ERR_NA;
798 }
799
800 return ret;
801}
802
803static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
804 const struct sr_channel_group *cg)
805{
806 GVariant *gvar;
807 GVariantBuilder gvb;
808
809 (void)sdi;
810 (void)cg;
811
812 switch (key) {
813 case SR_CONF_DEVICE_OPTIONS:
814 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
815 hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t));
816 break;
817 case SR_CONF_SAMPLERATE:
818 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
819 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
820 ARRAY_SIZE(samplerates), sizeof(uint64_t));
821 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
822 *data = g_variant_builder_end(&gvb);
823 break;
824 case SR_CONF_TRIGGER_TYPE:
825 *data = g_variant_new_string(TRIGGER_TYPE);
826 break;
827 default:
828 return SR_ERR_NA;
829 }
830
831 return SR_OK;
832}
833
834/* Software trigger to determine exact trigger position. */
835static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
836 struct sigma_trigger *t)
837{
838 int i;
839
840 for (i = 0; i < 8; ++i) {
841 if (i > 0)
842 last_sample = samples[i-1];
843
844 /* Simple triggers. */
845 if ((samples[i] & t->simplemask) != t->simplevalue)
846 continue;
847
848 /* Rising edge. */
849 if ((last_sample & t->risingmask) != 0 || (samples[i] &
850 t->risingmask) != t->risingmask)
851 continue;
852
853 /* Falling edge. */
854 if ((last_sample & t->fallingmask) != t->fallingmask ||
855 (samples[i] & t->fallingmask) != 0)
856 continue;
857
858 break;
859 }
860
861 /* If we did not match, return original trigger pos. */
862 return i & 0x7;
863}
864
865/*
866 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
867 * Each event is 20ns apart, and can contain multiple samples.
868 *
869 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
870 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
871 * For 50 MHz and below, events contain one sample for each channel,
872 * spread 20 ns apart.
873 */
874static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
875 uint16_t *lastsample, int triggerpos,
876 uint16_t limit_chunk, void *cb_data)
877{
878 struct sr_dev_inst *sdi = cb_data;
879 struct dev_context *devc = sdi->priv;
880 uint16_t tsdiff, ts;
881 uint16_t samples[65536 * devc->samples_per_event];
882 struct sr_datafeed_packet packet;
883 struct sr_datafeed_logic logic;
884 int i, j, k, l, numpad, tosend;
885 size_t n = 0, sent = 0;
886 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
887 uint16_t *event;
888 uint16_t cur_sample;
889 int triggerts = -1;
890
891 /* Check if trigger is in this chunk. */
892 if (triggerpos != -1) {
893 if (devc->cur_samplerate <= SR_MHZ(50))
894 triggerpos -= EVENTS_PER_CLUSTER - 1;
895
896 if (triggerpos < 0)
897 triggerpos = 0;
898
899 /* Find in which cluster the trigger occured. */
900 triggerts = triggerpos / 7;
901 }
902
903 /* For each ts. */
904 for (i = 0; i < 64; ++i) {
905 ts = *(uint16_t *) &buf[i * 16];
906 tsdiff = ts - *lastts;
907 *lastts = ts;
908
909 /* Decode partial chunk. */
910 if (limit_chunk && ts > limit_chunk)
911 return SR_OK;
912
913 /* Pad last sample up to current point. */
914 numpad = tsdiff * devc->samples_per_event - clustersize;
915 if (numpad > 0) {
916 for (j = 0; j < numpad; ++j)
917 samples[j] = *lastsample;
918
919 n = numpad;
920 }
921
922 /* Send samples between previous and this timestamp to sigrok. */
923 sent = 0;
924 while (sent < n) {
925 tosend = MIN(2048, n - sent);
926
927 packet.type = SR_DF_LOGIC;
928 packet.payload = &logic;
929 logic.length = tosend * sizeof(uint16_t);
930 logic.unitsize = 2;
931 logic.data = samples + sent;
932 sr_session_send(devc->cb_data, &packet);
933
934 sent += tosend;
935 }
936 n = 0;
937
938 event = (uint16_t *) &buf[i * 16 + 2];
939 cur_sample = 0;
940
941 /* For each event in cluster. */
942 for (j = 0; j < 7; ++j) {
943
944 /* For each sample in event. */
945 for (k = 0; k < devc->samples_per_event; ++k) {
946 cur_sample = 0;
947
948 /* For each channel. */
949 for (l = 0; l < devc->num_channels; ++l)
950 cur_sample |= (!!(event[j] & (1 << (l *
951 devc->samples_per_event + k)))) << l;
952
953 samples[n++] = cur_sample;
954 }
955 }
956
957 /* Send data up to trigger point (if triggered). */
958 sent = 0;
959 if (i == triggerts) {
960 /*
961 * Trigger is not always accurate to sample because of
962 * pipeline delay. However, it always triggers before
963 * the actual event. We therefore look at the next
964 * samples to pinpoint the exact position of the trigger.
965 */
966 tosend = get_trigger_offset(samples, *lastsample,
967 &devc->trigger);
968
969 if (tosend > 0) {
970 packet.type = SR_DF_LOGIC;
971 packet.payload = &logic;
972 logic.length = tosend * sizeof(uint16_t);
973 logic.unitsize = 2;
974 logic.data = samples;
975 sr_session_send(devc->cb_data, &packet);
976
977 sent += tosend;
978 }
979
980 /* Only send trigger if explicitly enabled. */
981 if (devc->use_triggers) {
982 packet.type = SR_DF_TRIGGER;
983 sr_session_send(devc->cb_data, &packet);
984 }
985 }
986
987 /* Send rest of the chunk to sigrok. */
988 tosend = n - sent;
989
990 if (tosend > 0) {
991 packet.type = SR_DF_LOGIC;
992 packet.payload = &logic;
993 logic.length = tosend * sizeof(uint16_t);
994 logic.unitsize = 2;
995 logic.data = samples + sent;
996 sr_session_send(devc->cb_data, &packet);
997 }
998
999 *lastsample = samples[n - 1];
1000 }
1001
1002 return SR_OK;
1003}
1004
1005static int receive_data(int fd, int revents, void *cb_data)
1006{
1007 struct sr_dev_inst *sdi = cb_data;
1008 struct dev_context *devc = sdi->priv;
1009 struct sr_datafeed_packet packet;
1010 const int chunks_per_read = 32;
1011 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1012 int bufsz, numchunks, i, newchunks;
1013 uint64_t running_msec;
1014 struct timeval tv;
1015
1016 (void)fd;
1017 (void)revents;
1018
1019 /* Get the current position. */
1020 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1021
1022 numchunks = (devc->state.stoppos + 511) / 512;
1023
1024 if (devc->state.state == SIGMA_IDLE)
1025 return TRUE;
1026
1027 if (devc->state.state == SIGMA_CAPTURE) {
1028 /* Check if the timer has expired, or memory is full. */
1029 gettimeofday(&tv, 0);
1030 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1031 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1032
1033 if (running_msec < devc->limit_msec && numchunks < 32767)
1034 return TRUE; /* While capturing... */
1035 else
1036 dev_acquisition_stop(sdi, sdi);
1037
1038 }
1039
1040 if (devc->state.state == SIGMA_DOWNLOAD) {
1041 if (devc->state.chunks_downloaded >= numchunks) {
1042 /* End of samples. */
1043 packet.type = SR_DF_END;
1044 sr_session_send(devc->cb_data, &packet);
1045
1046 devc->state.state = SIGMA_IDLE;
1047
1048 return TRUE;
1049 }
1050
1051 newchunks = MIN(chunks_per_read,
1052 numchunks - devc->state.chunks_downloaded);
1053
1054 sr_info("Downloading sample data: %.0f %%.",
1055 100.0 * devc->state.chunks_downloaded / numchunks);
1056
1057 bufsz = sigma_read_dram(devc->state.chunks_downloaded,
1058 newchunks, buf, devc);
1059 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1060 (void)bufsz;
1061
1062 /* Find first ts. */
1063 if (devc->state.chunks_downloaded == 0) {
1064 devc->state.lastts = RL16(buf) - 1;
1065 devc->state.lastsample = 0;
1066 }
1067
1068 /* Decode chunks and send them to sigrok. */
1069 for (i = 0; i < newchunks; ++i) {
1070 int limit_chunk = 0;
1071
1072 /* The last chunk may potentially be only in part. */
1073 if (devc->state.chunks_downloaded == numchunks - 1) {
1074 /* Find the last valid timestamp */
1075 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1076 }
1077
1078 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1079 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1080 &devc->state.lastts,
1081 &devc->state.lastsample,
1082 devc->state.triggerpos & 0x1ff,
1083 limit_chunk, sdi);
1084 else
1085 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1086 &devc->state.lastts,
1087 &devc->state.lastsample,
1088 -1, limit_chunk, sdi);
1089
1090 ++devc->state.chunks_downloaded;
1091 }
1092 }
1093
1094 return TRUE;
1095}
1096
1097/* Build a LUT entry used by the trigger functions. */
1098static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1099{
1100 int i, j, k, bit;
1101
1102 /* For each quad channel. */
1103 for (i = 0; i < 4; ++i) {
1104 entry[i] = 0xffff;
1105
1106 /* For each bit in LUT. */
1107 for (j = 0; j < 16; ++j)
1108
1109 /* For each channel in quad. */
1110 for (k = 0; k < 4; ++k) {
1111 bit = 1 << (i * 4 + k);
1112
1113 /* Set bit in entry */
1114 if ((mask & bit) &&
1115 ((!(value & bit)) !=
1116 (!(j & (1 << k)))))
1117 entry[i] &= ~(1 << j);
1118 }
1119 }
1120}
1121
1122/* Add a logical function to LUT mask. */
1123static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1124 int index, int neg, uint16_t *mask)
1125{
1126 int i, j;
1127 int x[2][2], tmp, a, b, aset, bset, rset;
1128
1129 memset(x, 0, 4 * sizeof(int));
1130
1131 /* Trigger detect condition. */
1132 switch (oper) {
1133 case OP_LEVEL:
1134 x[0][1] = 1;
1135 x[1][1] = 1;
1136 break;
1137 case OP_NOT:
1138 x[0][0] = 1;
1139 x[1][0] = 1;
1140 break;
1141 case OP_RISE:
1142 x[0][1] = 1;
1143 break;
1144 case OP_FALL:
1145 x[1][0] = 1;
1146 break;
1147 case OP_RISEFALL:
1148 x[0][1] = 1;
1149 x[1][0] = 1;
1150 break;
1151 case OP_NOTRISE:
1152 x[1][1] = 1;
1153 x[0][0] = 1;
1154 x[1][0] = 1;
1155 break;
1156 case OP_NOTFALL:
1157 x[1][1] = 1;
1158 x[0][0] = 1;
1159 x[0][1] = 1;
1160 break;
1161 case OP_NOTRISEFALL:
1162 x[1][1] = 1;
1163 x[0][0] = 1;
1164 break;
1165 }
1166
1167 /* Transpose if neg is set. */
1168 if (neg) {
1169 for (i = 0; i < 2; ++i) {
1170 for (j = 0; j < 2; ++j) {
1171 tmp = x[i][j];
1172 x[i][j] = x[1-i][1-j];
1173 x[1-i][1-j] = tmp;
1174 }
1175 }
1176 }
1177
1178 /* Update mask with function. */
1179 for (i = 0; i < 16; ++i) {
1180 a = (i >> (2 * index + 0)) & 1;
1181 b = (i >> (2 * index + 1)) & 1;
1182
1183 aset = (*mask >> i) & 1;
1184 bset = x[b][a];
1185
1186 if (func == FUNC_AND || func == FUNC_NAND)
1187 rset = aset & bset;
1188 else if (func == FUNC_OR || func == FUNC_NOR)
1189 rset = aset | bset;
1190 else if (func == FUNC_XOR || func == FUNC_NXOR)
1191 rset = aset ^ bset;
1192
1193 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1194 rset = !rset;
1195
1196 *mask &= ~(1 << i);
1197
1198 if (rset)
1199 *mask |= 1 << i;
1200 }
1201}
1202
1203/*
1204 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1205 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1206 * set at any time, but a full mask and value can be set (0/1).
1207 */
1208static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1209{
1210 int i,j;
1211 uint16_t masks[2] = { 0, 0 };
1212
1213 memset(lut, 0, sizeof(struct triggerlut));
1214
1215 /* Contant for simple triggers. */
1216 lut->m4 = 0xa000;
1217
1218 /* Value/mask trigger support. */
1219 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1220 lut->m2d);
1221
1222 /* Rise/fall trigger support. */
1223 for (i = 0, j = 0; i < 16; ++i) {
1224 if (devc->trigger.risingmask & (1 << i) ||
1225 devc->trigger.fallingmask & (1 << i))
1226 masks[j++] = 1 << i;
1227 }
1228
1229 build_lut_entry(masks[0], masks[0], lut->m0d);
1230 build_lut_entry(masks[1], masks[1], lut->m1d);
1231
1232 /* Add glue logic */
1233 if (masks[0] || masks[1]) {
1234 /* Transition trigger. */
1235 if (masks[0] & devc->trigger.risingmask)
1236 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1237 if (masks[0] & devc->trigger.fallingmask)
1238 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1239 if (masks[1] & devc->trigger.risingmask)
1240 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1241 if (masks[1] & devc->trigger.fallingmask)
1242 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1243 } else {
1244 /* Only value/mask trigger. */
1245 lut->m3 = 0xffff;
1246 }
1247
1248 /* Triggertype: event. */
1249 lut->params.selres = 3;
1250
1251 return SR_OK;
1252}
1253
1254static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
1255{
1256 struct dev_context *devc;
1257 struct clockselect_50 clockselect;
1258 int frac, triggerpin, ret;
1259 uint8_t triggerselect = 0;
1260 struct triggerinout triggerinout_conf;
1261 struct triggerlut lut;
1262
1263 if (sdi->status != SR_ST_ACTIVE)
1264 return SR_ERR_DEV_CLOSED;
1265
1266 devc = sdi->priv;
1267
1268 if (configure_channels(sdi) != SR_OK) {
1269 sr_err("Failed to configure channels.");
1270 return SR_ERR;
1271 }
1272
1273 /* If the samplerate has not been set, default to 200 kHz. */
1274 if (devc->cur_firmware == -1) {
1275 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1276 return ret;
1277 }
1278
1279 /* Enter trigger programming mode. */
1280 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1281
1282 /* 100 and 200 MHz mode. */
1283 if (devc->cur_samplerate >= SR_MHZ(100)) {
1284 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1285
1286 /* Find which pin to trigger on from mask. */
1287 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1288 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1289 (1 << triggerpin))
1290 break;
1291
1292 /* Set trigger pin and light LED on trigger. */
1293 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1294
1295 /* Default rising edge. */
1296 if (devc->trigger.fallingmask)
1297 triggerselect |= 1 << 3;
1298
1299 /* All other modes. */
1300 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1301 build_basic_trigger(&lut, devc);
1302
1303 sigma_write_trigger_lut(&lut, devc);
1304
1305 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1306 }
1307
1308 /* Setup trigger in and out pins to default values. */
1309 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1310 triggerinout_conf.trgout_bytrigger = 1;
1311 triggerinout_conf.trgout_enable = 1;
1312
1313 sigma_write_register(WRITE_TRIGGER_OPTION,
1314 (uint8_t *) &triggerinout_conf,
1315 sizeof(struct triggerinout), devc);
1316
1317 /* Go back to normal mode. */
1318 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1319
1320 /* Set clock select register. */
1321 if (devc->cur_samplerate == SR_MHZ(200))
1322 /* Enable 4 channels. */
1323 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1324 else if (devc->cur_samplerate == SR_MHZ(100))
1325 /* Enable 8 channels. */
1326 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1327 else {
1328 /*
1329 * 50 MHz mode (or fraction thereof). Any fraction down to
1330 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1331 */
1332 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1333
1334 clockselect.async = 0;
1335 clockselect.fraction = frac;
1336 clockselect.disabled_channels = 0;
1337
1338 sigma_write_register(WRITE_CLOCK_SELECT,
1339 (uint8_t *) &clockselect,
1340 sizeof(clockselect), devc);
1341 }
1342
1343 /* Setup maximum post trigger time. */
1344 sigma_set_register(WRITE_POST_TRIGGER,
1345 (devc->capture_ratio * 255) / 100, devc);
1346
1347 /* Start acqusition. */
1348 gettimeofday(&devc->start_tv, 0);
1349 sigma_set_register(WRITE_MODE, 0x0d, devc);
1350
1351 devc->cb_data = cb_data;
1352
1353 /* Send header packet to the session bus. */
1354 std_session_send_df_header(cb_data, LOG_PREFIX);
1355
1356 /* Add capture source. */
1357 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1358
1359 devc->state.state = SIGMA_CAPTURE;
1360
1361 return SR_OK;
1362}
1363
1364static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1365{
1366 struct dev_context *devc;
1367 uint8_t modestatus;
1368
1369 (void)cb_data;
1370
1371 sr_source_remove(0);
1372
1373 if (!(devc = sdi->priv)) {
1374 sr_err("%s: sdi->priv was NULL", __func__);
1375 return SR_ERR_BUG;
1376 }
1377
1378 /* Stop acquisition. */
1379 sigma_set_register(WRITE_MODE, 0x11, devc);
1380
1381 /* Set SDRAM Read Enable. */
1382 sigma_set_register(WRITE_MODE, 0x02, devc);
1383
1384 /* Get the current position. */
1385 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1386
1387 /* Check if trigger has fired. */
1388 modestatus = sigma_get_register(READ_MODE, devc);
1389 if (modestatus & 0x20)
1390 devc->state.triggerchunk = devc->state.triggerpos / 512;
1391 else
1392 devc->state.triggerchunk = -1;
1393
1394 devc->state.chunks_downloaded = 0;
1395
1396 devc->state.state = SIGMA_DOWNLOAD;
1397
1398 return SR_OK;
1399}
1400
1401SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1402 .name = "asix-sigma",
1403 .longname = "ASIX SIGMA/SIGMA2",
1404 .api_version = 1,
1405 .init = init,
1406 .cleanup = cleanup,
1407 .scan = scan,
1408 .dev_list = dev_list,
1409 .dev_clear = dev_clear,
1410 .config_get = config_get,
1411 .config_set = config_set,
1412 .config_list = config_list,
1413 .dev_open = dev_open,
1414 .dev_close = dev_close,
1415 .dev_acquisition_start = dev_acquisition_start,
1416 .dev_acquisition_stop = dev_acquisition_stop,
1417 .priv = NULL,
1418};
Hardware access and backend lib