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sr: new API call sr_dev_config_set()
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1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include "libsigrok.h"
31#include "libsigrok-internal.h"
32#include "asix-sigma.h"
33
34#define USB_VENDOR 0xa600
35#define USB_PRODUCT 0xa000
36#define USB_DESCRIPTION "ASIX SIGMA"
37#define USB_VENDOR_NAME "ASIX"
38#define USB_MODEL_NAME "SIGMA"
39#define USB_MODEL_VERSION ""
40#define TRIGGER_TYPES "rf10"
41#define NUM_PROBES 16
42
43SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44static struct sr_dev_driver *adi = &asix_sigma_driver_info;
45
46static const uint64_t supported_samplerates[] = {
47 SR_KHZ(200),
48 SR_KHZ(250),
49 SR_KHZ(500),
50 SR_MHZ(1),
51 SR_MHZ(5),
52 SR_MHZ(10),
53 SR_MHZ(25),
54 SR_MHZ(50),
55 SR_MHZ(100),
56 SR_MHZ(200),
57 0,
58};
59
60/*
61 * Probe numbers seem to go from 1-16, according to this image:
62 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
63 * (the cable has two additional GND pins, and a TI and TO pin)
64 */
65static const char *probe_names[NUM_PROBES + 1] = {
66 "1",
67 "2",
68 "3",
69 "4",
70 "5",
71 "6",
72 "7",
73 "8",
74 "9",
75 "10",
76 "11",
77 "12",
78 "13",
79 "14",
80 "15",
81 "16",
82 NULL,
83};
84
85static const struct sr_samplerates samplerates = {
86 0,
87 0,
88 0,
89 supported_samplerates,
90};
91
92static const int hwcaps[] = {
93 SR_HWCAP_LOGIC_ANALYZER,
94 SR_HWCAP_SAMPLERATE,
95 SR_HWCAP_CAPTURE_RATIO,
96 SR_HWCAP_PROBECONFIG,
97
98 SR_HWCAP_LIMIT_MSEC,
99 0,
100};
101
102/* Force the FPGA to reboot. */
103static uint8_t suicide[] = {
104 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
105};
106
107/* Prepare to upload firmware (FPGA specific). */
108static uint8_t init[] = {
109 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
110};
111
112/* Initialize the logic analyzer mode. */
113static uint8_t logic_mode_start[] = {
114 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
115 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
116};
117
118static const char *firmware_files[] = {
119 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
120 "asix-sigma-100.fw", /* 100 MHz */
121 "asix-sigma-200.fw", /* 200 MHz */
122 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
123 "asix-sigma-phasor.fw", /* Frequency counter */
124};
125
126static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi,
127 void *cb_data);
128
129static int sigma_read(void *buf, size_t size, struct dev_context *devc)
130{
131 int ret;
132
133 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
134 if (ret < 0) {
135 sr_err("sigma: ftdi_read_data failed: %s",
136 ftdi_get_error_string(&devc->ftdic));
137 }
138
139 return ret;
140}
141
142static int sigma_write(void *buf, size_t size, struct dev_context *devc)
143{
144 int ret;
145
146 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
147 if (ret < 0) {
148 sr_err("sigma: ftdi_write_data failed: %s",
149 ftdi_get_error_string(&devc->ftdic));
150 } else if ((size_t) ret != size) {
151 sr_err("sigma: ftdi_write_data did not complete write.");
152 }
153
154 return ret;
155}
156
157static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
158 struct dev_context *devc)
159{
160 size_t i;
161 uint8_t buf[len + 2];
162 int idx = 0;
163
164 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
165 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
166
167 for (i = 0; i < len; ++i) {
168 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
169 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
170 }
171
172 return sigma_write(buf, idx, devc);
173}
174
175static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
176{
177 return sigma_write_register(reg, &value, 1, devc);
178}
179
180static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
181 struct dev_context *devc)
182{
183 uint8_t buf[3];
184
185 buf[0] = REG_ADDR_LOW | (reg & 0xf);
186 buf[1] = REG_ADDR_HIGH | (reg >> 4);
187 buf[2] = REG_READ_ADDR;
188
189 sigma_write(buf, sizeof(buf), devc);
190
191 return sigma_read(data, len, devc);
192}
193
194static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
195{
196 uint8_t value;
197
198 if (1 != sigma_read_register(reg, &value, 1, devc)) {
199 sr_err("sigma: sigma_get_register: 1 byte expected");
200 return 0;
201 }
202
203 return value;
204}
205
206static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
207 struct dev_context *devc)
208{
209 uint8_t buf[] = {
210 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
211
212 REG_READ_ADDR | NEXT_REG,
213 REG_READ_ADDR | NEXT_REG,
214 REG_READ_ADDR | NEXT_REG,
215 REG_READ_ADDR | NEXT_REG,
216 REG_READ_ADDR | NEXT_REG,
217 REG_READ_ADDR | NEXT_REG,
218 };
219 uint8_t result[6];
220
221 sigma_write(buf, sizeof(buf), devc);
222
223 sigma_read(result, sizeof(result), devc);
224
225 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
226 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
227
228 /* Not really sure why this must be done, but according to spec. */
229 if ((--*stoppos & 0x1ff) == 0x1ff)
230 stoppos -= 64;
231
232 if ((*--triggerpos & 0x1ff) == 0x1ff)
233 triggerpos -= 64;
234
235 return 1;
236}
237
238static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
239 uint8_t *data, struct dev_context *devc)
240{
241 size_t i;
242 uint8_t buf[4096];
243 int idx = 0;
244
245 /* Send the startchunk. Index start with 1. */
246 buf[0] = startchunk >> 8;
247 buf[1] = startchunk & 0xff;
248 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
249
250 /* Read the DRAM. */
251 buf[idx++] = REG_DRAM_BLOCK;
252 buf[idx++] = REG_DRAM_WAIT_ACK;
253
254 for (i = 0; i < numchunks; ++i) {
255 /* Alternate bit to copy from DRAM to cache. */
256 if (i != (numchunks - 1))
257 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
258
259 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
260
261 if (i != (numchunks - 1))
262 buf[idx++] = REG_DRAM_WAIT_ACK;
263 }
264
265 sigma_write(buf, idx, devc);
266
267 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
268}
269
270/* Upload trigger look-up tables to Sigma. */
271static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
272{
273 int i;
274 uint8_t tmp[2];
275 uint16_t bit;
276
277 /* Transpose the table and send to Sigma. */
278 for (i = 0; i < 16; ++i) {
279 bit = 1 << i;
280
281 tmp[0] = tmp[1] = 0;
282
283 if (lut->m2d[0] & bit)
284 tmp[0] |= 0x01;
285 if (lut->m2d[1] & bit)
286 tmp[0] |= 0x02;
287 if (lut->m2d[2] & bit)
288 tmp[0] |= 0x04;
289 if (lut->m2d[3] & bit)
290 tmp[0] |= 0x08;
291
292 if (lut->m3 & bit)
293 tmp[0] |= 0x10;
294 if (lut->m3s & bit)
295 tmp[0] |= 0x20;
296 if (lut->m4 & bit)
297 tmp[0] |= 0x40;
298
299 if (lut->m0d[0] & bit)
300 tmp[1] |= 0x01;
301 if (lut->m0d[1] & bit)
302 tmp[1] |= 0x02;
303 if (lut->m0d[2] & bit)
304 tmp[1] |= 0x04;
305 if (lut->m0d[3] & bit)
306 tmp[1] |= 0x08;
307
308 if (lut->m1d[0] & bit)
309 tmp[1] |= 0x10;
310 if (lut->m1d[1] & bit)
311 tmp[1] |= 0x20;
312 if (lut->m1d[2] & bit)
313 tmp[1] |= 0x40;
314 if (lut->m1d[3] & bit)
315 tmp[1] |= 0x80;
316
317 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
318 devc);
319 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
320 }
321
322 /* Send the parameters */
323 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
324 sizeof(lut->params), devc);
325
326 return SR_OK;
327}
328
329/* Generate the bitbang stream for programming the FPGA. */
330static int bin2bitbang(const char *filename,
331 unsigned char **buf, size_t *buf_size)
332{
333 FILE *f;
334 unsigned long file_size;
335 unsigned long offset = 0;
336 unsigned char *p;
337 uint8_t *firmware;
338 unsigned long fwsize = 0;
339 const int buffer_size = 65536;
340 size_t i;
341 int c, bit, v;
342 uint32_t imm = 0x3f6df2ab;
343
344 f = g_fopen(filename, "rb");
345 if (!f) {
346 sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename);
347 return SR_ERR;
348 }
349
350 if (-1 == fseek(f, 0, SEEK_END)) {
351 sr_err("sigma: fseek on %s failed", filename);
352 fclose(f);
353 return SR_ERR;
354 }
355
356 file_size = ftell(f);
357
358 fseek(f, 0, SEEK_SET);
359
360 if (!(firmware = g_try_malloc(buffer_size))) {
361 sr_err("sigma: %s: firmware malloc failed", __func__);
362 fclose(f);
363 return SR_ERR_MALLOC;
364 }
365
366 while ((c = getc(f)) != EOF) {
367 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
368 firmware[fwsize++] = c ^ imm;
369 }
370 fclose(f);
371
372 if(fwsize != file_size) {
373 sr_err("sigma: %s: Error reading firmware", filename);
374 fclose(f);
375 g_free(firmware);
376 return SR_ERR;
377 }
378
379 *buf_size = fwsize * 2 * 8;
380
381 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
382 if (!p) {
383 sr_err("sigma: %s: buf/p malloc failed", __func__);
384 g_free(firmware);
385 return SR_ERR_MALLOC;
386 }
387
388 for (i = 0; i < fwsize; ++i) {
389 for (bit = 7; bit >= 0; --bit) {
390 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
391 p[offset++] = v | 0x01;
392 p[offset++] = v;
393 }
394 }
395
396 g_free(firmware);
397
398 if (offset != *buf_size) {
399 g_free(*buf);
400 sr_err("sigma: Error reading firmware %s "
401 "offset=%ld, file_size=%ld, buf_size=%zd.",
402 filename, offset, file_size, *buf_size);
403
404 return SR_ERR;
405 }
406
407 return SR_OK;
408}
409
410static void clear_instances(void)
411{
412 GSList *l;
413 struct sr_dev_inst *sdi;
414 struct drv_context *drvc;
415 struct dev_context *devc;
416
417 drvc = adi->priv;
418
419 /* Properly close all devices. */
420 for (l = drvc->instances; l; l = l->next) {
421 if (!(sdi = l->data)) {
422 /* Log error, but continue cleaning up the rest. */
423 sr_err("sigma: %s: sdi was NULL, continuing", __func__);
424 continue;
425 }
426 if (sdi->priv) {
427 devc = sdi->priv;
428 ftdi_free(&devc->ftdic);
429 }
430 sr_dev_inst_free(sdi);
431 }
432 g_slist_free(drvc->instances);
433 drvc->instances = NULL;
434
435}
436
437static int hw_init(void)
438{
439 struct drv_context *drvc;
440
441 if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) {
442 sr_err("asix-sigma: driver context malloc failed.");
443 return SR_ERR;
444 }
445 adi->priv = drvc;
446
447 return SR_OK;
448}
449
450static GSList *hw_scan(GSList *options)
451{
452 struct sr_dev_inst *sdi;
453 struct sr_probe *probe;
454 struct drv_context *drvc;
455 struct dev_context *devc;
456 GSList *devices;
457 struct ftdi_device_list *devlist;
458 char serial_txt[10];
459 uint32_t serial;
460 int ret, i;
461
462 (void)options;
463 drvc = adi->priv;
464 devices = NULL;
465 clear_instances();
466
467 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
468 sr_err("sigma: %s: devc malloc failed", __func__);
469 return NULL;
470 }
471
472 ftdi_init(&devc->ftdic);
473
474 /* Look for SIGMAs. */
475
476 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
477 USB_VENDOR, USB_PRODUCT)) <= 0) {
478 if (ret < 0)
479 sr_err("ftdi_usb_find_all(): %d", ret);
480 goto free;
481 }
482
483 /* Make sure it's a version 1 or 2 SIGMA. */
484 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
485 serial_txt, sizeof(serial_txt));
486 sscanf(serial_txt, "%x", &serial);
487
488 if (serial < 0xa6010000 || serial > 0xa602ffff) {
489 sr_err("sigma: Only SIGMA and SIGMA2 are supported "
490 "in this version of sigrok.");
491 goto free;
492 }
493
494 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
495
496 devc->cur_samplerate = 0;
497 devc->period_ps = 0;
498 devc->limit_msec = 0;
499 devc->cur_firmware = -1;
500 devc->num_probes = 0;
501 devc->samples_per_event = 0;
502 devc->capture_ratio = 50;
503 devc->use_triggers = 0;
504
505 /* Register SIGMA device. */
506 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
507 USB_MODEL_NAME, USB_MODEL_VERSION))) {
508 sr_err("sigma: %s: sdi was NULL", __func__);
509 goto free;
510 }
511 sdi->driver = adi;
512
513 for (i = 0; probe_names[i]; i++) {
514 if (!(probe = sr_probe_new(i, SR_PROBE_ANALOG, TRUE,
515 probe_names[i])))
516 return NULL;
517 sdi->probes = g_slist_append(sdi->probes, probe);
518 }
519
520 devices = g_slist_append(devices, sdi);
521 drvc->instances = g_slist_append(drvc->instances, sdi);
522 sdi->priv = devc;
523
524 /* We will open the device again when we need it. */
525 ftdi_list_free(&devlist);
526
527 return devices;
528
529free:
530 ftdi_deinit(&devc->ftdic);
531 g_free(devc);
532 return NULL;
533}
534
535static int upload_firmware(int firmware_idx, struct dev_context *devc)
536{
537 int ret;
538 unsigned char *buf;
539 unsigned char pins;
540 size_t buf_size;
541 unsigned char result[32];
542 char firmware_path[128];
543
544 /* Make sure it's an ASIX SIGMA. */
545 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
546 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
547 sr_err("sigma: ftdi_usb_open failed: %s",
548 ftdi_get_error_string(&devc->ftdic));
549 return 0;
550 }
551
552 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
553 sr_err("sigma: ftdi_set_bitmode failed: %s",
554 ftdi_get_error_string(&devc->ftdic));
555 return 0;
556 }
557
558 /* Four times the speed of sigmalogan - Works well. */
559 if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
560 sr_err("sigma: ftdi_set_baudrate failed: %s",
561 ftdi_get_error_string(&devc->ftdic));
562 return 0;
563 }
564
565 /* Force the FPGA to reboot. */
566 sigma_write(suicide, sizeof(suicide), devc);
567 sigma_write(suicide, sizeof(suicide), devc);
568 sigma_write(suicide, sizeof(suicide), devc);
569 sigma_write(suicide, sizeof(suicide), devc);
570
571 /* Prepare to upload firmware (FPGA specific). */
572 sigma_write(init, sizeof(init), devc);
573
574 ftdi_usb_purge_buffers(&devc->ftdic);
575
576 /* Wait until the FPGA asserts INIT_B. */
577 while (1) {
578 ret = sigma_read(result, 1, devc);
579 if (result[0] & 0x20)
580 break;
581 }
582
583 /* Prepare firmware. */
584 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
585 firmware_files[firmware_idx]);
586
587 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
588 sr_err("sigma: An error occured while reading the firmware: %s",
589 firmware_path);
590 return ret;
591 }
592
593 /* Upload firmare. */
594 sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]);
595 sigma_write(buf, buf_size, devc);
596
597 g_free(buf);
598
599 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
600 sr_err("sigma: ftdi_set_bitmode failed: %s",
601 ftdi_get_error_string(&devc->ftdic));
602 return SR_ERR;
603 }
604
605 ftdi_usb_purge_buffers(&devc->ftdic);
606
607 /* Discard garbage. */
608 while (1 == sigma_read(&pins, 1, devc))
609 ;
610
611 /* Initialize the logic analyzer mode. */
612 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
613
614 /* Expect a 3 byte reply. */
615 ret = sigma_read(result, 3, devc);
616 if (ret != 3 ||
617 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
618 sr_err("sigma: Configuration failed. Invalid reply received.");
619 return SR_ERR;
620 }
621
622 devc->cur_firmware = firmware_idx;
623
624 sr_info("sigma: Firmware uploaded");
625
626 return SR_OK;
627}
628
629static int hw_dev_open(struct sr_dev_inst *sdi)
630{
631 struct dev_context *devc;
632 int ret;
633
634 devc = sdi->priv;
635
636 /* Make sure it's an ASIX SIGMA. */
637 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
638 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
639
640 sr_err("sigma: ftdi_usb_open failed: %s",
641 ftdi_get_error_string(&devc->ftdic));
642
643 return 0;
644 }
645
646 sdi->status = SR_ST_ACTIVE;
647
648 return SR_OK;
649}
650
651static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
652{
653 int i, ret;
654 struct dev_context *devc = sdi->priv;
655
656 for (i = 0; supported_samplerates[i]; i++) {
657 if (supported_samplerates[i] == samplerate)
658 break;
659 }
660 if (supported_samplerates[i] == 0)
661 return SR_ERR_SAMPLERATE;
662
663 if (samplerate <= SR_MHZ(50)) {
664 ret = upload_firmware(0, devc);
665 devc->num_probes = 16;
666 }
667 if (samplerate == SR_MHZ(100)) {
668 ret = upload_firmware(1, devc);
669 devc->num_probes = 8;
670 }
671 else if (samplerate == SR_MHZ(200)) {
672 ret = upload_firmware(2, devc);
673 devc->num_probes = 4;
674 }
675
676 devc->cur_samplerate = samplerate;
677 devc->period_ps = 1000000000000 / samplerate;
678 devc->samples_per_event = 16 / devc->num_probes;
679 devc->state.state = SIGMA_IDLE;
680
681 return ret;
682}
683
684/*
685 * In 100 and 200 MHz mode, only a single pin rising/falling can be
686 * set as trigger. In other modes, two rising/falling triggers can be set,
687 * in addition to value/mask trigger for any number of probes.
688 *
689 * The Sigma supports complex triggers using boolean expressions, but this
690 * has not been implemented yet.
691 */
692static int configure_probes(const struct sr_dev_inst *sdi, const GSList *probes)
693{
694 struct dev_context *devc = sdi->priv;
695 const struct sr_probe *probe;
696 const GSList *l;
697 int trigger_set = 0;
698 int probebit;
699
700 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
701
702 for (l = probes; l; l = l->next) {
703 probe = (struct sr_probe *)l->data;
704 probebit = 1 << (probe->index);
705
706 if (!probe->enabled || !probe->trigger)
707 continue;
708
709 if (devc->cur_samplerate >= SR_MHZ(100)) {
710 /* Fast trigger support. */
711 if (trigger_set) {
712 sr_err("sigma: ASIX SIGMA only supports a single "
713 "pin trigger in 100 and 200MHz mode.");
714 return SR_ERR;
715 }
716 if (probe->trigger[0] == 'f')
717 devc->trigger.fallingmask |= probebit;
718 else if (probe->trigger[0] == 'r')
719 devc->trigger.risingmask |= probebit;
720 else {
721 sr_err("sigma: ASIX SIGMA only supports "
722 "rising/falling trigger in 100 "
723 "and 200MHz mode.");
724 return SR_ERR;
725 }
726
727 ++trigger_set;
728 } else {
729 /* Simple trigger support (event). */
730 if (probe->trigger[0] == '1') {
731 devc->trigger.simplevalue |= probebit;
732 devc->trigger.simplemask |= probebit;
733 }
734 else if (probe->trigger[0] == '0') {
735 devc->trigger.simplevalue &= ~probebit;
736 devc->trigger.simplemask |= probebit;
737 }
738 else if (probe->trigger[0] == 'f') {
739 devc->trigger.fallingmask |= probebit;
740 ++trigger_set;
741 }
742 else if (probe->trigger[0] == 'r') {
743 devc->trigger.risingmask |= probebit;
744 ++trigger_set;
745 }
746
747 /*
748 * Actually, Sigma supports 2 rising/falling triggers,
749 * but they are ORed and the current trigger syntax
750 * does not permit ORed triggers.
751 */
752 if (trigger_set > 1) {
753 sr_err("sigma: ASIX SIGMA only supports 1 "
754 "rising/falling triggers.");
755 return SR_ERR;
756 }
757 }
758
759 if (trigger_set)
760 devc->use_triggers = 1;
761 }
762
763 return SR_OK;
764}
765
766static int hw_dev_close(struct sr_dev_inst *sdi)
767{
768 struct dev_context *devc;
769
770 if (!(devc = sdi->priv)) {
771 sr_err("sigma: %s: sdi->priv was NULL", __func__);
772 return SR_ERR_BUG;
773 }
774
775 /* TODO */
776 if (sdi->status == SR_ST_ACTIVE)
777 ftdi_usb_close(&devc->ftdic);
778
779 sdi->status = SR_ST_INACTIVE;
780
781 return SR_OK;
782}
783
784static int hw_cleanup(void)
785{
786
787 if (!adi->priv)
788 return SR_OK;
789
790 clear_instances();
791
792 return SR_OK;
793}
794
795static int hw_info_get(int info_id, const void **data,
796 const struct sr_dev_inst *sdi)
797{
798 struct dev_context *devc;
799
800 switch (info_id) {
801 case SR_DI_HWCAPS:
802 *data = hwcaps;
803 break;
804 case SR_DI_NUM_PROBES:
805 *data = GINT_TO_POINTER(NUM_PROBES);
806 break;
807 case SR_DI_PROBE_NAMES:
808 *data = probe_names;
809 break;
810 case SR_DI_SAMPLERATES:
811 *data = &samplerates;
812 break;
813 case SR_DI_TRIGGER_TYPES:
814 *data = (char *)TRIGGER_TYPES;
815 break;
816 case SR_DI_CUR_SAMPLERATE:
817 if (sdi) {
818 devc = sdi->priv;
819 *data = &devc->cur_samplerate;
820 } else
821 return SR_ERR;
822 break;
823 default:
824 return SR_ERR_ARG;
825 }
826
827 return SR_OK;
828}
829
830static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
831 const void *value)
832{
833 struct dev_context *devc;
834 int ret;
835
836 devc = sdi->priv;
837
838 if (hwcap == SR_HWCAP_SAMPLERATE) {
839 ret = set_samplerate(sdi, *(const uint64_t *)value);
840 } else if (hwcap == SR_HWCAP_PROBECONFIG) {
841 ret = configure_probes(sdi, value);
842 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
843 devc->limit_msec = *(const uint64_t *)value;
844 if (devc->limit_msec > 0)
845 ret = SR_OK;
846 else
847 ret = SR_ERR;
848 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
849 devc->capture_ratio = *(const uint64_t *)value;
850 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
851 ret = SR_ERR;
852 else
853 ret = SR_OK;
854 } else {
855 ret = SR_ERR;
856 }
857
858 return ret;
859}
860
861/* Software trigger to determine exact trigger position. */
862static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
863 struct sigma_trigger *t)
864{
865 int i;
866
867 for (i = 0; i < 8; ++i) {
868 if (i > 0)
869 last_sample = samples[i-1];
870
871 /* Simple triggers. */
872 if ((samples[i] & t->simplemask) != t->simplevalue)
873 continue;
874
875 /* Rising edge. */
876 if ((last_sample & t->risingmask) != 0 || (samples[i] &
877 t->risingmask) != t->risingmask)
878 continue;
879
880 /* Falling edge. */
881 if ((last_sample & t->fallingmask) != t->fallingmask ||
882 (samples[i] & t->fallingmask) != 0)
883 continue;
884
885 break;
886 }
887
888 /* If we did not match, return original trigger pos. */
889 return i & 0x7;
890}
891
892/*
893 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
894 * Each event is 20ns apart, and can contain multiple samples.
895 *
896 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
897 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
898 * For 50 MHz and below, events contain one sample for each channel,
899 * spread 20 ns apart.
900 */
901static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
902 uint16_t *lastsample, int triggerpos,
903 uint16_t limit_chunk, void *cb_data)
904{
905 struct sr_dev_inst *sdi = cb_data;
906 struct dev_context *devc = sdi->priv;
907 uint16_t tsdiff, ts;
908 uint16_t samples[65536 * devc->samples_per_event];
909 struct sr_datafeed_packet packet;
910 struct sr_datafeed_logic logic;
911 int i, j, k, l, numpad, tosend;
912 size_t n = 0, sent = 0;
913 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
914 uint16_t *event;
915 uint16_t cur_sample;
916 int triggerts = -1;
917
918 /* Check if trigger is in this chunk. */
919 if (triggerpos != -1) {
920 if (devc->cur_samplerate <= SR_MHZ(50))
921 triggerpos -= EVENTS_PER_CLUSTER - 1;
922
923 if (triggerpos < 0)
924 triggerpos = 0;
925
926 /* Find in which cluster the trigger occured. */
927 triggerts = triggerpos / 7;
928 }
929
930 /* For each ts. */
931 for (i = 0; i < 64; ++i) {
932 ts = *(uint16_t *) &buf[i * 16];
933 tsdiff = ts - *lastts;
934 *lastts = ts;
935
936 /* Decode partial chunk. */
937 if (limit_chunk && ts > limit_chunk)
938 return SR_OK;
939
940 /* Pad last sample up to current point. */
941 numpad = tsdiff * devc->samples_per_event - clustersize;
942 if (numpad > 0) {
943 for (j = 0; j < numpad; ++j)
944 samples[j] = *lastsample;
945
946 n = numpad;
947 }
948
949 /* Send samples between previous and this timestamp to sigrok. */
950 sent = 0;
951 while (sent < n) {
952 tosend = MIN(2048, n - sent);
953
954 packet.type = SR_DF_LOGIC;
955 packet.payload = &logic;
956 logic.length = tosend * sizeof(uint16_t);
957 logic.unitsize = 2;
958 logic.data = samples + sent;
959 sr_session_send(devc->session_dev_id, &packet);
960
961 sent += tosend;
962 }
963 n = 0;
964
965 event = (uint16_t *) &buf[i * 16 + 2];
966 cur_sample = 0;
967
968 /* For each event in cluster. */
969 for (j = 0; j < 7; ++j) {
970
971 /* For each sample in event. */
972 for (k = 0; k < devc->samples_per_event; ++k) {
973 cur_sample = 0;
974
975 /* For each probe. */
976 for (l = 0; l < devc->num_probes; ++l)
977 cur_sample |= (!!(event[j] & (1 << (l *
978 devc->samples_per_event + k)))) << l;
979
980 samples[n++] = cur_sample;
981 }
982 }
983
984 /* Send data up to trigger point (if triggered). */
985 sent = 0;
986 if (i == triggerts) {
987 /*
988 * Trigger is not always accurate to sample because of
989 * pipeline delay. However, it always triggers before
990 * the actual event. We therefore look at the next
991 * samples to pinpoint the exact position of the trigger.
992 */
993 tosend = get_trigger_offset(samples, *lastsample,
994 &devc->trigger);
995
996 if (tosend > 0) {
997 packet.type = SR_DF_LOGIC;
998 packet.payload = &logic;
999 logic.length = tosend * sizeof(uint16_t);
1000 logic.unitsize = 2;
1001 logic.data = samples;
1002 sr_session_send(devc->session_dev_id, &packet);
1003
1004 sent += tosend;
1005 }
1006
1007 /* Only send trigger if explicitly enabled. */
1008 if (devc->use_triggers) {
1009 packet.type = SR_DF_TRIGGER;
1010 sr_session_send(devc->session_dev_id, &packet);
1011 }
1012 }
1013
1014 /* Send rest of the chunk to sigrok. */
1015 tosend = n - sent;
1016
1017 if (tosend > 0) {
1018 packet.type = SR_DF_LOGIC;
1019 packet.payload = &logic;
1020 logic.length = tosend * sizeof(uint16_t);
1021 logic.unitsize = 2;
1022 logic.data = samples + sent;
1023 sr_session_send(devc->session_dev_id, &packet);
1024 }
1025
1026 *lastsample = samples[n - 1];
1027 }
1028
1029 return SR_OK;
1030}
1031
1032static int receive_data(int fd, int revents, void *cb_data)
1033{
1034 struct sr_dev_inst *sdi = cb_data;
1035 struct dev_context *devc = sdi->priv;
1036 struct sr_datafeed_packet packet;
1037 const int chunks_per_read = 32;
1038 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1039 int bufsz, numchunks, i, newchunks;
1040 uint64_t running_msec;
1041 struct timeval tv;
1042
1043 /* Avoid compiler warnings. */
1044 (void)fd;
1045 (void)revents;
1046
1047 /* Get the current position. */
1048 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1049
1050 numchunks = (devc->state.stoppos + 511) / 512;
1051
1052 if (devc->state.state == SIGMA_IDLE)
1053 return TRUE;
1054
1055 if (devc->state.state == SIGMA_CAPTURE) {
1056 /* Check if the timer has expired, or memory is full. */
1057 gettimeofday(&tv, 0);
1058 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1059 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1060
1061 if (running_msec < devc->limit_msec && numchunks < 32767)
1062 return TRUE; /* While capturing... */
1063 else
1064 hw_dev_acquisition_stop(sdi, sdi);
1065
1066 } else if (devc->state.state == SIGMA_DOWNLOAD) {
1067 if (devc->state.chunks_downloaded >= numchunks) {
1068 /* End of samples. */
1069 packet.type = SR_DF_END;
1070 sr_session_send(devc->session_dev_id, &packet);
1071
1072 devc->state.state = SIGMA_IDLE;
1073
1074 return TRUE;
1075 }
1076
1077 newchunks = MIN(chunks_per_read,
1078 numchunks - devc->state.chunks_downloaded);
1079
1080 sr_info("sigma: Downloading sample data: %.0f %%",
1081 100.0 * devc->state.chunks_downloaded / numchunks);
1082
1083 bufsz = sigma_read_dram(devc->state.chunks_downloaded,
1084 newchunks, buf, devc);
1085 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1086 (void)bufsz;
1087
1088 /* Find first ts. */
1089 if (devc->state.chunks_downloaded == 0) {
1090 devc->state.lastts = *(uint16_t *) buf - 1;
1091 devc->state.lastsample = 0;
1092 }
1093
1094 /* Decode chunks and send them to sigrok. */
1095 for (i = 0; i < newchunks; ++i) {
1096 int limit_chunk = 0;
1097
1098 /* The last chunk may potentially be only in part. */
1099 if (devc->state.chunks_downloaded == numchunks - 1) {
1100 /* Find the last valid timestamp */
1101 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1102 }
1103
1104 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1105 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1106 &devc->state.lastts,
1107 &devc->state.lastsample,
1108 devc->state.triggerpos & 0x1ff,
1109 limit_chunk, sdi);
1110 else
1111 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1112 &devc->state.lastts,
1113 &devc->state.lastsample,
1114 -1, limit_chunk, sdi);
1115
1116 ++devc->state.chunks_downloaded;
1117 }
1118 }
1119
1120 return TRUE;
1121}
1122
1123/* Build a LUT entry used by the trigger functions. */
1124static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1125{
1126 int i, j, k, bit;
1127
1128 /* For each quad probe. */
1129 for (i = 0; i < 4; ++i) {
1130 entry[i] = 0xffff;
1131
1132 /* For each bit in LUT. */
1133 for (j = 0; j < 16; ++j)
1134
1135 /* For each probe in quad. */
1136 for (k = 0; k < 4; ++k) {
1137 bit = 1 << (i * 4 + k);
1138
1139 /* Set bit in entry */
1140 if ((mask & bit) &&
1141 ((!(value & bit)) !=
1142 (!(j & (1 << k)))))
1143 entry[i] &= ~(1 << j);
1144 }
1145 }
1146}
1147
1148/* Add a logical function to LUT mask. */
1149static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1150 int index, int neg, uint16_t *mask)
1151{
1152 int i, j;
1153 int x[2][2], tmp, a, b, aset, bset, rset;
1154
1155 memset(x, 0, 4 * sizeof(int));
1156
1157 /* Trigger detect condition. */
1158 switch (oper) {
1159 case OP_LEVEL:
1160 x[0][1] = 1;
1161 x[1][1] = 1;
1162 break;
1163 case OP_NOT:
1164 x[0][0] = 1;
1165 x[1][0] = 1;
1166 break;
1167 case OP_RISE:
1168 x[0][1] = 1;
1169 break;
1170 case OP_FALL:
1171 x[1][0] = 1;
1172 break;
1173 case OP_RISEFALL:
1174 x[0][1] = 1;
1175 x[1][0] = 1;
1176 break;
1177 case OP_NOTRISE:
1178 x[1][1] = 1;
1179 x[0][0] = 1;
1180 x[1][0] = 1;
1181 break;
1182 case OP_NOTFALL:
1183 x[1][1] = 1;
1184 x[0][0] = 1;
1185 x[0][1] = 1;
1186 break;
1187 case OP_NOTRISEFALL:
1188 x[1][1] = 1;
1189 x[0][0] = 1;
1190 break;
1191 }
1192
1193 /* Transpose if neg is set. */
1194 if (neg) {
1195 for (i = 0; i < 2; ++i) {
1196 for (j = 0; j < 2; ++j) {
1197 tmp = x[i][j];
1198 x[i][j] = x[1-i][1-j];
1199 x[1-i][1-j] = tmp;
1200 }
1201 }
1202 }
1203
1204 /* Update mask with function. */
1205 for (i = 0; i < 16; ++i) {
1206 a = (i >> (2 * index + 0)) & 1;
1207 b = (i >> (2 * index + 1)) & 1;
1208
1209 aset = (*mask >> i) & 1;
1210 bset = x[b][a];
1211
1212 if (func == FUNC_AND || func == FUNC_NAND)
1213 rset = aset & bset;
1214 else if (func == FUNC_OR || func == FUNC_NOR)
1215 rset = aset | bset;
1216 else if (func == FUNC_XOR || func == FUNC_NXOR)
1217 rset = aset ^ bset;
1218
1219 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1220 rset = !rset;
1221
1222 *mask &= ~(1 << i);
1223
1224 if (rset)
1225 *mask |= 1 << i;
1226 }
1227}
1228
1229/*
1230 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1231 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1232 * set at any time, but a full mask and value can be set (0/1).
1233 */
1234static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1235{
1236 int i,j;
1237 uint16_t masks[2] = { 0, 0 };
1238
1239 memset(lut, 0, sizeof(struct triggerlut));
1240
1241 /* Contant for simple triggers. */
1242 lut->m4 = 0xa000;
1243
1244 /* Value/mask trigger support. */
1245 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1246 lut->m2d);
1247
1248 /* Rise/fall trigger support. */
1249 for (i = 0, j = 0; i < 16; ++i) {
1250 if (devc->trigger.risingmask & (1 << i) ||
1251 devc->trigger.fallingmask & (1 << i))
1252 masks[j++] = 1 << i;
1253 }
1254
1255 build_lut_entry(masks[0], masks[0], lut->m0d);
1256 build_lut_entry(masks[1], masks[1], lut->m1d);
1257
1258 /* Add glue logic */
1259 if (masks[0] || masks[1]) {
1260 /* Transition trigger. */
1261 if (masks[0] & devc->trigger.risingmask)
1262 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1263 if (masks[0] & devc->trigger.fallingmask)
1264 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1265 if (masks[1] & devc->trigger.risingmask)
1266 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1267 if (masks[1] & devc->trigger.fallingmask)
1268 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1269 } else {
1270 /* Only value/mask trigger. */
1271 lut->m3 = 0xffff;
1272 }
1273
1274 /* Triggertype: event. */
1275 lut->params.selres = 3;
1276
1277 return SR_OK;
1278}
1279
1280static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
1281 void *cb_data)
1282{
1283 struct dev_context *devc;
1284 struct sr_datafeed_packet *packet;
1285 struct sr_datafeed_header *header;
1286 struct sr_datafeed_meta_logic meta;
1287 struct clockselect_50 clockselect;
1288 int frac, triggerpin, ret;
1289 uint8_t triggerselect;
1290 struct triggerinout triggerinout_conf;
1291 struct triggerlut lut;
1292
1293 devc = sdi->priv;
1294
1295 /* If the samplerate has not been set, default to 200 kHz. */
1296 if (devc->cur_firmware == -1) {
1297 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1298 return ret;
1299 }
1300
1301 /* Enter trigger programming mode. */
1302 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1303
1304 /* 100 and 200 MHz mode. */
1305 if (devc->cur_samplerate >= SR_MHZ(100)) {
1306 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1307
1308 /* Find which pin to trigger on from mask. */
1309 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1310 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1311 (1 << triggerpin))
1312 break;
1313
1314 /* Set trigger pin and light LED on trigger. */
1315 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1316
1317 /* Default rising edge. */
1318 if (devc->trigger.fallingmask)
1319 triggerselect |= 1 << 3;
1320
1321 /* All other modes. */
1322 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1323 build_basic_trigger(&lut, devc);
1324
1325 sigma_write_trigger_lut(&lut, devc);
1326
1327 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1328 }
1329
1330 /* Setup trigger in and out pins to default values. */
1331 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1332 triggerinout_conf.trgout_bytrigger = 1;
1333 triggerinout_conf.trgout_enable = 1;
1334
1335 sigma_write_register(WRITE_TRIGGER_OPTION,
1336 (uint8_t *) &triggerinout_conf,
1337 sizeof(struct triggerinout), devc);
1338
1339 /* Go back to normal mode. */
1340 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1341
1342 /* Set clock select register. */
1343 if (devc->cur_samplerate == SR_MHZ(200))
1344 /* Enable 4 probes. */
1345 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1346 else if (devc->cur_samplerate == SR_MHZ(100))
1347 /* Enable 8 probes. */
1348 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1349 else {
1350 /*
1351 * 50 MHz mode (or fraction thereof). Any fraction down to
1352 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1353 */
1354 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1355
1356 clockselect.async = 0;
1357 clockselect.fraction = frac;
1358 clockselect.disabled_probes = 0;
1359
1360 sigma_write_register(WRITE_CLOCK_SELECT,
1361 (uint8_t *) &clockselect,
1362 sizeof(clockselect), devc);
1363 }
1364
1365 /* Setup maximum post trigger time. */
1366 sigma_set_register(WRITE_POST_TRIGGER,
1367 (devc->capture_ratio * 255) / 100, devc);
1368
1369 /* Start acqusition. */
1370 gettimeofday(&devc->start_tv, 0);
1371 sigma_set_register(WRITE_MODE, 0x0d, devc);
1372
1373 devc->session_dev_id = cb_data;
1374
1375 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1376 sr_err("sigma: %s: packet malloc failed.", __func__);
1377 return SR_ERR_MALLOC;
1378 }
1379
1380 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1381 sr_err("sigma: %s: header malloc failed.", __func__);
1382 return SR_ERR_MALLOC;
1383 }
1384
1385 /* Send header packet to the session bus. */
1386 packet->type = SR_DF_HEADER;
1387 packet->payload = header;
1388 header->feed_version = 1;
1389 gettimeofday(&header->starttime, NULL);
1390 sr_session_send(devc->session_dev_id, packet);
1391
1392 /* Send metadata about the SR_DF_LOGIC packets to come. */
1393 packet->type = SR_DF_META_LOGIC;
1394 packet->payload = &meta;
1395 meta.samplerate = devc->cur_samplerate;
1396 meta.num_probes = devc->num_probes;
1397 sr_session_send(devc->session_dev_id, packet);
1398
1399 /* Add capture source. */
1400 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1401
1402 g_free(header);
1403 g_free(packet);
1404
1405 devc->state.state = SIGMA_CAPTURE;
1406
1407 return SR_OK;
1408}
1409
1410static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi,
1411 void *cb_data)
1412{
1413 struct dev_context *devc;
1414 uint8_t modestatus;
1415
1416 /* Avoid compiler warnings. */
1417 (void)cb_data;
1418
1419 sr_source_remove(0);
1420
1421 if (!(devc = sdi->priv)) {
1422 sr_err("sigma: %s: sdi->priv was NULL", __func__);
1423 return SR_ERR_BUG;
1424 }
1425
1426 /* Stop acquisition. */
1427 sigma_set_register(WRITE_MODE, 0x11, devc);
1428
1429 /* Set SDRAM Read Enable. */
1430 sigma_set_register(WRITE_MODE, 0x02, devc);
1431
1432 /* Get the current position. */
1433 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1434
1435 /* Check if trigger has fired. */
1436 modestatus = sigma_get_register(READ_MODE, devc);
1437 if (modestatus & 0x20)
1438 devc->state.triggerchunk = devc->state.triggerpos / 512;
1439 else
1440 devc->state.triggerchunk = -1;
1441
1442 devc->state.chunks_downloaded = 0;
1443
1444 devc->state.state = SIGMA_DOWNLOAD;
1445
1446 return SR_OK;
1447}
1448
1449SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1450 .name = "asix-sigma",
1451 .longname = "ASIX SIGMA/SIGMA2",
1452 .api_version = 1,
1453 .init = hw_init,
1454 .cleanup = hw_cleanup,
1455 .scan = hw_scan,
1456 .dev_open = hw_dev_open,
1457 .dev_close = hw_dev_close,
1458 .info_get = hw_info_get,
1459 .dev_config_set = hw_dev_config_set,
1460 .dev_acquisition_start = hw_dev_acquisition_start,
1461 .dev_acquisition_stop = hw_dev_acquisition_stop,
1462 .priv = NULL,
1463};
Hardware access and backend lib