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1 | /* | |
2 | * This file is part of the sigrok project. | |
3 | * | |
4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, | |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * ASIX SIGMA/SIGMA2 logic analyzer driver | |
24 | */ | |
25 | ||
26 | #include <glib.h> | |
27 | #include <glib/gstdio.h> | |
28 | #include <ftdi.h> | |
29 | #include <string.h> | |
30 | #include "libsigrok.h" | |
31 | #include "libsigrok-internal.h" | |
32 | #include "asix-sigma.h" | |
33 | ||
34 | #define USB_VENDOR 0xa600 | |
35 | #define USB_PRODUCT 0xa000 | |
36 | #define USB_DESCRIPTION "ASIX SIGMA" | |
37 | #define USB_VENDOR_NAME "ASIX" | |
38 | #define USB_MODEL_NAME "SIGMA" | |
39 | #define USB_MODEL_VERSION "" | |
40 | #define TRIGGER_TYPES "rf10" | |
41 | #define NUM_PROBES 16 | |
42 | ||
43 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; | |
44 | static struct sr_dev_driver *di = &asix_sigma_driver_info; | |
45 | static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data); | |
46 | ||
47 | static const uint64_t supported_samplerates[] = { | |
48 | SR_KHZ(200), | |
49 | SR_KHZ(250), | |
50 | SR_KHZ(500), | |
51 | SR_MHZ(1), | |
52 | SR_MHZ(5), | |
53 | SR_MHZ(10), | |
54 | SR_MHZ(25), | |
55 | SR_MHZ(50), | |
56 | SR_MHZ(100), | |
57 | SR_MHZ(200), | |
58 | 0, | |
59 | }; | |
60 | ||
61 | /* | |
62 | * Probe numbers seem to go from 1-16, according to this image: | |
63 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg | |
64 | * (the cable has two additional GND pins, and a TI and TO pin) | |
65 | */ | |
66 | static const char *probe_names[NUM_PROBES + 1] = { | |
67 | "1", "2", "3", "4", "5", "6", "7", "8", | |
68 | "9", "10", "11", "12", "13", "14", "15", "16", | |
69 | NULL, | |
70 | }; | |
71 | ||
72 | static const struct sr_samplerates samplerates = { | |
73 | 0, | |
74 | 0, | |
75 | 0, | |
76 | supported_samplerates, | |
77 | }; | |
78 | ||
79 | static const int hwcaps[] = { | |
80 | SR_CONF_LOGIC_ANALYZER, | |
81 | SR_CONF_SAMPLERATE, | |
82 | SR_CONF_CAPTURE_RATIO, | |
83 | ||
84 | SR_CONF_LIMIT_MSEC, | |
85 | 0, | |
86 | }; | |
87 | ||
88 | /* Force the FPGA to reboot. */ | |
89 | static uint8_t suicide[] = { | |
90 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
91 | }; | |
92 | ||
93 | /* Prepare to upload firmware (FPGA specific). */ | |
94 | static uint8_t init[] = { | |
95 | 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, | |
96 | }; | |
97 | ||
98 | /* Initialize the logic analyzer mode. */ | |
99 | static uint8_t logic_mode_start[] = { | |
100 | 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40, | |
101 | 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38, | |
102 | }; | |
103 | ||
104 | static const char *firmware_files[] = { | |
105 | "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */ | |
106 | "asix-sigma-100.fw", /* 100 MHz */ | |
107 | "asix-sigma-200.fw", /* 200 MHz */ | |
108 | "asix-sigma-50sync.fw", /* Synchronous clock from pin */ | |
109 | "asix-sigma-phasor.fw", /* Frequency counter */ | |
110 | }; | |
111 | ||
112 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) | |
113 | { | |
114 | int ret; | |
115 | ||
116 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); | |
117 | if (ret < 0) { | |
118 | sr_err("ftdi_read_data failed: %s", | |
119 | ftdi_get_error_string(&devc->ftdic)); | |
120 | } | |
121 | ||
122 | return ret; | |
123 | } | |
124 | ||
125 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) | |
126 | { | |
127 | int ret; | |
128 | ||
129 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); | |
130 | if (ret < 0) { | |
131 | sr_err("ftdi_write_data failed: %s", | |
132 | ftdi_get_error_string(&devc->ftdic)); | |
133 | } else if ((size_t) ret != size) { | |
134 | sr_err("ftdi_write_data did not complete write."); | |
135 | } | |
136 | ||
137 | return ret; | |
138 | } | |
139 | ||
140 | static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, | |
141 | struct dev_context *devc) | |
142 | { | |
143 | size_t i; | |
144 | uint8_t buf[len + 2]; | |
145 | int idx = 0; | |
146 | ||
147 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
148 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
149 | ||
150 | for (i = 0; i < len; ++i) { | |
151 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); | |
152 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
153 | } | |
154 | ||
155 | return sigma_write(buf, idx, devc); | |
156 | } | |
157 | ||
158 | static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) | |
159 | { | |
160 | return sigma_write_register(reg, &value, 1, devc); | |
161 | } | |
162 | ||
163 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, | |
164 | struct dev_context *devc) | |
165 | { | |
166 | uint8_t buf[3]; | |
167 | ||
168 | buf[0] = REG_ADDR_LOW | (reg & 0xf); | |
169 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
170 | buf[2] = REG_READ_ADDR; | |
171 | ||
172 | sigma_write(buf, sizeof(buf), devc); | |
173 | ||
174 | return sigma_read(data, len, devc); | |
175 | } | |
176 | ||
177 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) | |
178 | { | |
179 | uint8_t value; | |
180 | ||
181 | if (1 != sigma_read_register(reg, &value, 1, devc)) { | |
182 | sr_err("sigma_get_register: 1 byte expected"); | |
183 | return 0; | |
184 | } | |
185 | ||
186 | return value; | |
187 | } | |
188 | ||
189 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, | |
190 | struct dev_context *devc) | |
191 | { | |
192 | uint8_t buf[] = { | |
193 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
194 | ||
195 | REG_READ_ADDR | NEXT_REG, | |
196 | REG_READ_ADDR | NEXT_REG, | |
197 | REG_READ_ADDR | NEXT_REG, | |
198 | REG_READ_ADDR | NEXT_REG, | |
199 | REG_READ_ADDR | NEXT_REG, | |
200 | REG_READ_ADDR | NEXT_REG, | |
201 | }; | |
202 | uint8_t result[6]; | |
203 | ||
204 | sigma_write(buf, sizeof(buf), devc); | |
205 | ||
206 | sigma_read(result, sizeof(result), devc); | |
207 | ||
208 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
209 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
210 | ||
211 | /* Not really sure why this must be done, but according to spec. */ | |
212 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
213 | stoppos -= 64; | |
214 | ||
215 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
216 | triggerpos -= 64; | |
217 | ||
218 | return 1; | |
219 | } | |
220 | ||
221 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, | |
222 | uint8_t *data, struct dev_context *devc) | |
223 | { | |
224 | size_t i; | |
225 | uint8_t buf[4096]; | |
226 | int idx = 0; | |
227 | ||
228 | /* Send the startchunk. Index start with 1. */ | |
229 | buf[0] = startchunk >> 8; | |
230 | buf[1] = startchunk & 0xff; | |
231 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); | |
232 | ||
233 | /* Read the DRAM. */ | |
234 | buf[idx++] = REG_DRAM_BLOCK; | |
235 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
236 | ||
237 | for (i = 0; i < numchunks; ++i) { | |
238 | /* Alternate bit to copy from DRAM to cache. */ | |
239 | if (i != (numchunks - 1)) | |
240 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
241 | ||
242 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
243 | ||
244 | if (i != (numchunks - 1)) | |
245 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
246 | } | |
247 | ||
248 | sigma_write(buf, idx, devc); | |
249 | ||
250 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); | |
251 | } | |
252 | ||
253 | /* Upload trigger look-up tables to Sigma. */ | |
254 | static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) | |
255 | { | |
256 | int i; | |
257 | uint8_t tmp[2]; | |
258 | uint16_t bit; | |
259 | ||
260 | /* Transpose the table and send to Sigma. */ | |
261 | for (i = 0; i < 16; ++i) { | |
262 | bit = 1 << i; | |
263 | ||
264 | tmp[0] = tmp[1] = 0; | |
265 | ||
266 | if (lut->m2d[0] & bit) | |
267 | tmp[0] |= 0x01; | |
268 | if (lut->m2d[1] & bit) | |
269 | tmp[0] |= 0x02; | |
270 | if (lut->m2d[2] & bit) | |
271 | tmp[0] |= 0x04; | |
272 | if (lut->m2d[3] & bit) | |
273 | tmp[0] |= 0x08; | |
274 | ||
275 | if (lut->m3 & bit) | |
276 | tmp[0] |= 0x10; | |
277 | if (lut->m3s & bit) | |
278 | tmp[0] |= 0x20; | |
279 | if (lut->m4 & bit) | |
280 | tmp[0] |= 0x40; | |
281 | ||
282 | if (lut->m0d[0] & bit) | |
283 | tmp[1] |= 0x01; | |
284 | if (lut->m0d[1] & bit) | |
285 | tmp[1] |= 0x02; | |
286 | if (lut->m0d[2] & bit) | |
287 | tmp[1] |= 0x04; | |
288 | if (lut->m0d[3] & bit) | |
289 | tmp[1] |= 0x08; | |
290 | ||
291 | if (lut->m1d[0] & bit) | |
292 | tmp[1] |= 0x10; | |
293 | if (lut->m1d[1] & bit) | |
294 | tmp[1] |= 0x20; | |
295 | if (lut->m1d[2] & bit) | |
296 | tmp[1] |= 0x40; | |
297 | if (lut->m1d[3] & bit) | |
298 | tmp[1] |= 0x80; | |
299 | ||
300 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), | |
301 | devc); | |
302 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
303 | } | |
304 | ||
305 | /* Send the parameters */ | |
306 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
307 | sizeof(lut->params), devc); | |
308 | ||
309 | return SR_OK; | |
310 | } | |
311 | ||
312 | /* Generate the bitbang stream for programming the FPGA. */ | |
313 | static int bin2bitbang(const char *filename, | |
314 | unsigned char **buf, size_t *buf_size) | |
315 | { | |
316 | FILE *f; | |
317 | unsigned long file_size; | |
318 | unsigned long offset = 0; | |
319 | unsigned char *p; | |
320 | uint8_t *firmware; | |
321 | unsigned long fwsize = 0; | |
322 | const int buffer_size = 65536; | |
323 | size_t i; | |
324 | int c, bit, v; | |
325 | uint32_t imm = 0x3f6df2ab; | |
326 | ||
327 | f = g_fopen(filename, "rb"); | |
328 | if (!f) { | |
329 | sr_err("g_fopen(\"%s\", \"rb\")", filename); | |
330 | return SR_ERR; | |
331 | } | |
332 | ||
333 | if (-1 == fseek(f, 0, SEEK_END)) { | |
334 | sr_err("fseek on %s failed", filename); | |
335 | fclose(f); | |
336 | return SR_ERR; | |
337 | } | |
338 | ||
339 | file_size = ftell(f); | |
340 | ||
341 | fseek(f, 0, SEEK_SET); | |
342 | ||
343 | if (!(firmware = g_try_malloc(buffer_size))) { | |
344 | sr_err("%s: firmware malloc failed", __func__); | |
345 | fclose(f); | |
346 | return SR_ERR_MALLOC; | |
347 | } | |
348 | ||
349 | while ((c = getc(f)) != EOF) { | |
350 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
351 | firmware[fwsize++] = c ^ imm; | |
352 | } | |
353 | fclose(f); | |
354 | ||
355 | if(fwsize != file_size) { | |
356 | sr_err("%s: Error reading firmware", filename); | |
357 | fclose(f); | |
358 | g_free(firmware); | |
359 | return SR_ERR; | |
360 | } | |
361 | ||
362 | *buf_size = fwsize * 2 * 8; | |
363 | ||
364 | *buf = p = (unsigned char *)g_try_malloc(*buf_size); | |
365 | if (!p) { | |
366 | sr_err("%s: buf/p malloc failed", __func__); | |
367 | g_free(firmware); | |
368 | return SR_ERR_MALLOC; | |
369 | } | |
370 | ||
371 | for (i = 0; i < fwsize; ++i) { | |
372 | for (bit = 7; bit >= 0; --bit) { | |
373 | v = firmware[i] & 1 << bit ? 0x40 : 0x00; | |
374 | p[offset++] = v | 0x01; | |
375 | p[offset++] = v; | |
376 | } | |
377 | } | |
378 | ||
379 | g_free(firmware); | |
380 | ||
381 | if (offset != *buf_size) { | |
382 | g_free(*buf); | |
383 | sr_err("Error reading firmware %s " | |
384 | "offset=%ld, file_size=%ld, buf_size=%zd.", | |
385 | filename, offset, file_size, *buf_size); | |
386 | ||
387 | return SR_ERR; | |
388 | } | |
389 | ||
390 | return SR_OK; | |
391 | } | |
392 | ||
393 | static int clear_instances(void) | |
394 | { | |
395 | GSList *l; | |
396 | struct sr_dev_inst *sdi; | |
397 | struct drv_context *drvc; | |
398 | struct dev_context *devc; | |
399 | ||
400 | drvc = di->priv; | |
401 | ||
402 | /* Properly close all devices. */ | |
403 | for (l = drvc->instances; l; l = l->next) { | |
404 | if (!(sdi = l->data)) { | |
405 | /* Log error, but continue cleaning up the rest. */ | |
406 | sr_err("%s: sdi was NULL, continuing", __func__); | |
407 | continue; | |
408 | } | |
409 | if (sdi->priv) { | |
410 | devc = sdi->priv; | |
411 | ftdi_free(&devc->ftdic); | |
412 | } | |
413 | sr_dev_inst_free(sdi); | |
414 | } | |
415 | g_slist_free(drvc->instances); | |
416 | drvc->instances = NULL; | |
417 | ||
418 | return SR_OK; | |
419 | } | |
420 | ||
421 | static int hw_init(struct sr_context *sr_ctx) | |
422 | { | |
423 | struct drv_context *drvc; | |
424 | ||
425 | if (!(drvc = g_try_malloc0(sizeof(struct drv_context)))) { | |
426 | sr_err("Driver context malloc failed."); | |
427 | return SR_ERR_MALLOC; | |
428 | } | |
429 | drvc->sr_ctx = sr_ctx; | |
430 | di->priv = drvc; | |
431 | ||
432 | return SR_OK; | |
433 | } | |
434 | ||
435 | static GSList *hw_scan(GSList *options) | |
436 | { | |
437 | struct sr_dev_inst *sdi; | |
438 | struct sr_probe *probe; | |
439 | struct drv_context *drvc; | |
440 | struct dev_context *devc; | |
441 | GSList *devices; | |
442 | struct ftdi_device_list *devlist; | |
443 | char serial_txt[10]; | |
444 | uint32_t serial; | |
445 | int ret, i; | |
446 | ||
447 | (void)options; | |
448 | ||
449 | drvc = di->priv; | |
450 | devices = NULL; | |
451 | clear_instances(); | |
452 | ||
453 | if (!(devc = g_try_malloc(sizeof(struct dev_context)))) { | |
454 | sr_err("%s: devc malloc failed", __func__); | |
455 | return NULL; | |
456 | } | |
457 | ||
458 | ftdi_init(&devc->ftdic); | |
459 | ||
460 | /* Look for SIGMAs. */ | |
461 | ||
462 | if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist, | |
463 | USB_VENDOR, USB_PRODUCT)) <= 0) { | |
464 | if (ret < 0) | |
465 | sr_err("ftdi_usb_find_all(): %d", ret); | |
466 | goto free; | |
467 | } | |
468 | ||
469 | /* Make sure it's a version 1 or 2 SIGMA. */ | |
470 | ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0, | |
471 | serial_txt, sizeof(serial_txt)); | |
472 | sscanf(serial_txt, "%x", &serial); | |
473 | ||
474 | if (serial < 0xa6010000 || serial > 0xa602ffff) { | |
475 | sr_err("Only SIGMA and SIGMA2 are supported " | |
476 | "in this version of libsigrok."); | |
477 | goto free; | |
478 | } | |
479 | ||
480 | sr_info("Found ASIX SIGMA - Serial: %s", serial_txt); | |
481 | ||
482 | devc->cur_samplerate = 0; | |
483 | devc->period_ps = 0; | |
484 | devc->limit_msec = 0; | |
485 | devc->cur_firmware = -1; | |
486 | devc->num_probes = 0; | |
487 | devc->samples_per_event = 0; | |
488 | devc->capture_ratio = 50; | |
489 | devc->use_triggers = 0; | |
490 | ||
491 | /* Register SIGMA device. */ | |
492 | if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME, | |
493 | USB_MODEL_NAME, USB_MODEL_VERSION))) { | |
494 | sr_err("%s: sdi was NULL", __func__); | |
495 | goto free; | |
496 | } | |
497 | sdi->driver = di; | |
498 | ||
499 | for (i = 0; probe_names[i]; i++) { | |
500 | if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE, | |
501 | probe_names[i]))) | |
502 | return NULL; | |
503 | sdi->probes = g_slist_append(sdi->probes, probe); | |
504 | } | |
505 | ||
506 | devices = g_slist_append(devices, sdi); | |
507 | drvc->instances = g_slist_append(drvc->instances, sdi); | |
508 | sdi->priv = devc; | |
509 | ||
510 | /* We will open the device again when we need it. */ | |
511 | ftdi_list_free(&devlist); | |
512 | ||
513 | return devices; | |
514 | ||
515 | free: | |
516 | ftdi_deinit(&devc->ftdic); | |
517 | g_free(devc); | |
518 | return NULL; | |
519 | } | |
520 | ||
521 | static GSList *hw_dev_list(void) | |
522 | { | |
523 | struct drv_context *drvc; | |
524 | ||
525 | drvc = di->priv; | |
526 | ||
527 | return drvc->instances; | |
528 | } | |
529 | ||
530 | static int upload_firmware(int firmware_idx, struct dev_context *devc) | |
531 | { | |
532 | int ret; | |
533 | unsigned char *buf; | |
534 | unsigned char pins; | |
535 | size_t buf_size; | |
536 | unsigned char result[32]; | |
537 | char firmware_path[128]; | |
538 | ||
539 | /* Make sure it's an ASIX SIGMA. */ | |
540 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, | |
541 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
542 | sr_err("ftdi_usb_open failed: %s", | |
543 | ftdi_get_error_string(&devc->ftdic)); | |
544 | return 0; | |
545 | } | |
546 | ||
547 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) { | |
548 | sr_err("ftdi_set_bitmode failed: %s", | |
549 | ftdi_get_error_string(&devc->ftdic)); | |
550 | return 0; | |
551 | } | |
552 | ||
553 | /* Four times the speed of sigmalogan - Works well. */ | |
554 | if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) { | |
555 | sr_err("ftdi_set_baudrate failed: %s", | |
556 | ftdi_get_error_string(&devc->ftdic)); | |
557 | return 0; | |
558 | } | |
559 | ||
560 | /* Force the FPGA to reboot. */ | |
561 | sigma_write(suicide, sizeof(suicide), devc); | |
562 | sigma_write(suicide, sizeof(suicide), devc); | |
563 | sigma_write(suicide, sizeof(suicide), devc); | |
564 | sigma_write(suicide, sizeof(suicide), devc); | |
565 | ||
566 | /* Prepare to upload firmware (FPGA specific). */ | |
567 | sigma_write(init, sizeof(init), devc); | |
568 | ||
569 | ftdi_usb_purge_buffers(&devc->ftdic); | |
570 | ||
571 | /* Wait until the FPGA asserts INIT_B. */ | |
572 | while (1) { | |
573 | ret = sigma_read(result, 1, devc); | |
574 | if (result[0] & 0x20) | |
575 | break; | |
576 | } | |
577 | ||
578 | /* Prepare firmware. */ | |
579 | snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR, | |
580 | firmware_files[firmware_idx]); | |
581 | ||
582 | if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) { | |
583 | sr_err("An error occured while reading the firmware: %s", | |
584 | firmware_path); | |
585 | return ret; | |
586 | } | |
587 | ||
588 | /* Upload firmare. */ | |
589 | sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]); | |
590 | sigma_write(buf, buf_size, devc); | |
591 | ||
592 | g_free(buf); | |
593 | ||
594 | if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) { | |
595 | sr_err("ftdi_set_bitmode failed: %s", | |
596 | ftdi_get_error_string(&devc->ftdic)); | |
597 | return SR_ERR; | |
598 | } | |
599 | ||
600 | ftdi_usb_purge_buffers(&devc->ftdic); | |
601 | ||
602 | /* Discard garbage. */ | |
603 | while (1 == sigma_read(&pins, 1, devc)) | |
604 | ; | |
605 | ||
606 | /* Initialize the logic analyzer mode. */ | |
607 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); | |
608 | ||
609 | /* Expect a 3 byte reply. */ | |
610 | ret = sigma_read(result, 3, devc); | |
611 | if (ret != 3 || | |
612 | result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) { | |
613 | sr_err("Configuration failed. Invalid reply received."); | |
614 | return SR_ERR; | |
615 | } | |
616 | ||
617 | devc->cur_firmware = firmware_idx; | |
618 | ||
619 | sr_info("Firmware uploaded."); | |
620 | ||
621 | return SR_OK; | |
622 | } | |
623 | ||
624 | static int hw_dev_open(struct sr_dev_inst *sdi) | |
625 | { | |
626 | struct dev_context *devc; | |
627 | int ret; | |
628 | ||
629 | devc = sdi->priv; | |
630 | ||
631 | /* Make sure it's an ASIX SIGMA. */ | |
632 | if ((ret = ftdi_usb_open_desc(&devc->ftdic, | |
633 | USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) { | |
634 | ||
635 | sr_err("ftdi_usb_open failed: %s", | |
636 | ftdi_get_error_string(&devc->ftdic)); | |
637 | ||
638 | return 0; | |
639 | } | |
640 | ||
641 | sdi->status = SR_ST_ACTIVE; | |
642 | ||
643 | return SR_OK; | |
644 | } | |
645 | ||
646 | static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) | |
647 | { | |
648 | int i, ret; | |
649 | struct dev_context *devc = sdi->priv; | |
650 | ||
651 | ret = SR_OK; | |
652 | ||
653 | for (i = 0; supported_samplerates[i]; i++) { | |
654 | if (supported_samplerates[i] == samplerate) | |
655 | break; | |
656 | } | |
657 | if (supported_samplerates[i] == 0) | |
658 | return SR_ERR_SAMPLERATE; | |
659 | ||
660 | if (samplerate <= SR_MHZ(50)) { | |
661 | ret = upload_firmware(0, devc); | |
662 | devc->num_probes = 16; | |
663 | } | |
664 | if (samplerate == SR_MHZ(100)) { | |
665 | ret = upload_firmware(1, devc); | |
666 | devc->num_probes = 8; | |
667 | } | |
668 | else if (samplerate == SR_MHZ(200)) { | |
669 | ret = upload_firmware(2, devc); | |
670 | devc->num_probes = 4; | |
671 | } | |
672 | ||
673 | devc->cur_samplerate = samplerate; | |
674 | devc->period_ps = 1000000000000ULL / samplerate; | |
675 | devc->samples_per_event = 16 / devc->num_probes; | |
676 | devc->state.state = SIGMA_IDLE; | |
677 | ||
678 | return ret; | |
679 | } | |
680 | ||
681 | /* | |
682 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
683 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
684 | * in addition to value/mask trigger for any number of probes. | |
685 | * | |
686 | * The Sigma supports complex triggers using boolean expressions, but this | |
687 | * has not been implemented yet. | |
688 | */ | |
689 | static int configure_probes(const struct sr_dev_inst *sdi) | |
690 | { | |
691 | struct dev_context *devc = sdi->priv; | |
692 | const struct sr_probe *probe; | |
693 | const GSList *l; | |
694 | int trigger_set = 0; | |
695 | int probebit; | |
696 | ||
697 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); | |
698 | ||
699 | for (l = sdi->probes; l; l = l->next) { | |
700 | probe = (struct sr_probe *)l->data; | |
701 | probebit = 1 << (probe->index); | |
702 | ||
703 | if (!probe->enabled || !probe->trigger) | |
704 | continue; | |
705 | ||
706 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
707 | /* Fast trigger support. */ | |
708 | if (trigger_set) { | |
709 | sr_err("Only a single pin trigger in 100 and " | |
710 | "200MHz mode is supported."); | |
711 | return SR_ERR; | |
712 | } | |
713 | if (probe->trigger[0] == 'f') | |
714 | devc->trigger.fallingmask |= probebit; | |
715 | else if (probe->trigger[0] == 'r') | |
716 | devc->trigger.risingmask |= probebit; | |
717 | else { | |
718 | sr_err("Only rising/falling trigger in 100 " | |
719 | "and 200MHz mode is supported."); | |
720 | return SR_ERR; | |
721 | } | |
722 | ||
723 | ++trigger_set; | |
724 | } else { | |
725 | /* Simple trigger support (event). */ | |
726 | if (probe->trigger[0] == '1') { | |
727 | devc->trigger.simplevalue |= probebit; | |
728 | devc->trigger.simplemask |= probebit; | |
729 | } | |
730 | else if (probe->trigger[0] == '0') { | |
731 | devc->trigger.simplevalue &= ~probebit; | |
732 | devc->trigger.simplemask |= probebit; | |
733 | } | |
734 | else if (probe->trigger[0] == 'f') { | |
735 | devc->trigger.fallingmask |= probebit; | |
736 | ++trigger_set; | |
737 | } | |
738 | else if (probe->trigger[0] == 'r') { | |
739 | devc->trigger.risingmask |= probebit; | |
740 | ++trigger_set; | |
741 | } | |
742 | ||
743 | /* | |
744 | * Actually, Sigma supports 2 rising/falling triggers, | |
745 | * but they are ORed and the current trigger syntax | |
746 | * does not permit ORed triggers. | |
747 | */ | |
748 | if (trigger_set > 1) { | |
749 | sr_err("Only 1 rising/falling trigger " | |
750 | "is supported."); | |
751 | return SR_ERR; | |
752 | } | |
753 | } | |
754 | ||
755 | if (trigger_set) | |
756 | devc->use_triggers = 1; | |
757 | } | |
758 | ||
759 | return SR_OK; | |
760 | } | |
761 | ||
762 | static int hw_dev_close(struct sr_dev_inst *sdi) | |
763 | { | |
764 | struct dev_context *devc; | |
765 | ||
766 | if (!(devc = sdi->priv)) { | |
767 | sr_err("%s: sdi->priv was NULL", __func__); | |
768 | return SR_ERR_BUG; | |
769 | } | |
770 | ||
771 | /* TODO */ | |
772 | if (sdi->status == SR_ST_ACTIVE) | |
773 | ftdi_usb_close(&devc->ftdic); | |
774 | ||
775 | sdi->status = SR_ST_INACTIVE; | |
776 | ||
777 | return SR_OK; | |
778 | } | |
779 | ||
780 | static int hw_cleanup(void) | |
781 | { | |
782 | if (!di->priv) | |
783 | return SR_OK; | |
784 | ||
785 | clear_instances(); | |
786 | ||
787 | return SR_OK; | |
788 | } | |
789 | ||
790 | static int config_get(int id, const void **data, const struct sr_dev_inst *sdi) | |
791 | { | |
792 | struct dev_context *devc; | |
793 | ||
794 | switch (id) { | |
795 | case SR_DI_HWCAPS: | |
796 | *data = hwcaps; | |
797 | break; | |
798 | case SR_DI_SAMPLERATES: | |
799 | *data = &samplerates; | |
800 | break; | |
801 | case SR_DI_TRIGGER_TYPES: | |
802 | *data = (char *)TRIGGER_TYPES; | |
803 | break; | |
804 | case SR_DI_CUR_SAMPLERATE: | |
805 | if (sdi) { | |
806 | devc = sdi->priv; | |
807 | *data = &devc->cur_samplerate; | |
808 | } else | |
809 | return SR_ERR; | |
810 | break; | |
811 | default: | |
812 | return SR_ERR_ARG; | |
813 | } | |
814 | ||
815 | return SR_OK; | |
816 | } | |
817 | ||
818 | static int config_set(int id, const void *value, const struct sr_dev_inst *sdi) | |
819 | { | |
820 | struct dev_context *devc; | |
821 | int ret; | |
822 | ||
823 | devc = sdi->priv; | |
824 | ||
825 | if (id == SR_CONF_SAMPLERATE) { | |
826 | ret = set_samplerate(sdi, *(const uint64_t *)value); | |
827 | } else if (id == SR_CONF_LIMIT_MSEC) { | |
828 | devc->limit_msec = *(const uint64_t *)value; | |
829 | if (devc->limit_msec > 0) | |
830 | ret = SR_OK; | |
831 | else | |
832 | ret = SR_ERR; | |
833 | } else if (id == SR_CONF_CAPTURE_RATIO) { | |
834 | devc->capture_ratio = *(const uint64_t *)value; | |
835 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) | |
836 | ret = SR_ERR; | |
837 | else | |
838 | ret = SR_OK; | |
839 | } else { | |
840 | ret = SR_ERR; | |
841 | } | |
842 | ||
843 | return ret; | |
844 | } | |
845 | ||
846 | /* Software trigger to determine exact trigger position. */ | |
847 | static int get_trigger_offset(uint16_t *samples, uint16_t last_sample, | |
848 | struct sigma_trigger *t) | |
849 | { | |
850 | int i; | |
851 | ||
852 | for (i = 0; i < 8; ++i) { | |
853 | if (i > 0) | |
854 | last_sample = samples[i-1]; | |
855 | ||
856 | /* Simple triggers. */ | |
857 | if ((samples[i] & t->simplemask) != t->simplevalue) | |
858 | continue; | |
859 | ||
860 | /* Rising edge. */ | |
861 | if ((last_sample & t->risingmask) != 0 || (samples[i] & | |
862 | t->risingmask) != t->risingmask) | |
863 | continue; | |
864 | ||
865 | /* Falling edge. */ | |
866 | if ((last_sample & t->fallingmask) != t->fallingmask || | |
867 | (samples[i] & t->fallingmask) != 0) | |
868 | continue; | |
869 | ||
870 | break; | |
871 | } | |
872 | ||
873 | /* If we did not match, return original trigger pos. */ | |
874 | return i & 0x7; | |
875 | } | |
876 | ||
877 | /* | |
878 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. | |
879 | * Each event is 20ns apart, and can contain multiple samples. | |
880 | * | |
881 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
882 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
883 | * For 50 MHz and below, events contain one sample for each channel, | |
884 | * spread 20 ns apart. | |
885 | */ | |
886 | static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts, | |
887 | uint16_t *lastsample, int triggerpos, | |
888 | uint16_t limit_chunk, void *cb_data) | |
889 | { | |
890 | struct sr_dev_inst *sdi = cb_data; | |
891 | struct dev_context *devc = sdi->priv; | |
892 | uint16_t tsdiff, ts; | |
893 | uint16_t samples[65536 * devc->samples_per_event]; | |
894 | struct sr_datafeed_packet packet; | |
895 | struct sr_datafeed_logic logic; | |
896 | int i, j, k, l, numpad, tosend; | |
897 | size_t n = 0, sent = 0; | |
898 | int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event; | |
899 | uint16_t *event; | |
900 | uint16_t cur_sample; | |
901 | int triggerts = -1; | |
902 | ||
903 | /* Check if trigger is in this chunk. */ | |
904 | if (triggerpos != -1) { | |
905 | if (devc->cur_samplerate <= SR_MHZ(50)) | |
906 | triggerpos -= EVENTS_PER_CLUSTER - 1; | |
907 | ||
908 | if (triggerpos < 0) | |
909 | triggerpos = 0; | |
910 | ||
911 | /* Find in which cluster the trigger occured. */ | |
912 | triggerts = triggerpos / 7; | |
913 | } | |
914 | ||
915 | /* For each ts. */ | |
916 | for (i = 0; i < 64; ++i) { | |
917 | ts = *(uint16_t *) &buf[i * 16]; | |
918 | tsdiff = ts - *lastts; | |
919 | *lastts = ts; | |
920 | ||
921 | /* Decode partial chunk. */ | |
922 | if (limit_chunk && ts > limit_chunk) | |
923 | return SR_OK; | |
924 | ||
925 | /* Pad last sample up to current point. */ | |
926 | numpad = tsdiff * devc->samples_per_event - clustersize; | |
927 | if (numpad > 0) { | |
928 | for (j = 0; j < numpad; ++j) | |
929 | samples[j] = *lastsample; | |
930 | ||
931 | n = numpad; | |
932 | } | |
933 | ||
934 | /* Send samples between previous and this timestamp to sigrok. */ | |
935 | sent = 0; | |
936 | while (sent < n) { | |
937 | tosend = MIN(2048, n - sent); | |
938 | ||
939 | packet.type = SR_DF_LOGIC; | |
940 | packet.payload = &logic; | |
941 | logic.length = tosend * sizeof(uint16_t); | |
942 | logic.unitsize = 2; | |
943 | logic.data = samples + sent; | |
944 | sr_session_send(devc->session_dev_id, &packet); | |
945 | ||
946 | sent += tosend; | |
947 | } | |
948 | n = 0; | |
949 | ||
950 | event = (uint16_t *) &buf[i * 16 + 2]; | |
951 | cur_sample = 0; | |
952 | ||
953 | /* For each event in cluster. */ | |
954 | for (j = 0; j < 7; ++j) { | |
955 | ||
956 | /* For each sample in event. */ | |
957 | for (k = 0; k < devc->samples_per_event; ++k) { | |
958 | cur_sample = 0; | |
959 | ||
960 | /* For each probe. */ | |
961 | for (l = 0; l < devc->num_probes; ++l) | |
962 | cur_sample |= (!!(event[j] & (1 << (l * | |
963 | devc->samples_per_event + k)))) << l; | |
964 | ||
965 | samples[n++] = cur_sample; | |
966 | } | |
967 | } | |
968 | ||
969 | /* Send data up to trigger point (if triggered). */ | |
970 | sent = 0; | |
971 | if (i == triggerts) { | |
972 | /* | |
973 | * Trigger is not always accurate to sample because of | |
974 | * pipeline delay. However, it always triggers before | |
975 | * the actual event. We therefore look at the next | |
976 | * samples to pinpoint the exact position of the trigger. | |
977 | */ | |
978 | tosend = get_trigger_offset(samples, *lastsample, | |
979 | &devc->trigger); | |
980 | ||
981 | if (tosend > 0) { | |
982 | packet.type = SR_DF_LOGIC; | |
983 | packet.payload = &logic; | |
984 | logic.length = tosend * sizeof(uint16_t); | |
985 | logic.unitsize = 2; | |
986 | logic.data = samples; | |
987 | sr_session_send(devc->session_dev_id, &packet); | |
988 | ||
989 | sent += tosend; | |
990 | } | |
991 | ||
992 | /* Only send trigger if explicitly enabled. */ | |
993 | if (devc->use_triggers) { | |
994 | packet.type = SR_DF_TRIGGER; | |
995 | sr_session_send(devc->session_dev_id, &packet); | |
996 | } | |
997 | } | |
998 | ||
999 | /* Send rest of the chunk to sigrok. */ | |
1000 | tosend = n - sent; | |
1001 | ||
1002 | if (tosend > 0) { | |
1003 | packet.type = SR_DF_LOGIC; | |
1004 | packet.payload = &logic; | |
1005 | logic.length = tosend * sizeof(uint16_t); | |
1006 | logic.unitsize = 2; | |
1007 | logic.data = samples + sent; | |
1008 | sr_session_send(devc->session_dev_id, &packet); | |
1009 | } | |
1010 | ||
1011 | *lastsample = samples[n - 1]; | |
1012 | } | |
1013 | ||
1014 | return SR_OK; | |
1015 | } | |
1016 | ||
1017 | static int receive_data(int fd, int revents, void *cb_data) | |
1018 | { | |
1019 | struct sr_dev_inst *sdi = cb_data; | |
1020 | struct dev_context *devc = sdi->priv; | |
1021 | struct sr_datafeed_packet packet; | |
1022 | const int chunks_per_read = 32; | |
1023 | unsigned char buf[chunks_per_read * CHUNK_SIZE]; | |
1024 | int bufsz, numchunks, i, newchunks; | |
1025 | uint64_t running_msec; | |
1026 | struct timeval tv; | |
1027 | ||
1028 | (void)fd; | |
1029 | (void)revents; | |
1030 | ||
1031 | /* Get the current position. */ | |
1032 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); | |
1033 | ||
1034 | numchunks = (devc->state.stoppos + 511) / 512; | |
1035 | ||
1036 | if (devc->state.state == SIGMA_IDLE) | |
1037 | return TRUE; | |
1038 | ||
1039 | if (devc->state.state == SIGMA_CAPTURE) { | |
1040 | /* Check if the timer has expired, or memory is full. */ | |
1041 | gettimeofday(&tv, 0); | |
1042 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + | |
1043 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
1044 | ||
1045 | if (running_msec < devc->limit_msec && numchunks < 32767) | |
1046 | return TRUE; /* While capturing... */ | |
1047 | else | |
1048 | hw_dev_acquisition_stop(sdi, sdi); | |
1049 | ||
1050 | } | |
1051 | ||
1052 | if (devc->state.state == SIGMA_DOWNLOAD) { | |
1053 | if (devc->state.chunks_downloaded >= numchunks) { | |
1054 | /* End of samples. */ | |
1055 | packet.type = SR_DF_END; | |
1056 | sr_session_send(devc->session_dev_id, &packet); | |
1057 | ||
1058 | devc->state.state = SIGMA_IDLE; | |
1059 | ||
1060 | return TRUE; | |
1061 | } | |
1062 | ||
1063 | newchunks = MIN(chunks_per_read, | |
1064 | numchunks - devc->state.chunks_downloaded); | |
1065 | ||
1066 | sr_info("Downloading sample data: %.0f %%.", | |
1067 | 100.0 * devc->state.chunks_downloaded / numchunks); | |
1068 | ||
1069 | bufsz = sigma_read_dram(devc->state.chunks_downloaded, | |
1070 | newchunks, buf, devc); | |
1071 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ | |
1072 | (void)bufsz; | |
1073 | ||
1074 | /* Find first ts. */ | |
1075 | if (devc->state.chunks_downloaded == 0) { | |
1076 | devc->state.lastts = *(uint16_t *) buf - 1; | |
1077 | devc->state.lastsample = 0; | |
1078 | } | |
1079 | ||
1080 | /* Decode chunks and send them to sigrok. */ | |
1081 | for (i = 0; i < newchunks; ++i) { | |
1082 | int limit_chunk = 0; | |
1083 | ||
1084 | /* The last chunk may potentially be only in part. */ | |
1085 | if (devc->state.chunks_downloaded == numchunks - 1) { | |
1086 | /* Find the last valid timestamp */ | |
1087 | limit_chunk = devc->state.stoppos % 512 + devc->state.lastts; | |
1088 | } | |
1089 | ||
1090 | if (devc->state.chunks_downloaded + i == devc->state.triggerchunk) | |
1091 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1092 | &devc->state.lastts, | |
1093 | &devc->state.lastsample, | |
1094 | devc->state.triggerpos & 0x1ff, | |
1095 | limit_chunk, sdi); | |
1096 | else | |
1097 | decode_chunk_ts(buf + (i * CHUNK_SIZE), | |
1098 | &devc->state.lastts, | |
1099 | &devc->state.lastsample, | |
1100 | -1, limit_chunk, sdi); | |
1101 | ||
1102 | ++devc->state.chunks_downloaded; | |
1103 | } | |
1104 | } | |
1105 | ||
1106 | return TRUE; | |
1107 | } | |
1108 | ||
1109 | /* Build a LUT entry used by the trigger functions. */ | |
1110 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
1111 | { | |
1112 | int i, j, k, bit; | |
1113 | ||
1114 | /* For each quad probe. */ | |
1115 | for (i = 0; i < 4; ++i) { | |
1116 | entry[i] = 0xffff; | |
1117 | ||
1118 | /* For each bit in LUT. */ | |
1119 | for (j = 0; j < 16; ++j) | |
1120 | ||
1121 | /* For each probe in quad. */ | |
1122 | for (k = 0; k < 4; ++k) { | |
1123 | bit = 1 << (i * 4 + k); | |
1124 | ||
1125 | /* Set bit in entry */ | |
1126 | if ((mask & bit) && | |
1127 | ((!(value & bit)) != | |
1128 | (!(j & (1 << k))))) | |
1129 | entry[i] &= ~(1 << j); | |
1130 | } | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | /* Add a logical function to LUT mask. */ | |
1135 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1136 | int index, int neg, uint16_t *mask) | |
1137 | { | |
1138 | int i, j; | |
1139 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1140 | ||
1141 | memset(x, 0, 4 * sizeof(int)); | |
1142 | ||
1143 | /* Trigger detect condition. */ | |
1144 | switch (oper) { | |
1145 | case OP_LEVEL: | |
1146 | x[0][1] = 1; | |
1147 | x[1][1] = 1; | |
1148 | break; | |
1149 | case OP_NOT: | |
1150 | x[0][0] = 1; | |
1151 | x[1][0] = 1; | |
1152 | break; | |
1153 | case OP_RISE: | |
1154 | x[0][1] = 1; | |
1155 | break; | |
1156 | case OP_FALL: | |
1157 | x[1][0] = 1; | |
1158 | break; | |
1159 | case OP_RISEFALL: | |
1160 | x[0][1] = 1; | |
1161 | x[1][0] = 1; | |
1162 | break; | |
1163 | case OP_NOTRISE: | |
1164 | x[1][1] = 1; | |
1165 | x[0][0] = 1; | |
1166 | x[1][0] = 1; | |
1167 | break; | |
1168 | case OP_NOTFALL: | |
1169 | x[1][1] = 1; | |
1170 | x[0][0] = 1; | |
1171 | x[0][1] = 1; | |
1172 | break; | |
1173 | case OP_NOTRISEFALL: | |
1174 | x[1][1] = 1; | |
1175 | x[0][0] = 1; | |
1176 | break; | |
1177 | } | |
1178 | ||
1179 | /* Transpose if neg is set. */ | |
1180 | if (neg) { | |
1181 | for (i = 0; i < 2; ++i) { | |
1182 | for (j = 0; j < 2; ++j) { | |
1183 | tmp = x[i][j]; | |
1184 | x[i][j] = x[1-i][1-j]; | |
1185 | x[1-i][1-j] = tmp; | |
1186 | } | |
1187 | } | |
1188 | } | |
1189 | ||
1190 | /* Update mask with function. */ | |
1191 | for (i = 0; i < 16; ++i) { | |
1192 | a = (i >> (2 * index + 0)) & 1; | |
1193 | b = (i >> (2 * index + 1)) & 1; | |
1194 | ||
1195 | aset = (*mask >> i) & 1; | |
1196 | bset = x[b][a]; | |
1197 | ||
1198 | if (func == FUNC_AND || func == FUNC_NAND) | |
1199 | rset = aset & bset; | |
1200 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1201 | rset = aset | bset; | |
1202 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1203 | rset = aset ^ bset; | |
1204 | ||
1205 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1206 | rset = !rset; | |
1207 | ||
1208 | *mask &= ~(1 << i); | |
1209 | ||
1210 | if (rset) | |
1211 | *mask |= 1 << i; | |
1212 | } | |
1213 | } | |
1214 | ||
1215 | /* | |
1216 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1217 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1218 | * set at any time, but a full mask and value can be set (0/1). | |
1219 | */ | |
1220 | static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) | |
1221 | { | |
1222 | int i,j; | |
1223 | uint16_t masks[2] = { 0, 0 }; | |
1224 | ||
1225 | memset(lut, 0, sizeof(struct triggerlut)); | |
1226 | ||
1227 | /* Contant for simple triggers. */ | |
1228 | lut->m4 = 0xa000; | |
1229 | ||
1230 | /* Value/mask trigger support. */ | |
1231 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, | |
1232 | lut->m2d); | |
1233 | ||
1234 | /* Rise/fall trigger support. */ | |
1235 | for (i = 0, j = 0; i < 16; ++i) { | |
1236 | if (devc->trigger.risingmask & (1 << i) || | |
1237 | devc->trigger.fallingmask & (1 << i)) | |
1238 | masks[j++] = 1 << i; | |
1239 | } | |
1240 | ||
1241 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1242 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1243 | ||
1244 | /* Add glue logic */ | |
1245 | if (masks[0] || masks[1]) { | |
1246 | /* Transition trigger. */ | |
1247 | if (masks[0] & devc->trigger.risingmask) | |
1248 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); | |
1249 | if (masks[0] & devc->trigger.fallingmask) | |
1250 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); | |
1251 | if (masks[1] & devc->trigger.risingmask) | |
1252 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); | |
1253 | if (masks[1] & devc->trigger.fallingmask) | |
1254 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); | |
1255 | } else { | |
1256 | /* Only value/mask trigger. */ | |
1257 | lut->m3 = 0xffff; | |
1258 | } | |
1259 | ||
1260 | /* Triggertype: event. */ | |
1261 | lut->params.selres = 3; | |
1262 | ||
1263 | return SR_OK; | |
1264 | } | |
1265 | ||
1266 | static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi, | |
1267 | void *cb_data) | |
1268 | { | |
1269 | struct dev_context *devc; | |
1270 | struct sr_datafeed_packet *packet; | |
1271 | struct sr_datafeed_header *header; | |
1272 | struct clockselect_50 clockselect; | |
1273 | int frac, triggerpin, ret; | |
1274 | uint8_t triggerselect = 0; | |
1275 | struct triggerinout triggerinout_conf; | |
1276 | struct triggerlut lut; | |
1277 | ||
1278 | devc = sdi->priv; | |
1279 | ||
1280 | if (configure_probes(sdi) != SR_OK) { | |
1281 | sr_err("Failed to configure probes."); | |
1282 | return SR_ERR; | |
1283 | } | |
1284 | ||
1285 | /* If the samplerate has not been set, default to 200 kHz. */ | |
1286 | if (devc->cur_firmware == -1) { | |
1287 | if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK) | |
1288 | return ret; | |
1289 | } | |
1290 | ||
1291 | /* Enter trigger programming mode. */ | |
1292 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc); | |
1293 | ||
1294 | /* 100 and 200 MHz mode. */ | |
1295 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
1296 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc); | |
1297 | ||
1298 | /* Find which pin to trigger on from mask. */ | |
1299 | for (triggerpin = 0; triggerpin < 8; ++triggerpin) | |
1300 | if ((devc->trigger.risingmask | devc->trigger.fallingmask) & | |
1301 | (1 << triggerpin)) | |
1302 | break; | |
1303 | ||
1304 | /* Set trigger pin and light LED on trigger. */ | |
1305 | triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7); | |
1306 | ||
1307 | /* Default rising edge. */ | |
1308 | if (devc->trigger.fallingmask) | |
1309 | triggerselect |= 1 << 3; | |
1310 | ||
1311 | /* All other modes. */ | |
1312 | } else if (devc->cur_samplerate <= SR_MHZ(50)) { | |
1313 | build_basic_trigger(&lut, devc); | |
1314 | ||
1315 | sigma_write_trigger_lut(&lut, devc); | |
1316 | ||
1317 | triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0); | |
1318 | } | |
1319 | ||
1320 | /* Setup trigger in and out pins to default values. */ | |
1321 | memset(&triggerinout_conf, 0, sizeof(struct triggerinout)); | |
1322 | triggerinout_conf.trgout_bytrigger = 1; | |
1323 | triggerinout_conf.trgout_enable = 1; | |
1324 | ||
1325 | sigma_write_register(WRITE_TRIGGER_OPTION, | |
1326 | (uint8_t *) &triggerinout_conf, | |
1327 | sizeof(struct triggerinout), devc); | |
1328 | ||
1329 | /* Go back to normal mode. */ | |
1330 | sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc); | |
1331 | ||
1332 | /* Set clock select register. */ | |
1333 | if (devc->cur_samplerate == SR_MHZ(200)) | |
1334 | /* Enable 4 probes. */ | |
1335 | sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc); | |
1336 | else if (devc->cur_samplerate == SR_MHZ(100)) | |
1337 | /* Enable 8 probes. */ | |
1338 | sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc); | |
1339 | else { | |
1340 | /* | |
1341 | * 50 MHz mode (or fraction thereof). Any fraction down to | |
1342 | * 50 MHz / 256 can be used, but is not supported by sigrok API. | |
1343 | */ | |
1344 | frac = SR_MHZ(50) / devc->cur_samplerate - 1; | |
1345 | ||
1346 | clockselect.async = 0; | |
1347 | clockselect.fraction = frac; | |
1348 | clockselect.disabled_probes = 0; | |
1349 | ||
1350 | sigma_write_register(WRITE_CLOCK_SELECT, | |
1351 | (uint8_t *) &clockselect, | |
1352 | sizeof(clockselect), devc); | |
1353 | } | |
1354 | ||
1355 | /* Setup maximum post trigger time. */ | |
1356 | sigma_set_register(WRITE_POST_TRIGGER, | |
1357 | (devc->capture_ratio * 255) / 100, devc); | |
1358 | ||
1359 | /* Start acqusition. */ | |
1360 | gettimeofday(&devc->start_tv, 0); | |
1361 | sigma_set_register(WRITE_MODE, 0x0d, devc); | |
1362 | ||
1363 | devc->session_dev_id = cb_data; | |
1364 | ||
1365 | if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) { | |
1366 | sr_err("%s: packet malloc failed.", __func__); | |
1367 | return SR_ERR_MALLOC; | |
1368 | } | |
1369 | ||
1370 | if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) { | |
1371 | sr_err("%s: header malloc failed.", __func__); | |
1372 | return SR_ERR_MALLOC; | |
1373 | } | |
1374 | ||
1375 | /* Send header packet to the session bus. */ | |
1376 | packet->type = SR_DF_HEADER; | |
1377 | packet->payload = header; | |
1378 | header->feed_version = 1; | |
1379 | gettimeofday(&header->starttime, NULL); | |
1380 | sr_session_send(devc->session_dev_id, packet); | |
1381 | ||
1382 | /* Add capture source. */ | |
1383 | sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi); | |
1384 | ||
1385 | g_free(header); | |
1386 | g_free(packet); | |
1387 | ||
1388 | devc->state.state = SIGMA_CAPTURE; | |
1389 | ||
1390 | return SR_OK; | |
1391 | } | |
1392 | ||
1393 | static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data) | |
1394 | { | |
1395 | struct dev_context *devc; | |
1396 | uint8_t modestatus; | |
1397 | ||
1398 | (void)cb_data; | |
1399 | ||
1400 | sr_source_remove(0); | |
1401 | ||
1402 | if (!(devc = sdi->priv)) { | |
1403 | sr_err("%s: sdi->priv was NULL", __func__); | |
1404 | return SR_ERR_BUG; | |
1405 | } | |
1406 | ||
1407 | /* Stop acquisition. */ | |
1408 | sigma_set_register(WRITE_MODE, 0x11, devc); | |
1409 | ||
1410 | /* Set SDRAM Read Enable. */ | |
1411 | sigma_set_register(WRITE_MODE, 0x02, devc); | |
1412 | ||
1413 | /* Get the current position. */ | |
1414 | sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc); | |
1415 | ||
1416 | /* Check if trigger has fired. */ | |
1417 | modestatus = sigma_get_register(READ_MODE, devc); | |
1418 | if (modestatus & 0x20) | |
1419 | devc->state.triggerchunk = devc->state.triggerpos / 512; | |
1420 | else | |
1421 | devc->state.triggerchunk = -1; | |
1422 | ||
1423 | devc->state.chunks_downloaded = 0; | |
1424 | ||
1425 | devc->state.state = SIGMA_DOWNLOAD; | |
1426 | ||
1427 | return SR_OK; | |
1428 | } | |
1429 | ||
1430 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info = { | |
1431 | .name = "asix-sigma", | |
1432 | .longname = "ASIX SIGMA/SIGMA2", | |
1433 | .api_version = 1, | |
1434 | .init = hw_init, | |
1435 | .cleanup = hw_cleanup, | |
1436 | .scan = hw_scan, | |
1437 | .dev_list = hw_dev_list, | |
1438 | .dev_clear = clear_instances, | |
1439 | .config_get = config_get, | |
1440 | .config_set = config_set, | |
1441 | .dev_open = hw_dev_open, | |
1442 | .dev_close = hw_dev_close, | |
1443 | .dev_acquisition_start = hw_dev_acquisition_start, | |
1444 | .dev_acquisition_stop = hw_dev_acquisition_stop, | |
1445 | .priv = NULL, | |
1446 | }; |