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drivers: Consistently make LOG_PREFIX the first item after #includes.
[libsigrok.git] / src / hardware / sysclk-lwla / protocol.h
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1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
21#define LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
22
5874e88d 23#include <stdint.h>
93ed0241 24#include <libusb.h>
5874e88d 25#include <glib.h>
c1aae900 26#include <libsigrok/libsigrok.h>
be64f90b 27#include <libsigrok-internal.h>
aeaad0b0 28
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29#define LOG_PREFIX "sysclk-lwla"
30
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31/* Maximum configurable sample count limit.
32 * Due to compression, there is no meaningful hardware limit the driver
33 * could report. So this value is less than 2^64-1 for no reason other
34 * than to safeguard against integer overflows.
5874e88d 35 */
be64f90b 36#define MAX_LIMIT_SAMPLES (UINT64_C(1000) * 1000 * 1000 * 1000)
5874e88d 37
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38/* Maximum configurable acquisition time limit.
39 * Due to compression, there is no hardware limit that would be meaningful
40 * in practice. However, the LWLA1016 reports the elapsed time as a 32-bit
41 * value, so keep this below 2^32.
5874e88d 42 */
be64f90b 43#define MAX_LIMIT_MSEC (1000 * 1000 * 1000)
5874e88d 44
be64f90b 45struct acquisition_state;
5874e88d 46
ca314e06 47/* USB vendor and product IDs. */
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48enum {
49 USB_VID_SYSCLK = 0x2961,
50 USB_PID_LWLA1016 = 0x6688,
51 USB_PID_LWLA1034 = 0x6689,
52};
29d58767 53
ca314e06 54/* USB device characteristics. */
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55enum {
56 USB_CONFIG = 1,
57 USB_INTERFACE = 0,
e35a4592 58 USB_TIMEOUT_MS = 1000,
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59};
60
ca314e06 61/** USB device end points. */
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62enum usb_endpoint {
63 EP_COMMAND = 2,
64 EP_CONFIG = 4,
65 EP_REPLY = 6 | LIBUSB_ENDPOINT_IN
66};
67
ca314e06 68/** LWLA1034 clock sources. */
5874e88d 69enum clock_source {
be64f90b 70 CLOCK_INTERNAL = 0,
6358f0a9 71 CLOCK_EXT_CLK,
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72};
73
ca314e06 74/** LWLA1034 trigger sources. */
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75enum trigger_source {
76 TRIGGER_CHANNELS = 0,
77 TRIGGER_EXT_TRG,
78};
79
ca314e06 80/** Edge choices for the LWLA1034 external clock and trigger inputs. */
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81enum signal_edge {
82 EDGE_POSITIVE = 0,
83 EDGE_NEGATIVE,
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84};
85
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86/* Common indicator for no or unknown FPGA config. */
87enum {
88 FPGA_NOCONF = -1,
89};
90
ca314e06 91/** Acquisition protocol states. */
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92enum protocol_state {
93 /* idle states */
5874e88d 94 STATE_IDLE = 0,
5874e88d 95 STATE_STATUS_WAIT,
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96 /* device command states */
97 STATE_START_CAPTURE,
5874e88d 98 STATE_STOP_CAPTURE,
5874e88d 99 STATE_READ_PREPARE,
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100 STATE_READ_FINISH,
101 /* command followed by response */
102 STATE_EXPECT_RESPONSE = 1 << 3,
103 STATE_STATUS_REQUEST = STATE_EXPECT_RESPONSE,
104 STATE_LENGTH_REQUEST,
5874e88d 105 STATE_READ_REQUEST,
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106};
107
aeaad0b0 108struct dev_context {
be64f90b 109 uint64_t samplerate; /* requested samplerate */
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110 uint64_t limit_msec; /* requested capture duration in ms */
111 uint64_t limit_samples; /* requested capture length in samples */
5874e88d 112
407b6e2c 113 uint64_t channel_mask; /* bit mask of enabled channels */
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114 uint64_t trigger_mask; /* trigger enable mask */
115 uint64_t trigger_edge_mask; /* trigger type mask */
116 uint64_t trigger_values; /* trigger level/slope bits */
aeaad0b0 117
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118 const struct model_info *model; /* device model descriptor */
119 struct acquisition_state *acquisition; /* running capture state */
120 int active_fpga_config; /* FPGA configuration index */
78648577 121 gboolean short_transfer_quirk; /* 64 bytes response limit */
aeaad0b0 122
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123 enum protocol_state state; /* async protocol state */
124 gboolean cancel_requested; /* stop after current transfer */
125 gboolean transfer_error; /* error during device communication */
aeaad0b0 126
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127 gboolean cfg_rle; /* RLE compression setting */
128 enum clock_source cfg_clock_source; /* clock source setting */
129 enum signal_edge cfg_clock_edge; /* ext clock edge setting */
130 enum trigger_source cfg_trigger_source; /* trigger source setting */
131 enum signal_edge cfg_trigger_slope; /* ext trigger slope setting */
be64f90b 132};
6358f0a9 133
ca314e06 134/** LWLA model descriptor. */
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135struct model_info {
136 char name[12];
137 int num_channels;
5874e88d 138
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139 unsigned int num_devopts;
140 uint32_t devopts[8];
e6e54bd2 141
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142 unsigned int num_samplerates;
143 uint64_t samplerates[20];
c81069b3 144
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145 int (*apply_fpga_config)(const struct sr_dev_inst *sdi);
146 int (*device_init_check)(const struct sr_dev_inst *sdi);
147 int (*setup_acquisition)(const struct sr_dev_inst *sdi);
5874e88d 148
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149 int (*prepare_request)(const struct sr_dev_inst *sdi);
150 int (*handle_response)(const struct sr_dev_inst *sdi);
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151};
152
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153extern SR_PRIV const struct model_info lwla1016_info;
154extern SR_PRIV const struct model_info lwla1034_info;
5874e88d 155
5874e88d 156SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi);
aeaad0b0 157
db24496a 158#endif