]> sigrok.org Git - libsigrok.git/blame - src/hardware/pipistrello-ols/api.c
Add sr_dev_acquisition_start(), factor out SR_ERR_DEV_CLOSED check.
[libsigrok.git] / src / hardware / pipistrello-ols / api.c
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4bd80e12 1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
6ec6c43b 20#include <config.h>
4bd80e12 21#include "protocol.h"
22
f254bc4b 23static const uint32_t devopts[] = {
4bd80e12 24 SR_CONF_LOGIC_ANALYZER,
5827f61b
BV
25 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
26 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
27 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
28 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
29 SR_CONF_PATTERN_MODE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
30 SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
31 SR_CONF_SWAP | SR_CONF_SET,
32 SR_CONF_RLE | SR_CONF_GET | SR_CONF_SET,
4bd80e12 33};
34
acc885c7
BV
35static const int32_t trigger_matches[] = {
36 SR_TRIGGER_ZERO,
37 SR_TRIGGER_ONE,
38 SR_TRIGGER_RISING,
39 SR_TRIGGER_FALLING,
40};
41
4bd80e12 42#define STR_PATTERN_NONE "None"
43#define STR_PATTERN_EXTERNAL "External"
44#define STR_PATTERN_INTERNAL "Internal"
45
46/* Supported methods of test pattern outputs */
47enum {
48 /**
49 * Capture pins 31:16 (unbuffered wing) output a test pattern
50 * that can captured on pins 0:15.
51 */
52 PATTERN_EXTERNAL,
53
54 /** Route test pattern internally to capture buffer. */
55 PATTERN_INTERNAL,
56};
57
58static const char *patterns[] = {
59 STR_PATTERN_NONE,
60 STR_PATTERN_EXTERNAL,
61 STR_PATTERN_INTERNAL,
62};
63
64/* Channels are numbered 0-31 (on the PCB silkscreen). */
53cda65a 65SR_PRIV const char *p_ols_channel_names[] = {
4bd80e12 66 "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12",
67 "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23",
68 "24", "25", "26", "27", "28", "29", "30", "31",
4bd80e12 69};
70
71/* Default supported samplerates, can be overridden by device metadata. */
72static const uint64_t samplerates[] = {
73 SR_HZ(10),
74 SR_MHZ(200),
75 SR_HZ(1),
76};
77
4f840ce9 78static GSList *scan(struct sr_dev_driver *di, GSList *options)
4bd80e12 79{
80 struct sr_dev_inst *sdi;
4bd80e12 81 struct dev_context *devc;
82 GSList *devices;
83 int ret, i;
84 char buf[70];
85 int bytes_read;
86
87 (void)options;
88
4bd80e12 89 devices = NULL;
90
91 /* Allocate memory for our private device context. */
f57d8ffe 92 devc = g_malloc0(sizeof(struct dev_context));
4bd80e12 93
94 /* Device-specific settings */
b94cff40 95 devc->max_samplebytes = devc->max_samplerate = devc->protocol_version = 0;
4bd80e12 96
97 /* Acquisition settings */
98 devc->limit_samples = devc->capture_ratio = 0;
99 devc->trigger_at = -1;
100 devc->channel_mask = 0xffffffff;
101 devc->flag_reg = 0;
102
103 /* Allocate memory for the incoming ftdi data. */
a95f142e 104 devc->ftdi_buf = g_malloc0(FTDI_BUF_SIZE);
4bd80e12 105
106 /* Allocate memory for the FTDI context (ftdic) and initialize it. */
107 if (!(devc->ftdic = ftdi_new())) {
108 sr_err("Failed to initialize libftdi.");
109 goto err_free_ftdi_buf;;
110 }
111
112 /* Try to open the FTDI device */
113 if (p_ols_open(devc) != SR_OK) {
114 goto err_free_ftdic;
115 }
176d785d 116
4bd80e12 117 /* The discovery procedure is like this: first send the Reset
118 * command (0x00) 5 times, since the device could be anywhere
119 * in a 5-byte command. Then send the ID command (0x02).
120 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
121 * have a match.
122 */
123
124 ret = SR_OK;
125 for (i = 0; i < 5; i++) {
126 if ((ret = write_shortcommand(devc, CMD_RESET)) != SR_OK) {
127 break;
128 }
129 }
130 if (ret != SR_OK) {
131 sr_err("Could not reset device. Quitting.");
132 goto err_close_ftdic;
133 }
134 write_shortcommand(devc, CMD_ID);
135
136 /* Read the response data. */
137 bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 4);
138 if (bytes_read < 0) {
139 sr_err("Failed to read FTDI data (%d): %s.",
140 bytes_read, ftdi_get_error_string(devc->ftdic));
141 goto err_close_ftdic;
142 }
143 if (bytes_read == 0) {
144 goto err_close_ftdic;
145 }
146
147 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
148 goto err_close_ftdic;
149
150 /* Definitely using the OLS protocol, check if it supports
151 * the metadata command.
152 */
153 write_shortcommand(devc, CMD_METADATA);
154
155 /* Read the metadata. */
156 bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 64);
157 if (bytes_read < 0) {
158 sr_err("Failed to read FTDI data (%d): %s.",
159 bytes_read, ftdi_get_error_string(devc->ftdic));
160 goto err_close_ftdic;
161 }
162 if (bytes_read == 0) {
163 goto err_close_ftdic;
164 }
165
166 /* Close device. We'll reopen it again when we need it. */
167 p_ols_close(devc);
168
169 /* Parse the metadata. */
170 sdi = p_ols_get_metadata((uint8_t *)buf, bytes_read, devc);
4bd80e12 171
172 /* Configure samplerate and divider. */
173 if (p_ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK)
174 sr_dbg("Failed to set default samplerate (%"PRIu64").",
175 DEFAULT_SAMPLERATE);
4bd80e12 176
4bd80e12 177 devices = g_slist_append(devices, sdi);
178
15a5bfe4 179 return std_scan_complete(di, devices);
4bd80e12 180
181err_close_ftdic:
182 p_ols_close(devc);
183err_free_ftdic:
184 ftdi_free(devc->ftdic); /* NOT free() or g_free()! */
185err_free_ftdi_buf:
186 g_free(devc->ftdi_buf);
4bd80e12 187 g_free(devc);
4bd80e12 188
189 return NULL;
190}
191
4bd80e12 192static void clear_helper(void *priv)
193{
194 struct dev_context *devc;
195
196 devc = priv;
197
198 ftdi_free(devc->ftdic);
199 g_free(devc->ftdi_buf);
200}
201
4f840ce9 202static int dev_clear(const struct sr_dev_driver *di)
4bd80e12 203{
204 return std_dev_clear(di, clear_helper);
205}
206
584560f1 207static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
4bd80e12 208 const struct sr_channel_group *cg)
209{
210 struct dev_context *devc;
211
212 (void)cg;
213
214 if (!sdi)
215 return SR_ERR_ARG;
216
217 devc = sdi->priv;
584560f1 218 switch (key) {
4bd80e12 219 case SR_CONF_SAMPLERATE:
220 *data = g_variant_new_uint64(devc->cur_samplerate);
221 break;
222 case SR_CONF_CAPTURE_RATIO:
223 *data = g_variant_new_uint64(devc->capture_ratio);
224 break;
225 case SR_CONF_LIMIT_SAMPLES:
226 *data = g_variant_new_uint64(devc->limit_samples);
227 break;
228 case SR_CONF_PATTERN_MODE:
229 if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE)
230 *data = g_variant_new_string(STR_PATTERN_EXTERNAL);
231 else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE)
232 *data = g_variant_new_string(STR_PATTERN_INTERNAL);
233 else
234 *data = g_variant_new_string(STR_PATTERN_NONE);
235 break;
236 case SR_CONF_RLE:
237 *data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE);
238 break;
239 case SR_CONF_EXTERNAL_CLOCK:
240 *data = g_variant_new_boolean(devc->flag_reg & FLAG_CLOCK_EXTERNAL ? TRUE : FALSE);
241 break;
242 default:
243 return SR_ERR_NA;
244 }
245
246 return SR_OK;
247}
248
584560f1 249static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
4bd80e12 250 const struct sr_channel_group *cg)
251{
252 struct dev_context *devc;
253 uint16_t flag;
254 uint64_t tmp_u64;
255 int ret;
256 const char *stropt;
257
258 (void)cg;
259
260 if (sdi->status != SR_ST_ACTIVE)
261 return SR_ERR_DEV_CLOSED;
262
263 devc = sdi->priv;
264
584560f1 265 switch (key) {
4bd80e12 266 case SR_CONF_SAMPLERATE:
267 tmp_u64 = g_variant_get_uint64(data);
268 if (tmp_u64 < samplerates[0] || tmp_u64 > samplerates[1])
269 return SR_ERR_SAMPLERATE;
270 ret = p_ols_set_samplerate(sdi, g_variant_get_uint64(data));
271 break;
272 case SR_CONF_LIMIT_SAMPLES:
273 tmp_u64 = g_variant_get_uint64(data);
274 if (tmp_u64 < MIN_NUM_SAMPLES)
275 return SR_ERR;
276 devc->limit_samples = tmp_u64;
277 ret = SR_OK;
278 break;
279 case SR_CONF_CAPTURE_RATIO:
280 devc->capture_ratio = g_variant_get_uint64(data);
a5c38703 281 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
4bd80e12 282 ret = SR_ERR;
a5c38703 283 else
4bd80e12 284 ret = SR_OK;
285 break;
286 case SR_CONF_EXTERNAL_CLOCK:
287 if (g_variant_get_boolean(data)) {
288 sr_info("Enabling external clock.");
289 devc->flag_reg |= FLAG_CLOCK_EXTERNAL;
290 } else {
291 sr_info("Disabled external clock.");
292 devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL;
293 }
294 ret = SR_OK;
295 break;
296 case SR_CONF_PATTERN_MODE:
297 stropt = g_variant_get_string(data, NULL);
298 ret = SR_OK;
299 flag = 0xffff;
300 if (!strcmp(stropt, STR_PATTERN_NONE)) {
301 sr_info("Disabling test modes.");
302 flag = 0x0000;
303 }else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) {
304 sr_info("Enabling internal test mode.");
305 flag = FLAG_INTERNAL_TEST_MODE;
306 } else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) {
307 sr_info("Enabling external test mode.");
308 flag = FLAG_EXTERNAL_TEST_MODE;
309 } else {
310 ret = SR_ERR;
311 }
312 if (flag != 0xffff) {
313 devc->flag_reg &= ~(FLAG_INTERNAL_TEST_MODE | FLAG_EXTERNAL_TEST_MODE);
314 devc->flag_reg |= flag;
315 }
316 break;
317 case SR_CONF_SWAP:
318 if (g_variant_get_boolean(data)) {
319 sr_info("Enabling channel swapping.");
320 devc->flag_reg |= FLAG_SWAP_CHANNELS;
321 } else {
322 sr_info("Disabling channel swapping.");
323 devc->flag_reg &= ~FLAG_SWAP_CHANNELS;
324 }
325 ret = SR_OK;
326 break;
327
328 case SR_CONF_RLE:
329 if (g_variant_get_boolean(data)) {
330 sr_info("Enabling RLE.");
331 devc->flag_reg |= FLAG_RLE;
332 } else {
333 sr_info("Disabling RLE.");
334 devc->flag_reg &= ~FLAG_RLE;
335 }
336 ret = SR_OK;
337 break;
338 default:
339 ret = SR_ERR_NA;
340 }
341
342 return ret;
343}
344
584560f1 345static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
4bd80e12 346 const struct sr_channel_group *cg)
347{
348 struct dev_context *devc;
349 GVariant *gvar, *grange[2];
350 GVariantBuilder gvb;
acc885c7 351 int num_pols_changrp, i;
4bd80e12 352
353 (void)cg;
354
355 switch (key) {
356 case SR_CONF_DEVICE_OPTIONS:
584560f1 357 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
f254bc4b 358 devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
4bd80e12 359 break;
360 case SR_CONF_SAMPLERATE:
361 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
362 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
363 ARRAY_SIZE(samplerates), sizeof(uint64_t));
364 g_variant_builder_add(&gvb, "{sv}", "samplerate-steps", gvar);
365 *data = g_variant_builder_end(&gvb);
366 break;
acc885c7
BV
367 case SR_CONF_TRIGGER_MATCH:
368 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
369 trigger_matches, ARRAY_SIZE(trigger_matches),
370 sizeof(int32_t));
4bd80e12 371 break;
372 case SR_CONF_PATTERN_MODE:
373 *data = g_variant_new_strv(patterns, ARRAY_SIZE(patterns));
374 break;
375 case SR_CONF_LIMIT_SAMPLES:
376 if (!sdi)
377 return SR_ERR_ARG;
378 devc = sdi->priv;
379 if (devc->flag_reg & FLAG_RLE)
380 return SR_ERR_NA;
b94cff40 381 if (devc->max_samplebytes == 0)
4bd80e12 382 /* Device didn't specify sample memory size in metadata. */
383 return SR_ERR_NA;
384 /*
385 * Channel groups are turned off if no channels in that group are
386 * enabled, making more room for samples for the enabled group.
387 */
acc885c7
BV
388 pols_channel_mask(sdi);
389 num_pols_changrp = 0;
4bd80e12 390 for (i = 0; i < 4; i++) {
391 if (devc->channel_mask & (0xff << (i * 8)))
acc885c7 392 num_pols_changrp++;
4bd80e12 393 }
b94cff40 394 /* 3 channel groups takes as many bytes as 4 channel groups */
acc885c7
BV
395 if (num_pols_changrp == 3)
396 num_pols_changrp = 4;
4bd80e12 397 grange[0] = g_variant_new_uint64(MIN_NUM_SAMPLES);
acc885c7
BV
398 if (num_pols_changrp)
399 grange[1] = g_variant_new_uint64(devc->max_samplebytes / num_pols_changrp);
400 else
401 grange[1] = g_variant_new_uint64(MIN_NUM_SAMPLES);
4bd80e12 402 *data = g_variant_new_tuple(grange, 2);
403 break;
404 default:
405 return SR_ERR_NA;
406 }
407
408 return SR_OK;
409}
410
411static int dev_open(struct sr_dev_inst *sdi)
412{
413 struct dev_context *devc;
4bd80e12 414
415 devc = sdi->priv;
416
417 if (p_ols_open(devc) != SR_OK) {
418 return SR_ERR;
419 } else {
dcd438ee 420 sdi->status = SR_ST_ACTIVE;
4bd80e12 421 return SR_OK;
422 }
423}
424
425static int dev_close(struct sr_dev_inst *sdi)
426{
427 int ret;
428 struct dev_context *devc;
429
430 ret = SR_OK;
431 devc = sdi->priv;
432
433 if (sdi->status == SR_ST_ACTIVE) {
434 sr_dbg("Status ACTIVE, closing device.");
435 ret = p_ols_close(devc);
436 } else {
437 sr_spew("Status not ACTIVE, nothing to do.");
438 }
439
440 sdi->status = SR_ST_INACTIVE;
441
442 return ret;
443}
444
4bd80e12 445static int set_trigger(const struct sr_dev_inst *sdi, int stage)
446{
447 struct dev_context *devc;
448 uint8_t cmd, arg[4];
449
450 devc = sdi->priv;
451
452 cmd = CMD_SET_TRIGGER_MASK + stage * 4;
453 arg[0] = devc->trigger_mask[stage] & 0xff;
454 arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff;
455 arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff;
456 arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff;
457 if (write_longcommand(devc, cmd, arg) != SR_OK)
458 return SR_ERR;
459
460 cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
461 arg[0] = devc->trigger_value[stage] & 0xff;
462 arg[1] = (devc->trigger_value[stage] >> 8) & 0xff;
463 arg[2] = (devc->trigger_value[stage] >> 16) & 0xff;
464 arg[3] = (devc->trigger_value[stage] >> 24) & 0xff;
465 if (write_longcommand(devc, cmd, arg) != SR_OK)
466 return SR_ERR;
467
468 cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
469 arg[0] = arg[1] = arg[3] = 0x00;
470 arg[2] = stage;
471 if (stage == devc->num_stages)
472 /* Last stage, fire when this one matches. */
473 arg[3] |= TRIGGER_START;
474 if (write_longcommand(devc, cmd, arg) != SR_OK)
475 return SR_ERR;
476
1e0de846 477 cmd = CMD_SET_TRIGGER_EDGE + stage * 4;
478 arg[0] = devc->trigger_edge[stage] & 0xff;
479 arg[1] = (devc->trigger_edge[stage] >> 8) & 0xff;
480 arg[2] = (devc->trigger_edge[stage] >> 16) & 0xff;
481 arg[3] = (devc->trigger_edge[stage] >> 24) & 0xff;
482 if (write_longcommand(devc, cmd, arg) != SR_OK)
483 return SR_ERR;
484
4bd80e12 485 return SR_OK;
486}
487
84cbaf77
BV
488static int disable_trigger(const struct sr_dev_inst *sdi, int stage)
489{
490 struct dev_context *devc;
491 uint8_t cmd, arg[4];
492
493 devc = sdi->priv;
494
495 cmd = CMD_SET_TRIGGER_MASK + stage * 4;
496 arg[0] = arg[1] = arg[2] = arg[3] = 0x00;
497 if (write_longcommand(devc, cmd, arg) != SR_OK)
498 return SR_ERR;
499
500 cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
501 if (write_longcommand(devc, cmd, arg) != SR_OK)
502 return SR_ERR;
503
504 cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
505 arg[2] = 0x03;
506 if (write_longcommand(devc, cmd, arg) != SR_OK)
507 return SR_ERR;
508
509 cmd = CMD_SET_TRIGGER_EDGE + stage * 4;
510 arg[2] = 0x00;
511 if (write_longcommand(devc, cmd, arg) != SR_OK)
512 return SR_ERR;
513
514 return SR_OK;
515}
516
695dc859 517static int dev_acquisition_start(const struct sr_dev_inst *sdi)
4bd80e12 518{
519 struct dev_context *devc;
520 uint32_t samplecount, readcount, delaycount;
acc885c7 521 uint8_t pols_changrp_mask, arg[4];
b94cff40 522 uint16_t flag_tmp;
acc885c7 523 int num_pols_changrp, samplespercount;
4bd80e12 524 int ret, i;
525
4bd80e12 526 devc = sdi->priv;
527
acc885c7 528 pols_channel_mask(sdi);
4bd80e12 529
530 /*
531 * Enable/disable channel groups in the flag register according to the
acc885c7
BV
532 * channel mask. Calculate this here, because num_pols_changrp is
533 * needed to limit readcount.
4bd80e12 534 */
acc885c7
BV
535 pols_changrp_mask = 0;
536 num_pols_changrp = 0;
4bd80e12 537 for (i = 0; i < 4; i++) {
538 if (devc->channel_mask & (0xff << (i * 8))) {
acc885c7
BV
539 pols_changrp_mask |= (1 << i);
540 num_pols_changrp++;
4bd80e12 541 }
542 }
b94cff40 543 /* 3 channel groups takes as many bytes as 4 channel groups */
acc885c7
BV
544 if (num_pols_changrp == 3)
545 num_pols_changrp = 4;
b94cff40 546 /* maximum number of samples (or RLE counts) the buffer memory can hold */
acc885c7 547 devc->max_samples = devc->max_samplebytes / num_pols_changrp;
4bd80e12 548
549 /*
550 * Limit readcount to prevent reading past the end of the hardware
551 * buffer.
552 */
553 sr_dbg("max_samples = %d", devc->max_samples);
6433156c 554 sr_dbg("limit_samples = %" PRIu64, devc->limit_samples);
b94cff40 555 samplecount = MIN(devc->max_samples, devc->limit_samples);
4bd80e12 556 sr_dbg("Samplecount = %d", samplecount);
557
b94cff40 558 /* In demux mode the OLS is processing two samples per clock */
559 if (devc->flag_reg & FLAG_DEMUX) {
560 samplespercount = 8;
561 }
562 else {
563 samplespercount = 4;
564 }
565
566 readcount = samplecount / samplespercount;
567
4bd80e12 568 /* Rather read too many samples than too few. */
b94cff40 569 if (samplecount % samplespercount != 0)
4bd80e12 570 readcount++;
571
572 /* Basic triggers. */
acc885c7
BV
573 if (pols_convert_trigger(sdi) != SR_OK) {
574 sr_err("Failed to configure channels.");
575 return SR_ERR;
576 }
84cbaf77 577
acc885c7 578 if (devc->num_stages > 0) {
4bd80e12 579 delaycount = readcount * (1 - devc->capture_ratio / 100.0);
b94cff40 580 devc->trigger_at = (readcount - delaycount) * samplespercount - devc->num_stages;
84cbaf77
BV
581 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
582 if (i <= devc->num_stages) {
583 sr_dbg("Setting p-ols stage %d trigger.", i);
584 if ((ret = set_trigger(sdi, i)) != SR_OK)
585 return ret;
586 }
587 else {
588 sr_dbg("Disabling p-ols stage %d trigger.", i);
589 if ((ret = disable_trigger(sdi, i)) != SR_OK)
590 return ret;
591 }
4bd80e12 592 }
593 } else {
594 /* No triggers configured, force trigger on first stage. */
595 sr_dbg("Forcing trigger at stage 0.");
596 if ((ret = set_trigger(sdi, 0)) != SR_OK)
597 return ret;
598 delaycount = readcount;
599 }
600
601 /* Samplerate. */
602 sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
603 devc->cur_samplerate, devc->cur_samplerate_divider);
604 arg[0] = devc->cur_samplerate_divider & 0xff;
605 arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8;
606 arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16;
607 arg[3] = 0x00;
608 if (write_longcommand(devc, CMD_SET_DIVIDER, arg) != SR_OK)
609 return SR_ERR;
acc885c7 610
4bd80e12 611 /* Send extended sample limit and pre/post-trigger capture ratio. */
612 arg[0] = ((readcount - 1) & 0xff);
613 arg[1] = ((readcount - 1) & 0xff00) >> 8;
614 arg[2] = ((readcount - 1) & 0xff0000) >> 16;
615 arg[3] = ((readcount - 1) & 0xff000000) >> 24;
1e0de846 616 if (write_longcommand(devc, CMD_CAPTURE_DELAY, arg) != SR_OK)
4bd80e12 617 return SR_ERR;
618 arg[0] = ((delaycount - 1) & 0xff);
619 arg[1] = ((delaycount - 1) & 0xff00) >> 8;
620 arg[2] = ((delaycount - 1) & 0xff0000) >> 16;
621 arg[3] = ((delaycount - 1) & 0xff000000) >> 24;
1e0de846 622 if (write_longcommand(devc, CMD_CAPTURE_COUNT, arg) != SR_OK)
4bd80e12 623 return SR_ERR;
acc885c7 624
4bd80e12 625 /* Flag register. */
626 sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
627 devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off",
628 devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off",
629 devc->flag_reg & FLAG_RLE ? "on" : "off",
630 devc->flag_reg & FLAG_FILTER ? "on": "off",
631 devc->flag_reg & FLAG_DEMUX ? "on" : "off");
632
b94cff40 633 /*
634 * Enable/disable OLS channel groups in the flag register according
635 * to the channel mask. 1 means "disable channel".
636 */
637 devc->flag_reg &= ~0x3c;
acc885c7 638 devc->flag_reg |= ~(pols_changrp_mask << 2) & 0x3c;
b94cff40 639 sr_dbg("flag_reg = %x", devc->flag_reg);
640
641 /*
176d785d
UH
642 * In demux mode the OLS is processing two 8-bit or 16-bit samples
643 * in parallel and for this to work the lower two bits of the four
b94cff40 644 * "channel_disable" bits must be replicated to the upper two bits.
645 */
646 flag_tmp = devc->flag_reg;
647 if (devc->flag_reg & FLAG_DEMUX) {
648 flag_tmp &= ~0x30;
acc885c7 649 flag_tmp |= ~(pols_changrp_mask << 4) & 0x30;
b94cff40 650 }
651 arg[0] = flag_tmp & 0xff;
652 arg[1] = flag_tmp >> 8;
4bd80e12 653 arg[2] = arg[3] = 0x00;
654 if (write_longcommand(devc, CMD_SET_FLAGS, arg) != SR_OK)
655 return SR_ERR;
656
657 /* Start acquisition on the device. */
658 if (write_shortcommand(devc, CMD_RUN) != SR_OK)
659 return SR_ERR;
660
661 /* Reset all operational states. */
662 devc->rle_count = devc->num_transfers = 0;
663 devc->num_samples = devc->num_bytes = 0;
664 devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0;
665 memset(devc->sample, 0, 4);
666
bee2b016 667 std_session_send_df_header(sdi);
4bd80e12 668
669 /* Hook up a dummy handler to receive data from the device. */
c650d3ec 670 sr_session_source_add(sdi->session, -1, 0, 10, p_ols_receive_data,
695dc859 671 (struct sr_dev_inst *)sdi);
4bd80e12 672
673 return SR_OK;
674}
675
695dc859 676static int dev_acquisition_stop(struct sr_dev_inst *sdi)
4bd80e12 677{
678 struct dev_context *devc;
4bd80e12 679
680 devc = sdi->priv;
681
4bd80e12 682 write_shortcommand(devc, CMD_RESET);
683 write_shortcommand(devc, CMD_RESET);
684 write_shortcommand(devc, CMD_RESET);
685 write_shortcommand(devc, CMD_RESET);
686 write_shortcommand(devc, CMD_RESET);
687
dd7a4a71 688 sr_session_source_remove(sdi->session, -1);
4bd80e12 689
bee2b016 690 std_session_send_df_end(sdi);
4bd80e12 691
692 return SR_OK;
693}
694
695SR_PRIV struct sr_dev_driver p_ols_driver_info = {
acc885c7 696 .name = "p-ols",
4bd80e12 697 .longname = "Pipistrello OLS",
698 .api_version = 1,
c2fdcc25 699 .init = std_init,
700d6b64 700 .cleanup = std_cleanup,
4bd80e12 701 .scan = scan,
c01bf34c 702 .dev_list = std_dev_list,
4bd80e12 703 .dev_clear = dev_clear,
704 .config_get = config_get,
705 .config_set = config_set,
706 .config_list = config_list,
707 .dev_open = dev_open,
708 .dev_close = dev_close,
709 .dev_acquisition_start = dev_acquisition_start,
710 .dev_acquisition_stop = dev_acquisition_stop,
41812aca 711 .context = NULL,
4bd80e12 712};
dd5c48a6 713SR_REGISTER_DEV_DRIVER(p_ols_driver_info);