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4bd80e12 | 1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
5 | * | |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 3 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
6ec6c43b | 20 | #include <config.h> |
4bd80e12 | 21 | #include "protocol.h" |
22 | ||
05199c0a | 23 | static const uint32_t drvopts[] = { |
4bd80e12 | 24 | SR_CONF_LOGIC_ANALYZER, |
05199c0a UH |
25 | }; |
26 | ||
27 | static const uint32_t devopts[] = { | |
5827f61b BV |
28 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
29 | SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
30 | SR_CONF_TRIGGER_MATCH | SR_CONF_LIST, | |
31 | SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET, | |
32 | SR_CONF_PATTERN_MODE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
33 | SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET, | |
34 | SR_CONF_SWAP | SR_CONF_SET, | |
35 | SR_CONF_RLE | SR_CONF_GET | SR_CONF_SET, | |
4bd80e12 | 36 | }; |
37 | ||
acc885c7 BV |
38 | static const int32_t trigger_matches[] = { |
39 | SR_TRIGGER_ZERO, | |
40 | SR_TRIGGER_ONE, | |
41 | SR_TRIGGER_RISING, | |
42 | SR_TRIGGER_FALLING, | |
43 | }; | |
44 | ||
4bd80e12 | 45 | #define STR_PATTERN_NONE "None" |
46 | #define STR_PATTERN_EXTERNAL "External" | |
47 | #define STR_PATTERN_INTERNAL "Internal" | |
48 | ||
49 | /* Supported methods of test pattern outputs */ | |
50 | enum { | |
51 | /** | |
52 | * Capture pins 31:16 (unbuffered wing) output a test pattern | |
53 | * that can captured on pins 0:15. | |
54 | */ | |
55 | PATTERN_EXTERNAL, | |
56 | ||
57 | /** Route test pattern internally to capture buffer. */ | |
58 | PATTERN_INTERNAL, | |
59 | }; | |
60 | ||
61 | static const char *patterns[] = { | |
62 | STR_PATTERN_NONE, | |
63 | STR_PATTERN_EXTERNAL, | |
64 | STR_PATTERN_INTERNAL, | |
65 | }; | |
66 | ||
67 | /* Channels are numbered 0-31 (on the PCB silkscreen). */ | |
53cda65a | 68 | SR_PRIV const char *p_ols_channel_names[] = { |
4bd80e12 | 69 | "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", |
70 | "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23", | |
71 | "24", "25", "26", "27", "28", "29", "30", "31", | |
4bd80e12 | 72 | }; |
73 | ||
74 | /* Default supported samplerates, can be overridden by device metadata. */ | |
75 | static const uint64_t samplerates[] = { | |
76 | SR_HZ(10), | |
77 | SR_MHZ(200), | |
78 | SR_HZ(1), | |
79 | }; | |
80 | ||
4f840ce9 | 81 | static GSList *scan(struct sr_dev_driver *di, GSList *options) |
4bd80e12 | 82 | { |
83 | struct sr_dev_inst *sdi; | |
4bd80e12 | 84 | struct dev_context *devc; |
85 | GSList *devices; | |
86 | int ret, i; | |
87 | char buf[70]; | |
88 | int bytes_read; | |
89 | ||
90 | (void)options; | |
91 | ||
4bd80e12 | 92 | devices = NULL; |
93 | ||
f57d8ffe | 94 | devc = g_malloc0(sizeof(struct dev_context)); |
4bd80e12 | 95 | |
b94cff40 | 96 | devc->max_samplebytes = devc->max_samplerate = devc->protocol_version = 0; |
4bd80e12 | 97 | |
4bd80e12 | 98 | devc->limit_samples = devc->capture_ratio = 0; |
99 | devc->trigger_at = -1; | |
100 | devc->channel_mask = 0xffffffff; | |
101 | devc->flag_reg = 0; | |
102 | ||
a95f142e | 103 | devc->ftdi_buf = g_malloc0(FTDI_BUF_SIZE); |
4bd80e12 | 104 | |
4bd80e12 | 105 | if (!(devc->ftdic = ftdi_new())) { |
106 | sr_err("Failed to initialize libftdi."); | |
107 | goto err_free_ftdi_buf;; | |
108 | } | |
109 | ||
ca314e06 | 110 | if (p_ols_open(devc) != SR_OK) |
4bd80e12 | 111 | goto err_free_ftdic; |
176d785d | 112 | |
4bd80e12 | 113 | /* The discovery procedure is like this: first send the Reset |
114 | * command (0x00) 5 times, since the device could be anywhere | |
115 | * in a 5-byte command. Then send the ID command (0x02). | |
116 | * If the device responds with 4 bytes ("OLS1" or "SLA1"), we | |
117 | * have a match. | |
118 | */ | |
119 | ||
120 | ret = SR_OK; | |
121 | for (i = 0; i < 5; i++) { | |
122 | if ((ret = write_shortcommand(devc, CMD_RESET)) != SR_OK) { | |
123 | break; | |
124 | } | |
125 | } | |
126 | if (ret != SR_OK) { | |
127 | sr_err("Could not reset device. Quitting."); | |
128 | goto err_close_ftdic; | |
129 | } | |
130 | write_shortcommand(devc, CMD_ID); | |
131 | ||
132 | /* Read the response data. */ | |
133 | bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 4); | |
134 | if (bytes_read < 0) { | |
135 | sr_err("Failed to read FTDI data (%d): %s.", | |
136 | bytes_read, ftdi_get_error_string(devc->ftdic)); | |
137 | goto err_close_ftdic; | |
138 | } | |
139 | if (bytes_read == 0) { | |
140 | goto err_close_ftdic; | |
141 | } | |
142 | ||
143 | if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4)) | |
144 | goto err_close_ftdic; | |
145 | ||
146 | /* Definitely using the OLS protocol, check if it supports | |
147 | * the metadata command. | |
148 | */ | |
149 | write_shortcommand(devc, CMD_METADATA); | |
150 | ||
151 | /* Read the metadata. */ | |
152 | bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 64); | |
153 | if (bytes_read < 0) { | |
154 | sr_err("Failed to read FTDI data (%d): %s.", | |
155 | bytes_read, ftdi_get_error_string(devc->ftdic)); | |
156 | goto err_close_ftdic; | |
157 | } | |
158 | if (bytes_read == 0) { | |
159 | goto err_close_ftdic; | |
160 | } | |
161 | ||
4bd80e12 | 162 | p_ols_close(devc); |
163 | ||
164 | /* Parse the metadata. */ | |
165 | sdi = p_ols_get_metadata((uint8_t *)buf, bytes_read, devc); | |
4bd80e12 | 166 | |
167 | /* Configure samplerate and divider. */ | |
168 | if (p_ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK) | |
169 | sr_dbg("Failed to set default samplerate (%"PRIu64").", | |
170 | DEFAULT_SAMPLERATE); | |
4bd80e12 | 171 | |
4bd80e12 | 172 | devices = g_slist_append(devices, sdi); |
173 | ||
15a5bfe4 | 174 | return std_scan_complete(di, devices); |
4bd80e12 | 175 | |
176 | err_close_ftdic: | |
177 | p_ols_close(devc); | |
178 | err_free_ftdic: | |
ca314e06 | 179 | ftdi_free(devc->ftdic); |
4bd80e12 | 180 | err_free_ftdi_buf: |
181 | g_free(devc->ftdi_buf); | |
4bd80e12 | 182 | g_free(devc); |
4bd80e12 | 183 | |
184 | return NULL; | |
185 | } | |
186 | ||
3553451f | 187 | static void clear_helper(struct dev_context *devc) |
4bd80e12 | 188 | { |
4bd80e12 | 189 | ftdi_free(devc->ftdic); |
190 | g_free(devc->ftdi_buf); | |
191 | } | |
192 | ||
4f840ce9 | 193 | static int dev_clear(const struct sr_dev_driver *di) |
4bd80e12 | 194 | { |
3553451f | 195 | return std_dev_clear_with_callback(di, (std_dev_clear_callback)clear_helper); |
4bd80e12 | 196 | } |
197 | ||
dd7a72ea UH |
198 | static int config_get(uint32_t key, GVariant **data, |
199 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
4bd80e12 | 200 | { |
201 | struct dev_context *devc; | |
202 | ||
203 | (void)cg; | |
204 | ||
205 | if (!sdi) | |
206 | return SR_ERR_ARG; | |
207 | ||
208 | devc = sdi->priv; | |
758906aa | 209 | |
584560f1 | 210 | switch (key) { |
4bd80e12 | 211 | case SR_CONF_SAMPLERATE: |
212 | *data = g_variant_new_uint64(devc->cur_samplerate); | |
213 | break; | |
214 | case SR_CONF_CAPTURE_RATIO: | |
215 | *data = g_variant_new_uint64(devc->capture_ratio); | |
216 | break; | |
217 | case SR_CONF_LIMIT_SAMPLES: | |
218 | *data = g_variant_new_uint64(devc->limit_samples); | |
219 | break; | |
220 | case SR_CONF_PATTERN_MODE: | |
221 | if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE) | |
222 | *data = g_variant_new_string(STR_PATTERN_EXTERNAL); | |
223 | else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE) | |
224 | *data = g_variant_new_string(STR_PATTERN_INTERNAL); | |
225 | else | |
226 | *data = g_variant_new_string(STR_PATTERN_NONE); | |
227 | break; | |
228 | case SR_CONF_RLE: | |
229 | *data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE); | |
230 | break; | |
231 | case SR_CONF_EXTERNAL_CLOCK: | |
232 | *data = g_variant_new_boolean(devc->flag_reg & FLAG_CLOCK_EXTERNAL ? TRUE : FALSE); | |
233 | break; | |
234 | default: | |
235 | return SR_ERR_NA; | |
236 | } | |
237 | ||
238 | return SR_OK; | |
239 | } | |
240 | ||
dd7a72ea UH |
241 | static int config_set(uint32_t key, GVariant *data, |
242 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
4bd80e12 | 243 | { |
244 | struct dev_context *devc; | |
245 | uint16_t flag; | |
246 | uint64_t tmp_u64; | |
4bd80e12 | 247 | const char *stropt; |
248 | ||
249 | (void)cg; | |
250 | ||
4bd80e12 | 251 | devc = sdi->priv; |
252 | ||
584560f1 | 253 | switch (key) { |
4bd80e12 | 254 | case SR_CONF_SAMPLERATE: |
255 | tmp_u64 = g_variant_get_uint64(data); | |
256 | if (tmp_u64 < samplerates[0] || tmp_u64 > samplerates[1]) | |
257 | return SR_ERR_SAMPLERATE; | |
758906aa | 258 | return p_ols_set_samplerate(sdi, g_variant_get_uint64(data)); |
4bd80e12 | 259 | case SR_CONF_LIMIT_SAMPLES: |
260 | tmp_u64 = g_variant_get_uint64(data); | |
261 | if (tmp_u64 < MIN_NUM_SAMPLES) | |
262 | return SR_ERR; | |
263 | devc->limit_samples = tmp_u64; | |
4bd80e12 | 264 | break; |
265 | case SR_CONF_CAPTURE_RATIO: | |
266 | devc->capture_ratio = g_variant_get_uint64(data); | |
4bd80e12 | 267 | break; |
268 | case SR_CONF_EXTERNAL_CLOCK: | |
269 | if (g_variant_get_boolean(data)) { | |
270 | sr_info("Enabling external clock."); | |
271 | devc->flag_reg |= FLAG_CLOCK_EXTERNAL; | |
272 | } else { | |
273 | sr_info("Disabled external clock."); | |
274 | devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL; | |
275 | } | |
4bd80e12 | 276 | break; |
277 | case SR_CONF_PATTERN_MODE: | |
278 | stropt = g_variant_get_string(data, NULL); | |
4bd80e12 | 279 | flag = 0xffff; |
280 | if (!strcmp(stropt, STR_PATTERN_NONE)) { | |
281 | sr_info("Disabling test modes."); | |
282 | flag = 0x0000; | |
758906aa | 283 | } else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) { |
4bd80e12 | 284 | sr_info("Enabling internal test mode."); |
285 | flag = FLAG_INTERNAL_TEST_MODE; | |
286 | } else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) { | |
287 | sr_info("Enabling external test mode."); | |
288 | flag = FLAG_EXTERNAL_TEST_MODE; | |
289 | } else { | |
758906aa | 290 | return SR_ERR; |
4bd80e12 | 291 | } |
292 | if (flag != 0xffff) { | |
293 | devc->flag_reg &= ~(FLAG_INTERNAL_TEST_MODE | FLAG_EXTERNAL_TEST_MODE); | |
294 | devc->flag_reg |= flag; | |
295 | } | |
296 | break; | |
297 | case SR_CONF_SWAP: | |
298 | if (g_variant_get_boolean(data)) { | |
299 | sr_info("Enabling channel swapping."); | |
300 | devc->flag_reg |= FLAG_SWAP_CHANNELS; | |
301 | } else { | |
302 | sr_info("Disabling channel swapping."); | |
303 | devc->flag_reg &= ~FLAG_SWAP_CHANNELS; | |
304 | } | |
4bd80e12 | 305 | break; |
4bd80e12 | 306 | case SR_CONF_RLE: |
307 | if (g_variant_get_boolean(data)) { | |
308 | sr_info("Enabling RLE."); | |
309 | devc->flag_reg |= FLAG_RLE; | |
310 | } else { | |
311 | sr_info("Disabling RLE."); | |
312 | devc->flag_reg &= ~FLAG_RLE; | |
313 | } | |
4bd80e12 | 314 | break; |
315 | default: | |
758906aa | 316 | return SR_ERR_NA; |
4bd80e12 | 317 | } |
318 | ||
758906aa | 319 | return SR_OK; |
4bd80e12 | 320 | } |
321 | ||
dd7a72ea UH |
322 | static int config_list(uint32_t key, GVariant **data, |
323 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
4bd80e12 | 324 | { |
325 | struct dev_context *devc; | |
acc885c7 | 326 | int num_pols_changrp, i; |
4bd80e12 | 327 | |
4bd80e12 | 328 | switch (key) { |
329 | case SR_CONF_DEVICE_OPTIONS: | |
05199c0a | 330 | return STD_CONFIG_LIST(key, data, sdi, cg, NULL, drvopts, devopts); |
4bd80e12 | 331 | case SR_CONF_SAMPLERATE: |
53012da6 | 332 | *data = std_gvar_samplerates_steps(ARRAY_AND_SIZE(samplerates)); |
4bd80e12 | 333 | break; |
acc885c7 | 334 | case SR_CONF_TRIGGER_MATCH: |
53012da6 | 335 | *data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches)); |
4bd80e12 | 336 | break; |
337 | case SR_CONF_PATTERN_MODE: | |
53012da6 | 338 | *data = g_variant_new_strv(ARRAY_AND_SIZE(patterns)); |
4bd80e12 | 339 | break; |
340 | case SR_CONF_LIMIT_SAMPLES: | |
341 | if (!sdi) | |
342 | return SR_ERR_ARG; | |
343 | devc = sdi->priv; | |
344 | if (devc->flag_reg & FLAG_RLE) | |
345 | return SR_ERR_NA; | |
b94cff40 | 346 | if (devc->max_samplebytes == 0) |
4bd80e12 | 347 | /* Device didn't specify sample memory size in metadata. */ |
348 | return SR_ERR_NA; | |
349 | /* | |
350 | * Channel groups are turned off if no channels in that group are | |
351 | * enabled, making more room for samples for the enabled group. | |
352 | */ | |
acc885c7 BV |
353 | pols_channel_mask(sdi); |
354 | num_pols_changrp = 0; | |
4bd80e12 | 355 | for (i = 0; i < 4; i++) { |
356 | if (devc->channel_mask & (0xff << (i * 8))) | |
acc885c7 | 357 | num_pols_changrp++; |
4bd80e12 | 358 | } |
b94cff40 | 359 | /* 3 channel groups takes as many bytes as 4 channel groups */ |
acc885c7 BV |
360 | if (num_pols_changrp == 3) |
361 | num_pols_changrp = 4; | |
a162eeb2 UH |
362 | |
363 | *data = std_gvar_tuple_u64(MIN_NUM_SAMPLES, | |
364 | (num_pols_changrp) ? devc->max_samplebytes / num_pols_changrp : MIN_NUM_SAMPLES); | |
4bd80e12 | 365 | break; |
366 | default: | |
367 | return SR_ERR_NA; | |
368 | } | |
369 | ||
370 | return SR_OK; | |
371 | } | |
372 | ||
373 | static int dev_open(struct sr_dev_inst *sdi) | |
374 | { | |
375 | struct dev_context *devc; | |
4bd80e12 | 376 | |
377 | devc = sdi->priv; | |
378 | ||
7e463623 | 379 | return p_ols_open(devc); |
4bd80e12 | 380 | } |
381 | ||
382 | static int dev_close(struct sr_dev_inst *sdi) | |
383 | { | |
4bd80e12 | 384 | struct dev_context *devc; |
385 | ||
4bd80e12 | 386 | devc = sdi->priv; |
387 | ||
093e1cba | 388 | return p_ols_close(devc); |
4bd80e12 | 389 | } |
390 | ||
4bd80e12 | 391 | static int set_trigger(const struct sr_dev_inst *sdi, int stage) |
392 | { | |
393 | struct dev_context *devc; | |
394 | uint8_t cmd, arg[4]; | |
395 | ||
396 | devc = sdi->priv; | |
397 | ||
398 | cmd = CMD_SET_TRIGGER_MASK + stage * 4; | |
399 | arg[0] = devc->trigger_mask[stage] & 0xff; | |
400 | arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff; | |
401 | arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff; | |
402 | arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff; | |
403 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
404 | return SR_ERR; | |
405 | ||
406 | cmd = CMD_SET_TRIGGER_VALUE + stage * 4; | |
407 | arg[0] = devc->trigger_value[stage] & 0xff; | |
408 | arg[1] = (devc->trigger_value[stage] >> 8) & 0xff; | |
409 | arg[2] = (devc->trigger_value[stage] >> 16) & 0xff; | |
410 | arg[3] = (devc->trigger_value[stage] >> 24) & 0xff; | |
411 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
412 | return SR_ERR; | |
413 | ||
414 | cmd = CMD_SET_TRIGGER_CONFIG + stage * 4; | |
415 | arg[0] = arg[1] = arg[3] = 0x00; | |
416 | arg[2] = stage; | |
417 | if (stage == devc->num_stages) | |
418 | /* Last stage, fire when this one matches. */ | |
419 | arg[3] |= TRIGGER_START; | |
420 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
421 | return SR_ERR; | |
422 | ||
1e0de846 | 423 | cmd = CMD_SET_TRIGGER_EDGE + stage * 4; |
424 | arg[0] = devc->trigger_edge[stage] & 0xff; | |
425 | arg[1] = (devc->trigger_edge[stage] >> 8) & 0xff; | |
426 | arg[2] = (devc->trigger_edge[stage] >> 16) & 0xff; | |
427 | arg[3] = (devc->trigger_edge[stage] >> 24) & 0xff; | |
428 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
429 | return SR_ERR; | |
430 | ||
4bd80e12 | 431 | return SR_OK; |
432 | } | |
433 | ||
84cbaf77 BV |
434 | static int disable_trigger(const struct sr_dev_inst *sdi, int stage) |
435 | { | |
436 | struct dev_context *devc; | |
437 | uint8_t cmd, arg[4]; | |
438 | ||
439 | devc = sdi->priv; | |
440 | ||
441 | cmd = CMD_SET_TRIGGER_MASK + stage * 4; | |
442 | arg[0] = arg[1] = arg[2] = arg[3] = 0x00; | |
443 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
444 | return SR_ERR; | |
445 | ||
446 | cmd = CMD_SET_TRIGGER_VALUE + stage * 4; | |
447 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
448 | return SR_ERR; | |
449 | ||
450 | cmd = CMD_SET_TRIGGER_CONFIG + stage * 4; | |
451 | arg[2] = 0x03; | |
452 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
453 | return SR_ERR; | |
454 | ||
455 | cmd = CMD_SET_TRIGGER_EDGE + stage * 4; | |
456 | arg[2] = 0x00; | |
457 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
458 | return SR_ERR; | |
459 | ||
460 | return SR_OK; | |
461 | } | |
462 | ||
695dc859 | 463 | static int dev_acquisition_start(const struct sr_dev_inst *sdi) |
4bd80e12 | 464 | { |
465 | struct dev_context *devc; | |
466 | uint32_t samplecount, readcount, delaycount; | |
acc885c7 | 467 | uint8_t pols_changrp_mask, arg[4]; |
b94cff40 | 468 | uint16_t flag_tmp; |
acc885c7 | 469 | int num_pols_changrp, samplespercount; |
4bd80e12 | 470 | int ret, i; |
471 | ||
4bd80e12 | 472 | devc = sdi->priv; |
473 | ||
acc885c7 | 474 | pols_channel_mask(sdi); |
4bd80e12 | 475 | |
476 | /* | |
477 | * Enable/disable channel groups in the flag register according to the | |
acc885c7 BV |
478 | * channel mask. Calculate this here, because num_pols_changrp is |
479 | * needed to limit readcount. | |
4bd80e12 | 480 | */ |
acc885c7 BV |
481 | pols_changrp_mask = 0; |
482 | num_pols_changrp = 0; | |
4bd80e12 | 483 | for (i = 0; i < 4; i++) { |
484 | if (devc->channel_mask & (0xff << (i * 8))) { | |
acc885c7 BV |
485 | pols_changrp_mask |= (1 << i); |
486 | num_pols_changrp++; | |
4bd80e12 | 487 | } |
488 | } | |
b94cff40 | 489 | /* 3 channel groups takes as many bytes as 4 channel groups */ |
acc885c7 BV |
490 | if (num_pols_changrp == 3) |
491 | num_pols_changrp = 4; | |
b94cff40 | 492 | /* maximum number of samples (or RLE counts) the buffer memory can hold */ |
acc885c7 | 493 | devc->max_samples = devc->max_samplebytes / num_pols_changrp; |
4bd80e12 | 494 | |
495 | /* | |
496 | * Limit readcount to prevent reading past the end of the hardware | |
497 | * buffer. | |
498 | */ | |
499 | sr_dbg("max_samples = %d", devc->max_samples); | |
6433156c | 500 | sr_dbg("limit_samples = %" PRIu64, devc->limit_samples); |
b94cff40 | 501 | samplecount = MIN(devc->max_samples, devc->limit_samples); |
4bd80e12 | 502 | sr_dbg("Samplecount = %d", samplecount); |
503 | ||
b94cff40 | 504 | /* In demux mode the OLS is processing two samples per clock */ |
505 | if (devc->flag_reg & FLAG_DEMUX) { | |
506 | samplespercount = 8; | |
507 | } | |
508 | else { | |
509 | samplespercount = 4; | |
510 | } | |
511 | ||
512 | readcount = samplecount / samplespercount; | |
513 | ||
4bd80e12 | 514 | /* Rather read too many samples than too few. */ |
b94cff40 | 515 | if (samplecount % samplespercount != 0) |
4bd80e12 | 516 | readcount++; |
517 | ||
518 | /* Basic triggers. */ | |
acc885c7 BV |
519 | if (pols_convert_trigger(sdi) != SR_OK) { |
520 | sr_err("Failed to configure channels."); | |
521 | return SR_ERR; | |
522 | } | |
84cbaf77 | 523 | |
acc885c7 | 524 | if (devc->num_stages > 0) { |
4bd80e12 | 525 | delaycount = readcount * (1 - devc->capture_ratio / 100.0); |
b94cff40 | 526 | devc->trigger_at = (readcount - delaycount) * samplespercount - devc->num_stages; |
84cbaf77 BV |
527 | for (i = 0; i < NUM_TRIGGER_STAGES; i++) { |
528 | if (i <= devc->num_stages) { | |
529 | sr_dbg("Setting p-ols stage %d trigger.", i); | |
530 | if ((ret = set_trigger(sdi, i)) != SR_OK) | |
531 | return ret; | |
532 | } | |
533 | else { | |
534 | sr_dbg("Disabling p-ols stage %d trigger.", i); | |
535 | if ((ret = disable_trigger(sdi, i)) != SR_OK) | |
536 | return ret; | |
537 | } | |
4bd80e12 | 538 | } |
539 | } else { | |
540 | /* No triggers configured, force trigger on first stage. */ | |
541 | sr_dbg("Forcing trigger at stage 0."); | |
542 | if ((ret = set_trigger(sdi, 0)) != SR_OK) | |
543 | return ret; | |
544 | delaycount = readcount; | |
545 | } | |
546 | ||
547 | /* Samplerate. */ | |
548 | sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)", | |
549 | devc->cur_samplerate, devc->cur_samplerate_divider); | |
550 | arg[0] = devc->cur_samplerate_divider & 0xff; | |
551 | arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8; | |
552 | arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16; | |
553 | arg[3] = 0x00; | |
554 | if (write_longcommand(devc, CMD_SET_DIVIDER, arg) != SR_OK) | |
555 | return SR_ERR; | |
acc885c7 | 556 | |
4bd80e12 | 557 | /* Send extended sample limit and pre/post-trigger capture ratio. */ |
558 | arg[0] = ((readcount - 1) & 0xff); | |
559 | arg[1] = ((readcount - 1) & 0xff00) >> 8; | |
560 | arg[2] = ((readcount - 1) & 0xff0000) >> 16; | |
561 | arg[3] = ((readcount - 1) & 0xff000000) >> 24; | |
1e0de846 | 562 | if (write_longcommand(devc, CMD_CAPTURE_DELAY, arg) != SR_OK) |
4bd80e12 | 563 | return SR_ERR; |
564 | arg[0] = ((delaycount - 1) & 0xff); | |
565 | arg[1] = ((delaycount - 1) & 0xff00) >> 8; | |
566 | arg[2] = ((delaycount - 1) & 0xff0000) >> 16; | |
567 | arg[3] = ((delaycount - 1) & 0xff000000) >> 24; | |
1e0de846 | 568 | if (write_longcommand(devc, CMD_CAPTURE_COUNT, arg) != SR_OK) |
4bd80e12 | 569 | return SR_ERR; |
acc885c7 | 570 | |
4bd80e12 | 571 | /* Flag register. */ |
572 | sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s", | |
573 | devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off", | |
574 | devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off", | |
575 | devc->flag_reg & FLAG_RLE ? "on" : "off", | |
576 | devc->flag_reg & FLAG_FILTER ? "on": "off", | |
577 | devc->flag_reg & FLAG_DEMUX ? "on" : "off"); | |
578 | ||
b94cff40 | 579 | /* |
580 | * Enable/disable OLS channel groups in the flag register according | |
581 | * to the channel mask. 1 means "disable channel". | |
582 | */ | |
583 | devc->flag_reg &= ~0x3c; | |
acc885c7 | 584 | devc->flag_reg |= ~(pols_changrp_mask << 2) & 0x3c; |
b94cff40 | 585 | sr_dbg("flag_reg = %x", devc->flag_reg); |
586 | ||
587 | /* | |
176d785d UH |
588 | * In demux mode the OLS is processing two 8-bit or 16-bit samples |
589 | * in parallel and for this to work the lower two bits of the four | |
b94cff40 | 590 | * "channel_disable" bits must be replicated to the upper two bits. |
591 | */ | |
592 | flag_tmp = devc->flag_reg; | |
593 | if (devc->flag_reg & FLAG_DEMUX) { | |
594 | flag_tmp &= ~0x30; | |
acc885c7 | 595 | flag_tmp |= ~(pols_changrp_mask << 4) & 0x30; |
b94cff40 | 596 | } |
597 | arg[0] = flag_tmp & 0xff; | |
598 | arg[1] = flag_tmp >> 8; | |
4bd80e12 | 599 | arg[2] = arg[3] = 0x00; |
600 | if (write_longcommand(devc, CMD_SET_FLAGS, arg) != SR_OK) | |
601 | return SR_ERR; | |
602 | ||
603 | /* Start acquisition on the device. */ | |
604 | if (write_shortcommand(devc, CMD_RUN) != SR_OK) | |
605 | return SR_ERR; | |
606 | ||
607 | /* Reset all operational states. */ | |
608 | devc->rle_count = devc->num_transfers = 0; | |
609 | devc->num_samples = devc->num_bytes = 0; | |
610 | devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0; | |
611 | memset(devc->sample, 0, 4); | |
612 | ||
bee2b016 | 613 | std_session_send_df_header(sdi); |
4bd80e12 | 614 | |
615 | /* Hook up a dummy handler to receive data from the device. */ | |
c650d3ec | 616 | sr_session_source_add(sdi->session, -1, 0, 10, p_ols_receive_data, |
695dc859 | 617 | (struct sr_dev_inst *)sdi); |
4bd80e12 | 618 | |
619 | return SR_OK; | |
620 | } | |
621 | ||
695dc859 | 622 | static int dev_acquisition_stop(struct sr_dev_inst *sdi) |
4bd80e12 | 623 | { |
624 | struct dev_context *devc; | |
4bd80e12 | 625 | |
626 | devc = sdi->priv; | |
627 | ||
4bd80e12 | 628 | write_shortcommand(devc, CMD_RESET); |
629 | write_shortcommand(devc, CMD_RESET); | |
630 | write_shortcommand(devc, CMD_RESET); | |
631 | write_shortcommand(devc, CMD_RESET); | |
632 | write_shortcommand(devc, CMD_RESET); | |
633 | ||
dd7a4a71 | 634 | sr_session_source_remove(sdi->session, -1); |
4bd80e12 | 635 | |
bee2b016 | 636 | std_session_send_df_end(sdi); |
4bd80e12 | 637 | |
638 | return SR_OK; | |
639 | } | |
640 | ||
641 | SR_PRIV struct sr_dev_driver p_ols_driver_info = { | |
acc885c7 | 642 | .name = "p-ols", |
4bd80e12 | 643 | .longname = "Pipistrello OLS", |
644 | .api_version = 1, | |
c2fdcc25 | 645 | .init = std_init, |
700d6b64 | 646 | .cleanup = std_cleanup, |
4bd80e12 | 647 | .scan = scan, |
c01bf34c | 648 | .dev_list = std_dev_list, |
4bd80e12 | 649 | .dev_clear = dev_clear, |
650 | .config_get = config_get, | |
651 | .config_set = config_set, | |
652 | .config_list = config_list, | |
653 | .dev_open = dev_open, | |
654 | .dev_close = dev_close, | |
655 | .dev_acquisition_start = dev_acquisition_start, | |
656 | .dev_acquisition_stop = dev_acquisition_stop, | |
41812aca | 657 | .context = NULL, |
4bd80e12 | 658 | }; |
dd5c48a6 | 659 | SR_REGISTER_DEV_DRIVER(p_ols_driver_info); |