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Remove sdi->index from openbench-logic-sniffer and pipistrello-ols
[libsigrok.git] / src / hardware / pipistrello-ols / api.c
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4bd80e12 1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "protocol.h"
21
f254bc4b 22static const uint32_t devopts[] = {
4bd80e12 23 SR_CONF_LOGIC_ANALYZER,
5827f61b
BV
24 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
25 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
26 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
27 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
28 SR_CONF_PATTERN_MODE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
29 SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET,
30 SR_CONF_SWAP | SR_CONF_SET,
31 SR_CONF_RLE | SR_CONF_GET | SR_CONF_SET,
4bd80e12 32};
33
acc885c7
BV
34static const int32_t trigger_matches[] = {
35 SR_TRIGGER_ZERO,
36 SR_TRIGGER_ONE,
37 SR_TRIGGER_RISING,
38 SR_TRIGGER_FALLING,
39};
40
4bd80e12 41#define STR_PATTERN_NONE "None"
42#define STR_PATTERN_EXTERNAL "External"
43#define STR_PATTERN_INTERNAL "Internal"
44
45/* Supported methods of test pattern outputs */
46enum {
47 /**
48 * Capture pins 31:16 (unbuffered wing) output a test pattern
49 * that can captured on pins 0:15.
50 */
51 PATTERN_EXTERNAL,
52
53 /** Route test pattern internally to capture buffer. */
54 PATTERN_INTERNAL,
55};
56
57static const char *patterns[] = {
58 STR_PATTERN_NONE,
59 STR_PATTERN_EXTERNAL,
60 STR_PATTERN_INTERNAL,
61};
62
63/* Channels are numbered 0-31 (on the PCB silkscreen). */
64SR_PRIV const char *p_ols_channel_names[NUM_CHANNELS + 1] = {
65 "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12",
66 "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23",
67 "24", "25", "26", "27", "28", "29", "30", "31",
68 NULL,
69};
70
71/* Default supported samplerates, can be overridden by device metadata. */
72static const uint64_t samplerates[] = {
73 SR_HZ(10),
74 SR_MHZ(200),
75 SR_HZ(1),
76};
77
78SR_PRIV struct sr_dev_driver p_ols_driver_info;
79static struct sr_dev_driver *di = &p_ols_driver_info;
80
81static int init(struct sr_context *sr_ctx)
82{
83 return std_init(sr_ctx, di, LOG_PREFIX);
84}
85
86static GSList *scan(GSList *options)
87{
88 struct sr_dev_inst *sdi;
89 struct drv_context *drvc;
90 struct dev_context *devc;
91 GSList *devices;
92 int ret, i;
93 char buf[70];
94 int bytes_read;
95
96 (void)options;
97
98 drvc = di->priv;
99
100 devices = NULL;
101
102 /* Allocate memory for our private device context. */
103 if (!(devc = g_try_malloc0(sizeof(struct dev_context)))) {
104 sr_err("Device context malloc failed.");
105 goto err_free_nothing;
106 }
107
108 /* Device-specific settings */
b94cff40 109 devc->max_samplebytes = devc->max_samplerate = devc->protocol_version = 0;
4bd80e12 110
111 /* Acquisition settings */
112 devc->limit_samples = devc->capture_ratio = 0;
113 devc->trigger_at = -1;
114 devc->channel_mask = 0xffffffff;
115 devc->flag_reg = 0;
116
117 /* Allocate memory for the incoming ftdi data. */
118 if (!(devc->ftdi_buf = g_try_malloc0(FTDI_BUF_SIZE))) {
119 sr_err("ftdi_buf malloc failed.");
120 goto err_free_devc;
121 }
122
123 /* Allocate memory for the FTDI context (ftdic) and initialize it. */
124 if (!(devc->ftdic = ftdi_new())) {
125 sr_err("Failed to initialize libftdi.");
126 goto err_free_ftdi_buf;;
127 }
128
129 /* Try to open the FTDI device */
130 if (p_ols_open(devc) != SR_OK) {
131 goto err_free_ftdic;
132 }
133
134 /* The discovery procedure is like this: first send the Reset
135 * command (0x00) 5 times, since the device could be anywhere
136 * in a 5-byte command. Then send the ID command (0x02).
137 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
138 * have a match.
139 */
140
141 ret = SR_OK;
142 for (i = 0; i < 5; i++) {
143 if ((ret = write_shortcommand(devc, CMD_RESET)) != SR_OK) {
144 break;
145 }
146 }
147 if (ret != SR_OK) {
148 sr_err("Could not reset device. Quitting.");
149 goto err_close_ftdic;
150 }
151 write_shortcommand(devc, CMD_ID);
152
153 /* Read the response data. */
154 bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 4);
155 if (bytes_read < 0) {
156 sr_err("Failed to read FTDI data (%d): %s.",
157 bytes_read, ftdi_get_error_string(devc->ftdic));
158 goto err_close_ftdic;
159 }
160 if (bytes_read == 0) {
161 goto err_close_ftdic;
162 }
163
164 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
165 goto err_close_ftdic;
166
167 /* Definitely using the OLS protocol, check if it supports
168 * the metadata command.
169 */
170 write_shortcommand(devc, CMD_METADATA);
171
172 /* Read the metadata. */
173 bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 64);
174 if (bytes_read < 0) {
175 sr_err("Failed to read FTDI data (%d): %s.",
176 bytes_read, ftdi_get_error_string(devc->ftdic));
177 goto err_close_ftdic;
178 }
179 if (bytes_read == 0) {
180 goto err_close_ftdic;
181 }
182
183 /* Close device. We'll reopen it again when we need it. */
184 p_ols_close(devc);
185
186 /* Parse the metadata. */
187 sdi = p_ols_get_metadata((uint8_t *)buf, bytes_read, devc);
4bd80e12 188
189 /* Configure samplerate and divider. */
190 if (p_ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK)
191 sr_dbg("Failed to set default samplerate (%"PRIu64").",
192 DEFAULT_SAMPLERATE);
4bd80e12 193
194 drvc->instances = g_slist_append(drvc->instances, sdi);
195 devices = g_slist_append(devices, sdi);
196
197 return devices;
198
199err_close_ftdic:
200 p_ols_close(devc);
201err_free_ftdic:
202 ftdi_free(devc->ftdic); /* NOT free() or g_free()! */
203err_free_ftdi_buf:
204 g_free(devc->ftdi_buf);
205err_free_devc:
206 g_free(devc);
207err_free_nothing:
208
209 return NULL;
210}
211
212static GSList *dev_list(void)
213{
214 return ((struct drv_context *)(di->priv))->instances;
215}
216
217static void clear_helper(void *priv)
218{
219 struct dev_context *devc;
220
221 devc = priv;
222
223 ftdi_free(devc->ftdic);
224 g_free(devc->ftdi_buf);
225}
226
227static int dev_clear(void)
228{
229 return std_dev_clear(di, clear_helper);
230}
231
232static int cleanup(void)
233{
234 return dev_clear();
235}
236
237
584560f1 238static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
4bd80e12 239 const struct sr_channel_group *cg)
240{
241 struct dev_context *devc;
242
243 (void)cg;
244
245 if (!sdi)
246 return SR_ERR_ARG;
247
248 devc = sdi->priv;
584560f1 249 switch (key) {
4bd80e12 250 case SR_CONF_SAMPLERATE:
251 *data = g_variant_new_uint64(devc->cur_samplerate);
252 break;
253 case SR_CONF_CAPTURE_RATIO:
254 *data = g_variant_new_uint64(devc->capture_ratio);
255 break;
256 case SR_CONF_LIMIT_SAMPLES:
257 *data = g_variant_new_uint64(devc->limit_samples);
258 break;
259 case SR_CONF_PATTERN_MODE:
260 if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE)
261 *data = g_variant_new_string(STR_PATTERN_EXTERNAL);
262 else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE)
263 *data = g_variant_new_string(STR_PATTERN_INTERNAL);
264 else
265 *data = g_variant_new_string(STR_PATTERN_NONE);
266 break;
267 case SR_CONF_RLE:
268 *data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE);
269 break;
270 case SR_CONF_EXTERNAL_CLOCK:
271 *data = g_variant_new_boolean(devc->flag_reg & FLAG_CLOCK_EXTERNAL ? TRUE : FALSE);
272 break;
273 default:
274 return SR_ERR_NA;
275 }
276
277 return SR_OK;
278}
279
584560f1 280static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
4bd80e12 281 const struct sr_channel_group *cg)
282{
283 struct dev_context *devc;
284 uint16_t flag;
285 uint64_t tmp_u64;
286 int ret;
287 const char *stropt;
288
289 (void)cg;
290
291 if (sdi->status != SR_ST_ACTIVE)
292 return SR_ERR_DEV_CLOSED;
293
294 devc = sdi->priv;
295
584560f1 296 switch (key) {
4bd80e12 297 case SR_CONF_SAMPLERATE:
298 tmp_u64 = g_variant_get_uint64(data);
299 if (tmp_u64 < samplerates[0] || tmp_u64 > samplerates[1])
300 return SR_ERR_SAMPLERATE;
301 ret = p_ols_set_samplerate(sdi, g_variant_get_uint64(data));
302 break;
303 case SR_CONF_LIMIT_SAMPLES:
304 tmp_u64 = g_variant_get_uint64(data);
305 if (tmp_u64 < MIN_NUM_SAMPLES)
306 return SR_ERR;
307 devc->limit_samples = tmp_u64;
308 ret = SR_OK;
309 break;
310 case SR_CONF_CAPTURE_RATIO:
311 devc->capture_ratio = g_variant_get_uint64(data);
312 if (devc->capture_ratio < 0 || devc->capture_ratio > 100) {
313 devc->capture_ratio = 0;
314 ret = SR_ERR;
315 } else
316 ret = SR_OK;
317 break;
318 case SR_CONF_EXTERNAL_CLOCK:
319 if (g_variant_get_boolean(data)) {
320 sr_info("Enabling external clock.");
321 devc->flag_reg |= FLAG_CLOCK_EXTERNAL;
322 } else {
323 sr_info("Disabled external clock.");
324 devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL;
325 }
326 ret = SR_OK;
327 break;
328 case SR_CONF_PATTERN_MODE:
329 stropt = g_variant_get_string(data, NULL);
330 ret = SR_OK;
331 flag = 0xffff;
332 if (!strcmp(stropt, STR_PATTERN_NONE)) {
333 sr_info("Disabling test modes.");
334 flag = 0x0000;
335 }else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) {
336 sr_info("Enabling internal test mode.");
337 flag = FLAG_INTERNAL_TEST_MODE;
338 } else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) {
339 sr_info("Enabling external test mode.");
340 flag = FLAG_EXTERNAL_TEST_MODE;
341 } else {
342 ret = SR_ERR;
343 }
344 if (flag != 0xffff) {
345 devc->flag_reg &= ~(FLAG_INTERNAL_TEST_MODE | FLAG_EXTERNAL_TEST_MODE);
346 devc->flag_reg |= flag;
347 }
348 break;
349 case SR_CONF_SWAP:
350 if (g_variant_get_boolean(data)) {
351 sr_info("Enabling channel swapping.");
352 devc->flag_reg |= FLAG_SWAP_CHANNELS;
353 } else {
354 sr_info("Disabling channel swapping.");
355 devc->flag_reg &= ~FLAG_SWAP_CHANNELS;
356 }
357 ret = SR_OK;
358 break;
359
360 case SR_CONF_RLE:
361 if (g_variant_get_boolean(data)) {
362 sr_info("Enabling RLE.");
363 devc->flag_reg |= FLAG_RLE;
364 } else {
365 sr_info("Disabling RLE.");
366 devc->flag_reg &= ~FLAG_RLE;
367 }
368 ret = SR_OK;
369 break;
370 default:
371 ret = SR_ERR_NA;
372 }
373
374 return ret;
375}
376
584560f1 377static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
4bd80e12 378 const struct sr_channel_group *cg)
379{
380 struct dev_context *devc;
381 GVariant *gvar, *grange[2];
382 GVariantBuilder gvb;
acc885c7 383 int num_pols_changrp, i;
4bd80e12 384
385 (void)cg;
386
387 switch (key) {
388 case SR_CONF_DEVICE_OPTIONS:
584560f1 389 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
f254bc4b 390 devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
4bd80e12 391 break;
392 case SR_CONF_SAMPLERATE:
393 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
394 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
395 ARRAY_SIZE(samplerates), sizeof(uint64_t));
396 g_variant_builder_add(&gvb, "{sv}", "samplerate-steps", gvar);
397 *data = g_variant_builder_end(&gvb);
398 break;
acc885c7
BV
399 case SR_CONF_TRIGGER_MATCH:
400 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
401 trigger_matches, ARRAY_SIZE(trigger_matches),
402 sizeof(int32_t));
4bd80e12 403 break;
404 case SR_CONF_PATTERN_MODE:
405 *data = g_variant_new_strv(patterns, ARRAY_SIZE(patterns));
406 break;
407 case SR_CONF_LIMIT_SAMPLES:
408 if (!sdi)
409 return SR_ERR_ARG;
410 devc = sdi->priv;
411 if (devc->flag_reg & FLAG_RLE)
412 return SR_ERR_NA;
b94cff40 413 if (devc->max_samplebytes == 0)
4bd80e12 414 /* Device didn't specify sample memory size in metadata. */
415 return SR_ERR_NA;
416 /*
417 * Channel groups are turned off if no channels in that group are
418 * enabled, making more room for samples for the enabled group.
419 */
acc885c7
BV
420 pols_channel_mask(sdi);
421 num_pols_changrp = 0;
4bd80e12 422 for (i = 0; i < 4; i++) {
423 if (devc->channel_mask & (0xff << (i * 8)))
acc885c7 424 num_pols_changrp++;
4bd80e12 425 }
b94cff40 426 /* 3 channel groups takes as many bytes as 4 channel groups */
acc885c7
BV
427 if (num_pols_changrp == 3)
428 num_pols_changrp = 4;
4bd80e12 429 grange[0] = g_variant_new_uint64(MIN_NUM_SAMPLES);
acc885c7
BV
430 if (num_pols_changrp)
431 grange[1] = g_variant_new_uint64(devc->max_samplebytes / num_pols_changrp);
432 else
433 grange[1] = g_variant_new_uint64(MIN_NUM_SAMPLES);
4bd80e12 434 *data = g_variant_new_tuple(grange, 2);
435 break;
436 default:
437 return SR_ERR_NA;
438 }
439
440 return SR_OK;
441}
442
443static int dev_open(struct sr_dev_inst *sdi)
444{
445 struct dev_context *devc;
4bd80e12 446
447 devc = sdi->priv;
448
449 if (p_ols_open(devc) != SR_OK) {
450 return SR_ERR;
451 } else {
452 sdi->status = SR_ST_ACTIVE;
453 return SR_OK;
454 }
455}
456
457static int dev_close(struct sr_dev_inst *sdi)
458{
459 int ret;
460 struct dev_context *devc;
461
462 ret = SR_OK;
463 devc = sdi->priv;
464
465 if (sdi->status == SR_ST_ACTIVE) {
466 sr_dbg("Status ACTIVE, closing device.");
467 ret = p_ols_close(devc);
468 } else {
469 sr_spew("Status not ACTIVE, nothing to do.");
470 }
471
472 sdi->status = SR_ST_INACTIVE;
473
474 return ret;
475}
476
477
478static int set_trigger(const struct sr_dev_inst *sdi, int stage)
479{
480 struct dev_context *devc;
481 uint8_t cmd, arg[4];
482
483 devc = sdi->priv;
484
485 cmd = CMD_SET_TRIGGER_MASK + stage * 4;
486 arg[0] = devc->trigger_mask[stage] & 0xff;
487 arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff;
488 arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff;
489 arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff;
490 if (write_longcommand(devc, cmd, arg) != SR_OK)
491 return SR_ERR;
492
493 cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
494 arg[0] = devc->trigger_value[stage] & 0xff;
495 arg[1] = (devc->trigger_value[stage] >> 8) & 0xff;
496 arg[2] = (devc->trigger_value[stage] >> 16) & 0xff;
497 arg[3] = (devc->trigger_value[stage] >> 24) & 0xff;
498 if (write_longcommand(devc, cmd, arg) != SR_OK)
499 return SR_ERR;
500
501 cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
502 arg[0] = arg[1] = arg[3] = 0x00;
503 arg[2] = stage;
504 if (stage == devc->num_stages)
505 /* Last stage, fire when this one matches. */
506 arg[3] |= TRIGGER_START;
507 if (write_longcommand(devc, cmd, arg) != SR_OK)
508 return SR_ERR;
509
1e0de846 510 cmd = CMD_SET_TRIGGER_EDGE + stage * 4;
511 arg[0] = devc->trigger_edge[stage] & 0xff;
512 arg[1] = (devc->trigger_edge[stage] >> 8) & 0xff;
513 arg[2] = (devc->trigger_edge[stage] >> 16) & 0xff;
514 arg[3] = (devc->trigger_edge[stage] >> 24) & 0xff;
515 if (write_longcommand(devc, cmd, arg) != SR_OK)
516 return SR_ERR;
517
4bd80e12 518 return SR_OK;
519}
520
84cbaf77
BV
521static int disable_trigger(const struct sr_dev_inst *sdi, int stage)
522{
523 struct dev_context *devc;
524 uint8_t cmd, arg[4];
525
526 devc = sdi->priv;
527
528 cmd = CMD_SET_TRIGGER_MASK + stage * 4;
529 arg[0] = arg[1] = arg[2] = arg[3] = 0x00;
530 if (write_longcommand(devc, cmd, arg) != SR_OK)
531 return SR_ERR;
532
533 cmd = CMD_SET_TRIGGER_VALUE + stage * 4;
534 if (write_longcommand(devc, cmd, arg) != SR_OK)
535 return SR_ERR;
536
537 cmd = CMD_SET_TRIGGER_CONFIG + stage * 4;
538 arg[2] = 0x03;
539 if (write_longcommand(devc, cmd, arg) != SR_OK)
540 return SR_ERR;
541
542 cmd = CMD_SET_TRIGGER_EDGE + stage * 4;
543 arg[2] = 0x00;
544 if (write_longcommand(devc, cmd, arg) != SR_OK)
545 return SR_ERR;
546
547 return SR_OK;
548}
549
4bd80e12 550static int dev_acquisition_start(const struct sr_dev_inst *sdi,
551 void *cb_data)
552{
553 struct dev_context *devc;
554 uint32_t samplecount, readcount, delaycount;
acc885c7 555 uint8_t pols_changrp_mask, arg[4];
b94cff40 556 uint16_t flag_tmp;
acc885c7 557 int num_pols_changrp, samplespercount;
4bd80e12 558 int ret, i;
559
560 if (sdi->status != SR_ST_ACTIVE)
561 return SR_ERR_DEV_CLOSED;
562
563 devc = sdi->priv;
564
acc885c7 565 pols_channel_mask(sdi);
4bd80e12 566
567 /*
568 * Enable/disable channel groups in the flag register according to the
acc885c7
BV
569 * channel mask. Calculate this here, because num_pols_changrp is
570 * needed to limit readcount.
4bd80e12 571 */
acc885c7
BV
572 pols_changrp_mask = 0;
573 num_pols_changrp = 0;
4bd80e12 574 for (i = 0; i < 4; i++) {
575 if (devc->channel_mask & (0xff << (i * 8))) {
acc885c7
BV
576 pols_changrp_mask |= (1 << i);
577 num_pols_changrp++;
4bd80e12 578 }
579 }
b94cff40 580 /* 3 channel groups takes as many bytes as 4 channel groups */
acc885c7
BV
581 if (num_pols_changrp == 3)
582 num_pols_changrp = 4;
b94cff40 583 /* maximum number of samples (or RLE counts) the buffer memory can hold */
acc885c7 584 devc->max_samples = devc->max_samplebytes / num_pols_changrp;
4bd80e12 585
586 /*
587 * Limit readcount to prevent reading past the end of the hardware
588 * buffer.
589 */
590 sr_dbg("max_samples = %d", devc->max_samples);
591 sr_dbg("limit_samples = %d", devc->limit_samples);
b94cff40 592 samplecount = MIN(devc->max_samples, devc->limit_samples);
4bd80e12 593 sr_dbg("Samplecount = %d", samplecount);
594
b94cff40 595 /* In demux mode the OLS is processing two samples per clock */
596 if (devc->flag_reg & FLAG_DEMUX) {
597 samplespercount = 8;
598 }
599 else {
600 samplespercount = 4;
601 }
602
603 readcount = samplecount / samplespercount;
604
4bd80e12 605 /* Rather read too many samples than too few. */
b94cff40 606 if (samplecount % samplespercount != 0)
4bd80e12 607 readcount++;
608
609 /* Basic triggers. */
acc885c7
BV
610 if (pols_convert_trigger(sdi) != SR_OK) {
611 sr_err("Failed to configure channels.");
612 return SR_ERR;
613 }
84cbaf77 614
acc885c7 615 if (devc->num_stages > 0) {
4bd80e12 616 delaycount = readcount * (1 - devc->capture_ratio / 100.0);
b94cff40 617 devc->trigger_at = (readcount - delaycount) * samplespercount - devc->num_stages;
84cbaf77
BV
618 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
619 if (i <= devc->num_stages) {
620 sr_dbg("Setting p-ols stage %d trigger.", i);
621 if ((ret = set_trigger(sdi, i)) != SR_OK)
622 return ret;
623 }
624 else {
625 sr_dbg("Disabling p-ols stage %d trigger.", i);
626 if ((ret = disable_trigger(sdi, i)) != SR_OK)
627 return ret;
628 }
4bd80e12 629 }
630 } else {
631 /* No triggers configured, force trigger on first stage. */
632 sr_dbg("Forcing trigger at stage 0.");
633 if ((ret = set_trigger(sdi, 0)) != SR_OK)
634 return ret;
635 delaycount = readcount;
636 }
637
638 /* Samplerate. */
639 sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)",
640 devc->cur_samplerate, devc->cur_samplerate_divider);
641 arg[0] = devc->cur_samplerate_divider & 0xff;
642 arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8;
643 arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16;
644 arg[3] = 0x00;
645 if (write_longcommand(devc, CMD_SET_DIVIDER, arg) != SR_OK)
646 return SR_ERR;
acc885c7 647
4bd80e12 648 /* Send extended sample limit and pre/post-trigger capture ratio. */
649 arg[0] = ((readcount - 1) & 0xff);
650 arg[1] = ((readcount - 1) & 0xff00) >> 8;
651 arg[2] = ((readcount - 1) & 0xff0000) >> 16;
652 arg[3] = ((readcount - 1) & 0xff000000) >> 24;
1e0de846 653 if (write_longcommand(devc, CMD_CAPTURE_DELAY, arg) != SR_OK)
4bd80e12 654 return SR_ERR;
655 arg[0] = ((delaycount - 1) & 0xff);
656 arg[1] = ((delaycount - 1) & 0xff00) >> 8;
657 arg[2] = ((delaycount - 1) & 0xff0000) >> 16;
658 arg[3] = ((delaycount - 1) & 0xff000000) >> 24;
1e0de846 659 if (write_longcommand(devc, CMD_CAPTURE_COUNT, arg) != SR_OK)
4bd80e12 660 return SR_ERR;
acc885c7 661
4bd80e12 662 /* Flag register. */
663 sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s",
664 devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off",
665 devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off",
666 devc->flag_reg & FLAG_RLE ? "on" : "off",
667 devc->flag_reg & FLAG_FILTER ? "on": "off",
668 devc->flag_reg & FLAG_DEMUX ? "on" : "off");
669
b94cff40 670 /*
671 * Enable/disable OLS channel groups in the flag register according
672 * to the channel mask. 1 means "disable channel".
673 */
674 devc->flag_reg &= ~0x3c;
acc885c7 675 devc->flag_reg |= ~(pols_changrp_mask << 2) & 0x3c;
b94cff40 676 sr_dbg("flag_reg = %x", devc->flag_reg);
677
678 /*
679 * In demux mode the OLS is processing two 8-bit or 16-bit samples
680 * in parallel and for this to work the lower two bits of the four
681 * "channel_disable" bits must be replicated to the upper two bits.
682 */
683 flag_tmp = devc->flag_reg;
684 if (devc->flag_reg & FLAG_DEMUX) {
685 flag_tmp &= ~0x30;
acc885c7 686 flag_tmp |= ~(pols_changrp_mask << 4) & 0x30;
b94cff40 687 }
688 arg[0] = flag_tmp & 0xff;
689 arg[1] = flag_tmp >> 8;
4bd80e12 690 arg[2] = arg[3] = 0x00;
691 if (write_longcommand(devc, CMD_SET_FLAGS, arg) != SR_OK)
692 return SR_ERR;
693
694 /* Start acquisition on the device. */
695 if (write_shortcommand(devc, CMD_RUN) != SR_OK)
696 return SR_ERR;
697
698 /* Reset all operational states. */
699 devc->rle_count = devc->num_transfers = 0;
700 devc->num_samples = devc->num_bytes = 0;
701 devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0;
702 memset(devc->sample, 0, 4);
703
704 /* Send header packet to the session bus. */
705 std_session_send_df_header(cb_data, LOG_PREFIX);
706
707 /* Hook up a dummy handler to receive data from the device. */
acc885c7
BV
708 sr_session_source_add(sdi->session, 0, G_IO_IN, 10, p_ols_receive_data,
709 cb_data);
4bd80e12 710
711 return SR_OK;
712}
713
714
715
716static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
717{
718 struct dev_context *devc;
719 struct sr_datafeed_packet packet;
720
721 devc = sdi->priv;
722
723 sr_dbg("Stopping acquisition.");
724 write_shortcommand(devc, CMD_RESET);
725 write_shortcommand(devc, CMD_RESET);
726 write_shortcommand(devc, CMD_RESET);
727 write_shortcommand(devc, CMD_RESET);
728 write_shortcommand(devc, CMD_RESET);
729
acc885c7 730 sr_session_source_remove(sdi->session, 0);
4bd80e12 731
732 /* Send end packet to the session bus. */
733 sr_dbg("Sending SR_DF_END.");
734 packet.type = SR_DF_END;
735 sr_session_send(cb_data, &packet);
736
737 return SR_OK;
738}
739
740SR_PRIV struct sr_dev_driver p_ols_driver_info = {
acc885c7 741 .name = "p-ols",
4bd80e12 742 .longname = "Pipistrello OLS",
743 .api_version = 1,
744 .init = init,
745 .cleanup = cleanup,
746 .scan = scan,
747 .dev_list = dev_list,
748 .dev_clear = dev_clear,
749 .config_get = config_get,
750 .config_set = config_set,
751 .config_list = config_list,
752 .dev_open = dev_open,
753 .dev_close = dev_close,
754 .dev_acquisition_start = dev_acquisition_start,
755 .dev_acquisition_stop = dev_acquisition_stop,
756 .priv = NULL,
757};