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4bd80e12 | 1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
5 | * | |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 3 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
6ec6c43b | 20 | #include <config.h> |
4bd80e12 | 21 | #include "protocol.h" |
22 | ||
05199c0a | 23 | static const uint32_t drvopts[] = { |
4bd80e12 | 24 | SR_CONF_LOGIC_ANALYZER, |
05199c0a UH |
25 | }; |
26 | ||
27 | static const uint32_t devopts[] = { | |
5827f61b BV |
28 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
29 | SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
30 | SR_CONF_TRIGGER_MATCH | SR_CONF_LIST, | |
31 | SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET, | |
32 | SR_CONF_PATTERN_MODE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
33 | SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET, | |
34 | SR_CONF_SWAP | SR_CONF_SET, | |
35 | SR_CONF_RLE | SR_CONF_GET | SR_CONF_SET, | |
4bd80e12 | 36 | }; |
37 | ||
acc885c7 BV |
38 | static const int32_t trigger_matches[] = { |
39 | SR_TRIGGER_ZERO, | |
40 | SR_TRIGGER_ONE, | |
41 | SR_TRIGGER_RISING, | |
42 | SR_TRIGGER_FALLING, | |
43 | }; | |
44 | ||
4bd80e12 | 45 | #define STR_PATTERN_NONE "None" |
46 | #define STR_PATTERN_EXTERNAL "External" | |
47 | #define STR_PATTERN_INTERNAL "Internal" | |
48 | ||
49 | /* Supported methods of test pattern outputs */ | |
50 | enum { | |
51 | /** | |
52 | * Capture pins 31:16 (unbuffered wing) output a test pattern | |
53 | * that can captured on pins 0:15. | |
54 | */ | |
55 | PATTERN_EXTERNAL, | |
56 | ||
57 | /** Route test pattern internally to capture buffer. */ | |
58 | PATTERN_INTERNAL, | |
59 | }; | |
60 | ||
61 | static const char *patterns[] = { | |
62 | STR_PATTERN_NONE, | |
63 | STR_PATTERN_EXTERNAL, | |
64 | STR_PATTERN_INTERNAL, | |
65 | }; | |
66 | ||
67 | /* Channels are numbered 0-31 (on the PCB silkscreen). */ | |
53cda65a | 68 | SR_PRIV const char *p_ols_channel_names[] = { |
4bd80e12 | 69 | "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", |
70 | "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23", | |
71 | "24", "25", "26", "27", "28", "29", "30", "31", | |
4bd80e12 | 72 | }; |
73 | ||
74 | /* Default supported samplerates, can be overridden by device metadata. */ | |
75 | static const uint64_t samplerates[] = { | |
76 | SR_HZ(10), | |
77 | SR_MHZ(200), | |
78 | SR_HZ(1), | |
79 | }; | |
80 | ||
4f840ce9 | 81 | static GSList *scan(struct sr_dev_driver *di, GSList *options) |
4bd80e12 | 82 | { |
83 | struct sr_dev_inst *sdi; | |
4bd80e12 | 84 | struct dev_context *devc; |
85 | GSList *devices; | |
86 | int ret, i; | |
87 | char buf[70]; | |
88 | int bytes_read; | |
89 | ||
90 | (void)options; | |
91 | ||
4bd80e12 | 92 | devices = NULL; |
93 | ||
94 | /* Allocate memory for our private device context. */ | |
f57d8ffe | 95 | devc = g_malloc0(sizeof(struct dev_context)); |
4bd80e12 | 96 | |
97 | /* Device-specific settings */ | |
b94cff40 | 98 | devc->max_samplebytes = devc->max_samplerate = devc->protocol_version = 0; |
4bd80e12 | 99 | |
100 | /* Acquisition settings */ | |
101 | devc->limit_samples = devc->capture_ratio = 0; | |
102 | devc->trigger_at = -1; | |
103 | devc->channel_mask = 0xffffffff; | |
104 | devc->flag_reg = 0; | |
105 | ||
106 | /* Allocate memory for the incoming ftdi data. */ | |
a95f142e | 107 | devc->ftdi_buf = g_malloc0(FTDI_BUF_SIZE); |
4bd80e12 | 108 | |
109 | /* Allocate memory for the FTDI context (ftdic) and initialize it. */ | |
110 | if (!(devc->ftdic = ftdi_new())) { | |
111 | sr_err("Failed to initialize libftdi."); | |
112 | goto err_free_ftdi_buf;; | |
113 | } | |
114 | ||
115 | /* Try to open the FTDI device */ | |
116 | if (p_ols_open(devc) != SR_OK) { | |
117 | goto err_free_ftdic; | |
118 | } | |
176d785d | 119 | |
4bd80e12 | 120 | /* The discovery procedure is like this: first send the Reset |
121 | * command (0x00) 5 times, since the device could be anywhere | |
122 | * in a 5-byte command. Then send the ID command (0x02). | |
123 | * If the device responds with 4 bytes ("OLS1" or "SLA1"), we | |
124 | * have a match. | |
125 | */ | |
126 | ||
127 | ret = SR_OK; | |
128 | for (i = 0; i < 5; i++) { | |
129 | if ((ret = write_shortcommand(devc, CMD_RESET)) != SR_OK) { | |
130 | break; | |
131 | } | |
132 | } | |
133 | if (ret != SR_OK) { | |
134 | sr_err("Could not reset device. Quitting."); | |
135 | goto err_close_ftdic; | |
136 | } | |
137 | write_shortcommand(devc, CMD_ID); | |
138 | ||
139 | /* Read the response data. */ | |
140 | bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 4); | |
141 | if (bytes_read < 0) { | |
142 | sr_err("Failed to read FTDI data (%d): %s.", | |
143 | bytes_read, ftdi_get_error_string(devc->ftdic)); | |
144 | goto err_close_ftdic; | |
145 | } | |
146 | if (bytes_read == 0) { | |
147 | goto err_close_ftdic; | |
148 | } | |
149 | ||
150 | if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4)) | |
151 | goto err_close_ftdic; | |
152 | ||
153 | /* Definitely using the OLS protocol, check if it supports | |
154 | * the metadata command. | |
155 | */ | |
156 | write_shortcommand(devc, CMD_METADATA); | |
157 | ||
158 | /* Read the metadata. */ | |
159 | bytes_read = ftdi_read_data(devc->ftdic, (uint8_t *)buf, 64); | |
160 | if (bytes_read < 0) { | |
161 | sr_err("Failed to read FTDI data (%d): %s.", | |
162 | bytes_read, ftdi_get_error_string(devc->ftdic)); | |
163 | goto err_close_ftdic; | |
164 | } | |
165 | if (bytes_read == 0) { | |
166 | goto err_close_ftdic; | |
167 | } | |
168 | ||
169 | /* Close device. We'll reopen it again when we need it. */ | |
170 | p_ols_close(devc); | |
171 | ||
172 | /* Parse the metadata. */ | |
173 | sdi = p_ols_get_metadata((uint8_t *)buf, bytes_read, devc); | |
4bd80e12 | 174 | |
175 | /* Configure samplerate and divider. */ | |
176 | if (p_ols_set_samplerate(sdi, DEFAULT_SAMPLERATE) != SR_OK) | |
177 | sr_dbg("Failed to set default samplerate (%"PRIu64").", | |
178 | DEFAULT_SAMPLERATE); | |
4bd80e12 | 179 | |
4bd80e12 | 180 | devices = g_slist_append(devices, sdi); |
181 | ||
15a5bfe4 | 182 | return std_scan_complete(di, devices); |
4bd80e12 | 183 | |
184 | err_close_ftdic: | |
185 | p_ols_close(devc); | |
186 | err_free_ftdic: | |
187 | ftdi_free(devc->ftdic); /* NOT free() or g_free()! */ | |
188 | err_free_ftdi_buf: | |
189 | g_free(devc->ftdi_buf); | |
4bd80e12 | 190 | g_free(devc); |
4bd80e12 | 191 | |
192 | return NULL; | |
193 | } | |
194 | ||
3553451f | 195 | static void clear_helper(struct dev_context *devc) |
4bd80e12 | 196 | { |
4bd80e12 | 197 | ftdi_free(devc->ftdic); |
198 | g_free(devc->ftdi_buf); | |
199 | } | |
200 | ||
4f840ce9 | 201 | static int dev_clear(const struct sr_dev_driver *di) |
4bd80e12 | 202 | { |
3553451f | 203 | return std_dev_clear_with_callback(di, (std_dev_clear_callback)clear_helper); |
4bd80e12 | 204 | } |
205 | ||
584560f1 | 206 | static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi, |
4bd80e12 | 207 | const struct sr_channel_group *cg) |
208 | { | |
209 | struct dev_context *devc; | |
210 | ||
211 | (void)cg; | |
212 | ||
213 | if (!sdi) | |
214 | return SR_ERR_ARG; | |
215 | ||
216 | devc = sdi->priv; | |
584560f1 | 217 | switch (key) { |
4bd80e12 | 218 | case SR_CONF_SAMPLERATE: |
219 | *data = g_variant_new_uint64(devc->cur_samplerate); | |
220 | break; | |
221 | case SR_CONF_CAPTURE_RATIO: | |
222 | *data = g_variant_new_uint64(devc->capture_ratio); | |
223 | break; | |
224 | case SR_CONF_LIMIT_SAMPLES: | |
225 | *data = g_variant_new_uint64(devc->limit_samples); | |
226 | break; | |
227 | case SR_CONF_PATTERN_MODE: | |
228 | if (devc->flag_reg & FLAG_EXTERNAL_TEST_MODE) | |
229 | *data = g_variant_new_string(STR_PATTERN_EXTERNAL); | |
230 | else if (devc->flag_reg & FLAG_INTERNAL_TEST_MODE) | |
231 | *data = g_variant_new_string(STR_PATTERN_INTERNAL); | |
232 | else | |
233 | *data = g_variant_new_string(STR_PATTERN_NONE); | |
234 | break; | |
235 | case SR_CONF_RLE: | |
236 | *data = g_variant_new_boolean(devc->flag_reg & FLAG_RLE ? TRUE : FALSE); | |
237 | break; | |
238 | case SR_CONF_EXTERNAL_CLOCK: | |
239 | *data = g_variant_new_boolean(devc->flag_reg & FLAG_CLOCK_EXTERNAL ? TRUE : FALSE); | |
240 | break; | |
241 | default: | |
242 | return SR_ERR_NA; | |
243 | } | |
244 | ||
245 | return SR_OK; | |
246 | } | |
247 | ||
584560f1 | 248 | static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi, |
4bd80e12 | 249 | const struct sr_channel_group *cg) |
250 | { | |
251 | struct dev_context *devc; | |
252 | uint16_t flag; | |
253 | uint64_t tmp_u64; | |
254 | int ret; | |
255 | const char *stropt; | |
256 | ||
257 | (void)cg; | |
258 | ||
4bd80e12 | 259 | devc = sdi->priv; |
260 | ||
584560f1 | 261 | switch (key) { |
4bd80e12 | 262 | case SR_CONF_SAMPLERATE: |
263 | tmp_u64 = g_variant_get_uint64(data); | |
264 | if (tmp_u64 < samplerates[0] || tmp_u64 > samplerates[1]) | |
265 | return SR_ERR_SAMPLERATE; | |
266 | ret = p_ols_set_samplerate(sdi, g_variant_get_uint64(data)); | |
267 | break; | |
268 | case SR_CONF_LIMIT_SAMPLES: | |
269 | tmp_u64 = g_variant_get_uint64(data); | |
270 | if (tmp_u64 < MIN_NUM_SAMPLES) | |
271 | return SR_ERR; | |
272 | devc->limit_samples = tmp_u64; | |
273 | ret = SR_OK; | |
274 | break; | |
275 | case SR_CONF_CAPTURE_RATIO: | |
276 | devc->capture_ratio = g_variant_get_uint64(data); | |
a5c38703 | 277 | if (devc->capture_ratio < 0 || devc->capture_ratio > 100) |
4bd80e12 | 278 | ret = SR_ERR; |
a5c38703 | 279 | else |
4bd80e12 | 280 | ret = SR_OK; |
281 | break; | |
282 | case SR_CONF_EXTERNAL_CLOCK: | |
283 | if (g_variant_get_boolean(data)) { | |
284 | sr_info("Enabling external clock."); | |
285 | devc->flag_reg |= FLAG_CLOCK_EXTERNAL; | |
286 | } else { | |
287 | sr_info("Disabled external clock."); | |
288 | devc->flag_reg &= ~FLAG_CLOCK_EXTERNAL; | |
289 | } | |
290 | ret = SR_OK; | |
291 | break; | |
292 | case SR_CONF_PATTERN_MODE: | |
293 | stropt = g_variant_get_string(data, NULL); | |
294 | ret = SR_OK; | |
295 | flag = 0xffff; | |
296 | if (!strcmp(stropt, STR_PATTERN_NONE)) { | |
297 | sr_info("Disabling test modes."); | |
298 | flag = 0x0000; | |
299 | }else if (!strcmp(stropt, STR_PATTERN_INTERNAL)) { | |
300 | sr_info("Enabling internal test mode."); | |
301 | flag = FLAG_INTERNAL_TEST_MODE; | |
302 | } else if (!strcmp(stropt, STR_PATTERN_EXTERNAL)) { | |
303 | sr_info("Enabling external test mode."); | |
304 | flag = FLAG_EXTERNAL_TEST_MODE; | |
305 | } else { | |
306 | ret = SR_ERR; | |
307 | } | |
308 | if (flag != 0xffff) { | |
309 | devc->flag_reg &= ~(FLAG_INTERNAL_TEST_MODE | FLAG_EXTERNAL_TEST_MODE); | |
310 | devc->flag_reg |= flag; | |
311 | } | |
312 | break; | |
313 | case SR_CONF_SWAP: | |
314 | if (g_variant_get_boolean(data)) { | |
315 | sr_info("Enabling channel swapping."); | |
316 | devc->flag_reg |= FLAG_SWAP_CHANNELS; | |
317 | } else { | |
318 | sr_info("Disabling channel swapping."); | |
319 | devc->flag_reg &= ~FLAG_SWAP_CHANNELS; | |
320 | } | |
321 | ret = SR_OK; | |
322 | break; | |
323 | ||
324 | case SR_CONF_RLE: | |
325 | if (g_variant_get_boolean(data)) { | |
326 | sr_info("Enabling RLE."); | |
327 | devc->flag_reg |= FLAG_RLE; | |
328 | } else { | |
329 | sr_info("Disabling RLE."); | |
330 | devc->flag_reg &= ~FLAG_RLE; | |
331 | } | |
332 | ret = SR_OK; | |
333 | break; | |
334 | default: | |
335 | ret = SR_ERR_NA; | |
336 | } | |
337 | ||
338 | return ret; | |
339 | } | |
340 | ||
584560f1 | 341 | static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi, |
4bd80e12 | 342 | const struct sr_channel_group *cg) |
343 | { | |
344 | struct dev_context *devc; | |
345 | GVariant *gvar, *grange[2]; | |
346 | GVariantBuilder gvb; | |
acc885c7 | 347 | int num_pols_changrp, i; |
4bd80e12 | 348 | |
4bd80e12 | 349 | switch (key) { |
350 | case SR_CONF_DEVICE_OPTIONS: | |
05199c0a | 351 | return STD_CONFIG_LIST(key, data, sdi, cg, NULL, drvopts, devopts); |
4bd80e12 | 352 | case SR_CONF_SAMPLERATE: |
353 | g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}")); | |
354 | gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates, | |
355 | ARRAY_SIZE(samplerates), sizeof(uint64_t)); | |
356 | g_variant_builder_add(&gvb, "{sv}", "samplerate-steps", gvar); | |
357 | *data = g_variant_builder_end(&gvb); | |
358 | break; | |
acc885c7 BV |
359 | case SR_CONF_TRIGGER_MATCH: |
360 | *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32, | |
361 | trigger_matches, ARRAY_SIZE(trigger_matches), | |
362 | sizeof(int32_t)); | |
4bd80e12 | 363 | break; |
364 | case SR_CONF_PATTERN_MODE: | |
365 | *data = g_variant_new_strv(patterns, ARRAY_SIZE(patterns)); | |
366 | break; | |
367 | case SR_CONF_LIMIT_SAMPLES: | |
368 | if (!sdi) | |
369 | return SR_ERR_ARG; | |
370 | devc = sdi->priv; | |
371 | if (devc->flag_reg & FLAG_RLE) | |
372 | return SR_ERR_NA; | |
b94cff40 | 373 | if (devc->max_samplebytes == 0) |
4bd80e12 | 374 | /* Device didn't specify sample memory size in metadata. */ |
375 | return SR_ERR_NA; | |
376 | /* | |
377 | * Channel groups are turned off if no channels in that group are | |
378 | * enabled, making more room for samples for the enabled group. | |
379 | */ | |
acc885c7 BV |
380 | pols_channel_mask(sdi); |
381 | num_pols_changrp = 0; | |
4bd80e12 | 382 | for (i = 0; i < 4; i++) { |
383 | if (devc->channel_mask & (0xff << (i * 8))) | |
acc885c7 | 384 | num_pols_changrp++; |
4bd80e12 | 385 | } |
b94cff40 | 386 | /* 3 channel groups takes as many bytes as 4 channel groups */ |
acc885c7 BV |
387 | if (num_pols_changrp == 3) |
388 | num_pols_changrp = 4; | |
4bd80e12 | 389 | grange[0] = g_variant_new_uint64(MIN_NUM_SAMPLES); |
acc885c7 BV |
390 | if (num_pols_changrp) |
391 | grange[1] = g_variant_new_uint64(devc->max_samplebytes / num_pols_changrp); | |
392 | else | |
393 | grange[1] = g_variant_new_uint64(MIN_NUM_SAMPLES); | |
4bd80e12 | 394 | *data = g_variant_new_tuple(grange, 2); |
395 | break; | |
396 | default: | |
397 | return SR_ERR_NA; | |
398 | } | |
399 | ||
400 | return SR_OK; | |
401 | } | |
402 | ||
403 | static int dev_open(struct sr_dev_inst *sdi) | |
404 | { | |
405 | struct dev_context *devc; | |
4bd80e12 | 406 | |
407 | devc = sdi->priv; | |
408 | ||
7e463623 | 409 | return p_ols_open(devc); |
4bd80e12 | 410 | } |
411 | ||
412 | static int dev_close(struct sr_dev_inst *sdi) | |
413 | { | |
4bd80e12 | 414 | struct dev_context *devc; |
415 | ||
4bd80e12 | 416 | devc = sdi->priv; |
417 | ||
093e1cba | 418 | return p_ols_close(devc); |
4bd80e12 | 419 | } |
420 | ||
4bd80e12 | 421 | static int set_trigger(const struct sr_dev_inst *sdi, int stage) |
422 | { | |
423 | struct dev_context *devc; | |
424 | uint8_t cmd, arg[4]; | |
425 | ||
426 | devc = sdi->priv; | |
427 | ||
428 | cmd = CMD_SET_TRIGGER_MASK + stage * 4; | |
429 | arg[0] = devc->trigger_mask[stage] & 0xff; | |
430 | arg[1] = (devc->trigger_mask[stage] >> 8) & 0xff; | |
431 | arg[2] = (devc->trigger_mask[stage] >> 16) & 0xff; | |
432 | arg[3] = (devc->trigger_mask[stage] >> 24) & 0xff; | |
433 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
434 | return SR_ERR; | |
435 | ||
436 | cmd = CMD_SET_TRIGGER_VALUE + stage * 4; | |
437 | arg[0] = devc->trigger_value[stage] & 0xff; | |
438 | arg[1] = (devc->trigger_value[stage] >> 8) & 0xff; | |
439 | arg[2] = (devc->trigger_value[stage] >> 16) & 0xff; | |
440 | arg[3] = (devc->trigger_value[stage] >> 24) & 0xff; | |
441 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
442 | return SR_ERR; | |
443 | ||
444 | cmd = CMD_SET_TRIGGER_CONFIG + stage * 4; | |
445 | arg[0] = arg[1] = arg[3] = 0x00; | |
446 | arg[2] = stage; | |
447 | if (stage == devc->num_stages) | |
448 | /* Last stage, fire when this one matches. */ | |
449 | arg[3] |= TRIGGER_START; | |
450 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
451 | return SR_ERR; | |
452 | ||
1e0de846 | 453 | cmd = CMD_SET_TRIGGER_EDGE + stage * 4; |
454 | arg[0] = devc->trigger_edge[stage] & 0xff; | |
455 | arg[1] = (devc->trigger_edge[stage] >> 8) & 0xff; | |
456 | arg[2] = (devc->trigger_edge[stage] >> 16) & 0xff; | |
457 | arg[3] = (devc->trigger_edge[stage] >> 24) & 0xff; | |
458 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
459 | return SR_ERR; | |
460 | ||
4bd80e12 | 461 | return SR_OK; |
462 | } | |
463 | ||
84cbaf77 BV |
464 | static int disable_trigger(const struct sr_dev_inst *sdi, int stage) |
465 | { | |
466 | struct dev_context *devc; | |
467 | uint8_t cmd, arg[4]; | |
468 | ||
469 | devc = sdi->priv; | |
470 | ||
471 | cmd = CMD_SET_TRIGGER_MASK + stage * 4; | |
472 | arg[0] = arg[1] = arg[2] = arg[3] = 0x00; | |
473 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
474 | return SR_ERR; | |
475 | ||
476 | cmd = CMD_SET_TRIGGER_VALUE + stage * 4; | |
477 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
478 | return SR_ERR; | |
479 | ||
480 | cmd = CMD_SET_TRIGGER_CONFIG + stage * 4; | |
481 | arg[2] = 0x03; | |
482 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
483 | return SR_ERR; | |
484 | ||
485 | cmd = CMD_SET_TRIGGER_EDGE + stage * 4; | |
486 | arg[2] = 0x00; | |
487 | if (write_longcommand(devc, cmd, arg) != SR_OK) | |
488 | return SR_ERR; | |
489 | ||
490 | return SR_OK; | |
491 | } | |
492 | ||
695dc859 | 493 | static int dev_acquisition_start(const struct sr_dev_inst *sdi) |
4bd80e12 | 494 | { |
495 | struct dev_context *devc; | |
496 | uint32_t samplecount, readcount, delaycount; | |
acc885c7 | 497 | uint8_t pols_changrp_mask, arg[4]; |
b94cff40 | 498 | uint16_t flag_tmp; |
acc885c7 | 499 | int num_pols_changrp, samplespercount; |
4bd80e12 | 500 | int ret, i; |
501 | ||
4bd80e12 | 502 | devc = sdi->priv; |
503 | ||
acc885c7 | 504 | pols_channel_mask(sdi); |
4bd80e12 | 505 | |
506 | /* | |
507 | * Enable/disable channel groups in the flag register according to the | |
acc885c7 BV |
508 | * channel mask. Calculate this here, because num_pols_changrp is |
509 | * needed to limit readcount. | |
4bd80e12 | 510 | */ |
acc885c7 BV |
511 | pols_changrp_mask = 0; |
512 | num_pols_changrp = 0; | |
4bd80e12 | 513 | for (i = 0; i < 4; i++) { |
514 | if (devc->channel_mask & (0xff << (i * 8))) { | |
acc885c7 BV |
515 | pols_changrp_mask |= (1 << i); |
516 | num_pols_changrp++; | |
4bd80e12 | 517 | } |
518 | } | |
b94cff40 | 519 | /* 3 channel groups takes as many bytes as 4 channel groups */ |
acc885c7 BV |
520 | if (num_pols_changrp == 3) |
521 | num_pols_changrp = 4; | |
b94cff40 | 522 | /* maximum number of samples (or RLE counts) the buffer memory can hold */ |
acc885c7 | 523 | devc->max_samples = devc->max_samplebytes / num_pols_changrp; |
4bd80e12 | 524 | |
525 | /* | |
526 | * Limit readcount to prevent reading past the end of the hardware | |
527 | * buffer. | |
528 | */ | |
529 | sr_dbg("max_samples = %d", devc->max_samples); | |
6433156c | 530 | sr_dbg("limit_samples = %" PRIu64, devc->limit_samples); |
b94cff40 | 531 | samplecount = MIN(devc->max_samples, devc->limit_samples); |
4bd80e12 | 532 | sr_dbg("Samplecount = %d", samplecount); |
533 | ||
b94cff40 | 534 | /* In demux mode the OLS is processing two samples per clock */ |
535 | if (devc->flag_reg & FLAG_DEMUX) { | |
536 | samplespercount = 8; | |
537 | } | |
538 | else { | |
539 | samplespercount = 4; | |
540 | } | |
541 | ||
542 | readcount = samplecount / samplespercount; | |
543 | ||
4bd80e12 | 544 | /* Rather read too many samples than too few. */ |
b94cff40 | 545 | if (samplecount % samplespercount != 0) |
4bd80e12 | 546 | readcount++; |
547 | ||
548 | /* Basic triggers. */ | |
acc885c7 BV |
549 | if (pols_convert_trigger(sdi) != SR_OK) { |
550 | sr_err("Failed to configure channels."); | |
551 | return SR_ERR; | |
552 | } | |
84cbaf77 | 553 | |
acc885c7 | 554 | if (devc->num_stages > 0) { |
4bd80e12 | 555 | delaycount = readcount * (1 - devc->capture_ratio / 100.0); |
b94cff40 | 556 | devc->trigger_at = (readcount - delaycount) * samplespercount - devc->num_stages; |
84cbaf77 BV |
557 | for (i = 0; i < NUM_TRIGGER_STAGES; i++) { |
558 | if (i <= devc->num_stages) { | |
559 | sr_dbg("Setting p-ols stage %d trigger.", i); | |
560 | if ((ret = set_trigger(sdi, i)) != SR_OK) | |
561 | return ret; | |
562 | } | |
563 | else { | |
564 | sr_dbg("Disabling p-ols stage %d trigger.", i); | |
565 | if ((ret = disable_trigger(sdi, i)) != SR_OK) | |
566 | return ret; | |
567 | } | |
4bd80e12 | 568 | } |
569 | } else { | |
570 | /* No triggers configured, force trigger on first stage. */ | |
571 | sr_dbg("Forcing trigger at stage 0."); | |
572 | if ((ret = set_trigger(sdi, 0)) != SR_OK) | |
573 | return ret; | |
574 | delaycount = readcount; | |
575 | } | |
576 | ||
577 | /* Samplerate. */ | |
578 | sr_dbg("Setting samplerate to %" PRIu64 "Hz (divider %u)", | |
579 | devc->cur_samplerate, devc->cur_samplerate_divider); | |
580 | arg[0] = devc->cur_samplerate_divider & 0xff; | |
581 | arg[1] = (devc->cur_samplerate_divider & 0xff00) >> 8; | |
582 | arg[2] = (devc->cur_samplerate_divider & 0xff0000) >> 16; | |
583 | arg[3] = 0x00; | |
584 | if (write_longcommand(devc, CMD_SET_DIVIDER, arg) != SR_OK) | |
585 | return SR_ERR; | |
acc885c7 | 586 | |
4bd80e12 | 587 | /* Send extended sample limit and pre/post-trigger capture ratio. */ |
588 | arg[0] = ((readcount - 1) & 0xff); | |
589 | arg[1] = ((readcount - 1) & 0xff00) >> 8; | |
590 | arg[2] = ((readcount - 1) & 0xff0000) >> 16; | |
591 | arg[3] = ((readcount - 1) & 0xff000000) >> 24; | |
1e0de846 | 592 | if (write_longcommand(devc, CMD_CAPTURE_DELAY, arg) != SR_OK) |
4bd80e12 | 593 | return SR_ERR; |
594 | arg[0] = ((delaycount - 1) & 0xff); | |
595 | arg[1] = ((delaycount - 1) & 0xff00) >> 8; | |
596 | arg[2] = ((delaycount - 1) & 0xff0000) >> 16; | |
597 | arg[3] = ((delaycount - 1) & 0xff000000) >> 24; | |
1e0de846 | 598 | if (write_longcommand(devc, CMD_CAPTURE_COUNT, arg) != SR_OK) |
4bd80e12 | 599 | return SR_ERR; |
acc885c7 | 600 | |
4bd80e12 | 601 | /* Flag register. */ |
602 | sr_dbg("Setting intpat %s, extpat %s, RLE %s, noise_filter %s, demux %s", | |
603 | devc->flag_reg & FLAG_INTERNAL_TEST_MODE ? "on": "off", | |
604 | devc->flag_reg & FLAG_EXTERNAL_TEST_MODE ? "on": "off", | |
605 | devc->flag_reg & FLAG_RLE ? "on" : "off", | |
606 | devc->flag_reg & FLAG_FILTER ? "on": "off", | |
607 | devc->flag_reg & FLAG_DEMUX ? "on" : "off"); | |
608 | ||
b94cff40 | 609 | /* |
610 | * Enable/disable OLS channel groups in the flag register according | |
611 | * to the channel mask. 1 means "disable channel". | |
612 | */ | |
613 | devc->flag_reg &= ~0x3c; | |
acc885c7 | 614 | devc->flag_reg |= ~(pols_changrp_mask << 2) & 0x3c; |
b94cff40 | 615 | sr_dbg("flag_reg = %x", devc->flag_reg); |
616 | ||
617 | /* | |
176d785d UH |
618 | * In demux mode the OLS is processing two 8-bit or 16-bit samples |
619 | * in parallel and for this to work the lower two bits of the four | |
b94cff40 | 620 | * "channel_disable" bits must be replicated to the upper two bits. |
621 | */ | |
622 | flag_tmp = devc->flag_reg; | |
623 | if (devc->flag_reg & FLAG_DEMUX) { | |
624 | flag_tmp &= ~0x30; | |
acc885c7 | 625 | flag_tmp |= ~(pols_changrp_mask << 4) & 0x30; |
b94cff40 | 626 | } |
627 | arg[0] = flag_tmp & 0xff; | |
628 | arg[1] = flag_tmp >> 8; | |
4bd80e12 | 629 | arg[2] = arg[3] = 0x00; |
630 | if (write_longcommand(devc, CMD_SET_FLAGS, arg) != SR_OK) | |
631 | return SR_ERR; | |
632 | ||
633 | /* Start acquisition on the device. */ | |
634 | if (write_shortcommand(devc, CMD_RUN) != SR_OK) | |
635 | return SR_ERR; | |
636 | ||
637 | /* Reset all operational states. */ | |
638 | devc->rle_count = devc->num_transfers = 0; | |
639 | devc->num_samples = devc->num_bytes = 0; | |
640 | devc->cnt_bytes = devc->cnt_samples = devc->cnt_samples_rle = 0; | |
641 | memset(devc->sample, 0, 4); | |
642 | ||
bee2b016 | 643 | std_session_send_df_header(sdi); |
4bd80e12 | 644 | |
645 | /* Hook up a dummy handler to receive data from the device. */ | |
c650d3ec | 646 | sr_session_source_add(sdi->session, -1, 0, 10, p_ols_receive_data, |
695dc859 | 647 | (struct sr_dev_inst *)sdi); |
4bd80e12 | 648 | |
649 | return SR_OK; | |
650 | } | |
651 | ||
695dc859 | 652 | static int dev_acquisition_stop(struct sr_dev_inst *sdi) |
4bd80e12 | 653 | { |
654 | struct dev_context *devc; | |
4bd80e12 | 655 | |
656 | devc = sdi->priv; | |
657 | ||
4bd80e12 | 658 | write_shortcommand(devc, CMD_RESET); |
659 | write_shortcommand(devc, CMD_RESET); | |
660 | write_shortcommand(devc, CMD_RESET); | |
661 | write_shortcommand(devc, CMD_RESET); | |
662 | write_shortcommand(devc, CMD_RESET); | |
663 | ||
dd7a4a71 | 664 | sr_session_source_remove(sdi->session, -1); |
4bd80e12 | 665 | |
bee2b016 | 666 | std_session_send_df_end(sdi); |
4bd80e12 | 667 | |
668 | return SR_OK; | |
669 | } | |
670 | ||
671 | SR_PRIV struct sr_dev_driver p_ols_driver_info = { | |
acc885c7 | 672 | .name = "p-ols", |
4bd80e12 | 673 | .longname = "Pipistrello OLS", |
674 | .api_version = 1, | |
c2fdcc25 | 675 | .init = std_init, |
700d6b64 | 676 | .cleanup = std_cleanup, |
4bd80e12 | 677 | .scan = scan, |
c01bf34c | 678 | .dev_list = std_dev_list, |
4bd80e12 | 679 | .dev_clear = dev_clear, |
680 | .config_get = config_get, | |
681 | .config_set = config_set, | |
682 | .config_list = config_list, | |
683 | .dev_open = dev_open, | |
684 | .dev_close = dev_close, | |
685 | .dev_acquisition_start = dev_acquisition_start, | |
686 | .dev_acquisition_stop = dev_acquisition_stop, | |
41812aca | 687 | .context = NULL, |
4bd80e12 | 688 | }; |
dd5c48a6 | 689 | SR_REGISTER_DEV_DRIVER(p_ols_driver_info); |