[libsigrok.git] / src / hardware / ikalogic-scanaplus / protocol.c

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Uwe Hermann <uwe@hermann-uwe.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */

#include <config.h>
#include "protocol.h"

/*
 * Logic level thresholds.
 *
 * For each of the two channel groups (1-4 and 5-9), the logic level
 * threshold can be set independently.
 *
 * The threshold can be set to values that are usable for systems with
 * different voltage levels, e.g. for 1.8V or 3.3V systems.
 *
 * The actual threshold value is always the middle of the values below.
 * E.g. for a system voltage level of 1.8V, the threshold is at 0.9V. That
 * means that values <= 0.9V are considered to be a logic 0/low, and
 * values > 0.9V are considered to be a logic 1/high.
 *
 *  - 1.2V system: threshold = 0.6V
 *  - 1.5V system: threshold = 0.75V
 *  - 1.8V system: threshold = 0.9V
 *  - 2.8V system: threshold = 1.4V
 *  - 3.3V system: threshold = 1.65V
 */
#define THRESHOLD_1_2V_SYSTEM 0x2e
#define THRESHOLD_1_5V_SYSTEM 0x39
#define THRESHOLD_1_8V_SYSTEM 0x45
#define THRESHOLD_2_8V_SYSTEM 0x6c
#define THRESHOLD_3_3V_SYSTEM 0x7f

static int scanaplus_write(struct dev_context *devc, uint8_t *buf, int size)
{
	int i, bytes_written;
	GString *s;

	/* Note: Caller checks devc, devc->ftdic, buf, size. */

	s = g_string_sized_new(100);
	g_string_printf(s, "Writing %d bytes: ", size);
	for (i = 0; i < size; i++)
		g_string_append_printf(s, "0x%02x ", buf[i]);
	sr_spew("%s", s->str);
	g_string_free(s, TRUE);

	bytes_written = ftdi_write_data(devc->ftdic, buf, size);
	if (bytes_written < 0) {
		sr_err("Failed to write FTDI data (%d): %s.",
		       bytes_written, ftdi_get_error_string(devc->ftdic));
	} else if (bytes_written != size) {
		sr_err("FTDI write error, only %d/%d bytes written: %s.",
		       bytes_written, size, ftdi_get_error_string(devc->ftdic));
	}

	return bytes_written;
}

SR_PRIV int scanaplus_close(struct dev_context *devc)
{
	int ret;

	/* Note: Caller checks devc and devc->ftdic. */

	if ((ret = ftdi_usb_close(devc->ftdic)) < 0) {
		sr_err("Failed to close FTDI device (%d): %s.",
		       ret, ftdi_get_error_string(devc->ftdic));
		return SR_ERR;
	}

	return SR_OK;
}

static void scanaplus_uncompress_block(struct dev_context *devc,
				       uint64_t num_bytes)
{
	uint64_t i, j;
	uint8_t num_samples, low, high;

	for (i = 0; i < num_bytes; i += 2) {
		num_samples = devc->compressed_buf[i + 0] >> 1;

		low = devc->compressed_buf[i + 0] & (1 << 0);
		high = devc->compressed_buf[i + 1];

		for (j = 0; j < num_samples; j++) {
			devc->sample_buf[devc->bytes_received++] = high;
			devc->sample_buf[devc->bytes_received++] = low;
		}
	}
}

static void send_samples(const struct sr_dev_inst *sdi, uint64_t samples_to_send)
{
	struct sr_datafeed_packet packet;
	struct sr_datafeed_logic logic;
	struct dev_context *devc;

	devc = sdi->priv;

	sr_spew("Sending %" PRIu64 " samples.", samples_to_send);

	packet.type = SR_DF_LOGIC;
	packet.payload = &logic;
	logic.length = samples_to_send * 2;
	logic.unitsize = 2; /* We need 2 bytes for 9 channels. */
	logic.data = devc->sample_buf;
	sr_session_send(sdi, &packet);

	devc->samples_sent += samples_to_send;
	devc->bytes_received -= samples_to_send * 2;
}

SR_PRIV int scanaplus_get_device_id(struct dev_context *devc)
{
	int ret;
	uint16_t val1, val2;

	/* FTDI EEPROM indices 16+17 contain the 3 device ID bytes. */
	if ((ret = ftdi_read_eeprom_location(devc->ftdic, 16, &val1)) < 0) {
		sr_err("Failed to read EEPROM index 16 (%d): %s.",
		       ret, ftdi_get_error_string(devc->ftdic));
		return SR_ERR;
	}
	if ((ret = ftdi_read_eeprom_location(devc->ftdic, 17, &val2)) < 0) {
		sr_err("Failed to read EEPROM index 17 (%d): %s.",
		       ret, ftdi_get_error_string(devc->ftdic));
		return SR_ERR;
	}

	/*
	 * Note: Bit 7 of the three bytes must not be used, apparently.
	 *
	 * Even though the three bits can be either 0 or 1 (we've seen both
	 * in actual ScanaPLUS devices), the device ID as sent to the FPGA
	 * has bit 7 of each byte zero'd out.
	 *
	 * It is unknown whether bit 7 of these bytes has any meaning,
	 * whether it's used somewhere, or whether it can be simply ignored.
	 */
	devc->devid[0] = ((val1 >> 0) & 0xff) & ~(1 << 7);
	devc->devid[1] = ((val1 >> 8) & 0xff) & ~(1 << 7);
	devc->devid[2] = ((val2 >> 0) & 0xff) & ~(1 << 7);

	return SR_OK;
}

static int scanaplus_clear_device_id(struct dev_context *devc)
{
	uint8_t buf[2];

	buf[0] = 0x8c;
	buf[1] = 0x00;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x8e;
	buf[1] = 0x00;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x8f;
	buf[1] = 0x00;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	return SR_OK;
}

static int scanaplus_send_device_id(struct dev_context *devc)
{
	uint8_t buf[2];

	buf[0] = 0x8c;
	buf[1] = devc->devid[0];
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x8e;
	buf[1] = devc->devid[1];
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x8f;
	buf[1] = devc->devid[2];
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	return SR_OK;
}

SR_PRIV int scanaplus_init(struct dev_context *devc)
{
	int i;
	uint8_t buf[8];

	buf[0] = 0x88;
	buf[1] = 0x41;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x89;
	buf[1] = 0x64;
	buf[2] = 0x8a;
	buf[3] = 0x64;
	if (scanaplus_write(devc, (uint8_t *)&buf, 4) < 0)
		return SR_ERR;

	buf[0] = 0x88;
	buf[1] = 0x41;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x88;
	buf[1] = 0x40;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	buf[0] = 0x8d;
	buf[1] = 0x01;
	buf[2] = 0x8d;
	buf[3] = 0x05;
	buf[4] = 0x8d;
	buf[5] = 0x01;
	buf[6] = 0x8d;
	buf[7] = 0x02;
	if (scanaplus_write(devc, (uint8_t *)&buf, 8) < 0)
		return SR_ERR;

	for (i = 0; i < 57; i++) {
		buf[0] = 0x8d;
		buf[1] = 0x06;
		if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
			return SR_ERR;

		buf[0] = 0x8d;
		buf[1] = 0x02;
		if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
			return SR_ERR;
	}

	if (scanaplus_send_device_id(devc) < 0)
		return SR_ERR;

	buf[0] = 0x88;
	buf[1] = 0x40;
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	return SR_OK;
}

SR_PRIV int scanaplus_start_acquisition(struct dev_context *devc)
{
	uint8_t buf[4];

	/* Threshold and differential channel settings not yet implemented. */

	buf[0] = 0x89;
	buf[1] = 0x7f; /* Logic level threshold for channels 1-4. */
	buf[2] = 0x8a;
	buf[3] = 0x7f; /* Logic level threshold for channels 5-9. */
	if (scanaplus_write(devc, (uint8_t *)&buf, 4) < 0)
		return SR_ERR;

	buf[0] = 0x88;
	buf[1] = 0x40; /* Special config of channels 5/6 and 7/8. */
	/* 0x40: normal, 0x50: ch56 diff, 0x48: ch78 diff, 0x58: ch5678 diff */
	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
		return SR_ERR;

	if (scanaplus_clear_device_id(devc) < 0)
		return SR_ERR;

	if (scanaplus_send_device_id(devc) < 0)
		return SR_ERR;

	return SR_OK;
}

SR_PRIV int scanaplus_receive_data(int fd, int revents, void *cb_data)
{
	int bytes_read;
	struct sr_dev_inst *sdi;
	struct dev_context *devc;
	uint64_t max, n;

	(void)fd;
	(void)revents;

	if (!(sdi = cb_data))
		return TRUE;

	if (!(devc = sdi->priv))
		return TRUE;

	if (!devc->ftdic)
		return TRUE;

	/* Get a block of data. */
	bytes_read = ftdi_read_data(devc->ftdic, devc->compressed_buf,
				    COMPRESSED_BUF_SIZE);
	if (bytes_read < 0) {
		sr_err("Failed to read FTDI data (%d): %s.",
		       bytes_read, ftdi_get_error_string(devc->ftdic));
		sdi->driver->dev_acquisition_stop(sdi);
		return FALSE;
	}
	if (bytes_read == 0) {
		sr_spew("Received 0 bytes, nothing to do.");
		return TRUE;
	}

	/*
	 * After a ScanaPLUS acquisition starts, a bunch of samples will be
	 * returned as all-zero, no matter which signals are actually present
	 * on the channels. This is probably due to the FPGA reconfiguring some
	 * of its internal state/config during this time.
	 *
	 * As far as we know there is apparently no way for the PC-side to
	 * know when this "reconfiguration" starts or ends. The FTDI chip
	 * will return all-zero "dummy" samples during this time, which is
	 * indistinguishable from actual all-zero samples.
	 *
	 * We currently simply ignore the first 64kB of data after an
	 * acquisition starts. Empirical tests have shown that the
	 * "reconfigure" time is a lot less than that usually.
	 */
	if (devc->compressed_bytes_ignored < COMPRESSED_BUF_SIZE) {
		/* Ignore the first 64kB of data of every acquisition. */
		sr_spew("Ignoring first 64kB chunk of data.");
		devc->compressed_bytes_ignored += COMPRESSED_BUF_SIZE;
		return TRUE;
	}

	/* TODO: Handle bytes_read which is not a multiple of 2? */
	scanaplus_uncompress_block(devc, bytes_read);

	n = devc->samples_sent + (devc->bytes_received / 2);
	max = (SR_MHZ(100) / 1000) * devc->limit_msec;

	if (devc->limit_samples && (n >= devc->limit_samples)) {
		send_samples(sdi, devc->limit_samples - devc->samples_sent);
		sr_info("Requested number of samples reached.");
		sdi->driver->dev_acquisition_stop(sdi);
		return TRUE;
	} else if (devc->limit_msec && (n >= max)) {
		send_samples(sdi, max - devc->samples_sent);
		sr_info("Requested time limit reached.");
		sdi->driver->dev_acquisition_stop(sdi);
		return TRUE;
	} else {
		send_samples(sdi, devc->bytes_received / 2);
	}

	return TRUE;
}
Commit	Line	Data
fdf4a1f5 UH	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2013 Uwe Hermann <uwe@hermann-uwe.de>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
	20
6ec6c43b	21	#include <config.h>
fdf4a1f5 UH	22	#include "protocol.h"
fdf4a1f5 UH	23
ab4bb6eb UH	24	/*
	25	* Logic level thresholds.
	26	*
	27	* For each of the two channel groups (1-4 and 5-9), the logic level
	28	* threshold can be set independently.
	29	*
	30	* The threshold can be set to values that are usable for systems with
	31	* different voltage levels, e.g. for 1.8V or 3.3V systems.
	32	*
	33	* The actual threshold value is always the middle of the values below.
	34	* E.g. for a system voltage level of 1.8V, the threshold is at 0.9V. That
	35	* means that values <= 0.9V are considered to be a logic 0/low, and
	36	* values > 0.9V are considered to be a logic 1/high.
	37	*
	38	* - 1.2V system: threshold = 0.6V
	39	* - 1.5V system: threshold = 0.75V
	40	* - 1.8V system: threshold = 0.9V
	41	* - 2.8V system: threshold = 1.4V
	42	* - 3.3V system: threshold = 1.65V
	43	*/
	44	#define THRESHOLD_1_2V_SYSTEM 0x2e
	45	#define THRESHOLD_1_5V_SYSTEM 0x39
	46	#define THRESHOLD_1_8V_SYSTEM 0x45
	47	#define THRESHOLD_2_8V_SYSTEM 0x6c
	48	#define THRESHOLD_3_3V_SYSTEM 0x7f
	49
	50	static int scanaplus_write(struct dev_context devc, uint8_t buf, int size)
	51	{
	52	int i, bytes_written;
	53	GString *s;
	54
	55	/* Note: Caller checks devc, devc->ftdic, buf, size. */
	56
	57	s = g_string_sized_new(100);
	58	g_string_printf(s, "Writing %d bytes: ", size);
	59	for (i = 0; i < size; i++)
	60	g_string_append_printf(s, "0x%02x ", buf[i]);
	61	sr_spew("%s", s->str);
	62	g_string_free(s, TRUE);
	63
	64	bytes_written = ftdi_write_data(devc->ftdic, buf, size);
	65	if (bytes_written < 0) {
	66	sr_err("Failed to write FTDI data (%d): %s.",
	67	bytes_written, ftdi_get_error_string(devc->ftdic));
	68	} else if (bytes_written != size) {
	69	sr_err("FTDI write error, only %d/%d bytes written: %s.",
	70	bytes_written, size, ftdi_get_error_string(devc->ftdic));
	71	}
	72
	73	return bytes_written;
	74	}
	75
	76	SR_PRIV int scanaplus_close(struct dev_context *devc)
	77	{
	78	int ret;
	79
	80	/* Note: Caller checks devc and devc->ftdic. */
	81
	82	if ((ret = ftdi_usb_close(devc->ftdic)) < 0) {
	83	sr_err("Failed to close FTDI device (%d): %s.",
	84	ret, ftdi_get_error_string(devc->ftdic));
	85	return SR_ERR;
	86	}
	87
88	return SR_OK;
89	}
90
91	static void scanaplus_uncompress_block(struct dev_context *devc,
92	uint64_t num_bytes)
fdf4a1f5	93	{
ab4bb6eb UH	94	uint64_t i, j;
	95	uint8_t num_samples, low, high;
	96
	97	for (i = 0; i < num_bytes; i += 2) {
	98	num_samples = devc->compressed_buf[i + 0] >> 1;
	99
	100	low = devc->compressed_buf[i + 0] & (1 << 0);
	101	high = devc->compressed_buf[i + 1];
	102
	103	for (j = 0; j < num_samples; j++) {
	104	devc->sample_buf[devc->bytes_received++] = high;
	105	devc->sample_buf[devc->bytes_received++] = low;
	106	}
	107	}
	108	}
	109
695dc859	110	static void send_samples(const struct sr_dev_inst *sdi, uint64_t samples_to_send)
ab4bb6eb UH	111	{
	112	struct sr_datafeed_packet packet;
	113	struct sr_datafeed_logic logic;
695dc859 UH	114	struct dev_context *devc;
	115
	116	devc = sdi->priv;
ab4bb6eb UH	117
	118	sr_spew("Sending %" PRIu64 " samples.", samples_to_send);
	119
	120	packet.type = SR_DF_LOGIC;
	121	packet.payload = &logic;
	122	logic.length = samples_to_send * 2;
ba7dd8bb	123	logic.unitsize = 2; /* We need 2 bytes for 9 channels. */
ab4bb6eb	124	logic.data = devc->sample_buf;
695dc859	125	sr_session_send(sdi, &packet);
ab4bb6eb UH	126
	127	devc->samples_sent += samples_to_send;
	128	devc->bytes_received -= samples_to_send * 2;
	129	}
	130
	131	SR_PRIV int scanaplus_get_device_id(struct dev_context *devc)
	132	{
	133	int ret;
	134	uint16_t val1, val2;
	135
	136	/* FTDI EEPROM indices 16+17 contain the 3 device ID bytes. */
	137	if ((ret = ftdi_read_eeprom_location(devc->ftdic, 16, &val1)) < 0) {
	138	sr_err("Failed to read EEPROM index 16 (%d): %s.",
	139	ret, ftdi_get_error_string(devc->ftdic));
	140	return SR_ERR;
	141	}
	142	if ((ret = ftdi_read_eeprom_location(devc->ftdic, 17, &val2)) < 0) {
	143	sr_err("Failed to read EEPROM index 17 (%d): %s.",
	144	ret, ftdi_get_error_string(devc->ftdic));
	145	return SR_ERR;
	146	}
	147
	148	/*
	149	* Note: Bit 7 of the three bytes must not be used, apparently.
	150	*
	151	* Even though the three bits can be either 0 or 1 (we've seen both
	152	* in actual ScanaPLUS devices), the device ID as sent to the FPGA
	153	* has bit 7 of each byte zero'd out.
	154	*
	155	* It is unknown whether bit 7 of these bytes has any meaning,
	156	* whether it's used somewhere, or whether it can be simply ignored.
	157	*/
	158	devc->devid[0] = ((val1 >> 0) & 0xff) & ~(1 << 7);
	159	devc->devid[1] = ((val1 >> 8) & 0xff) & ~(1 << 7);
	160	devc->devid[2] = ((val2 >> 0) & 0xff) & ~(1 << 7);
	161
	162	return SR_OK;
	163	}
	164
	165	static int scanaplus_clear_device_id(struct dev_context *devc)
	166	{
	167	uint8_t buf[2];
	168
	169	buf[0] = 0x8c;
	170	buf[1] = 0x00;
	171	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
	172	return SR_ERR;
	173
	174	buf[0] = 0x8e;
	175	buf[1] = 0x00;
	176	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
	177	return SR_ERR;
	178
	179	buf[0] = 0x8f;
	180	buf[1] = 0x00;
	181	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
	182	return SR_ERR;
	183
	184	return SR_OK;
	185	}
	186
	187	static int scanaplus_send_device_id(struct dev_context *devc)
	188	{
	189	uint8_t buf[2];
190
191	buf[0] = 0x8c;
192	buf[1] = devc->devid[0];
193	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
194	return SR_ERR;
195
196	buf[0] = 0x8e;
197	buf[1] = devc->devid[1];
198	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
199	return SR_ERR;
200
201	buf[0] = 0x8f;
202	buf[1] = devc->devid[2];
203	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
204	return SR_ERR;
205
206	return SR_OK;
207	}
208
209	SR_PRIV int scanaplus_init(struct dev_context *devc)
210	{
211	int i;
212	uint8_t buf[8];
213
214	buf[0] = 0x88;
215	buf[1] = 0x41;
216	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
217	return SR_ERR;
218
219	buf[0] = 0x89;
220	buf[1] = 0x64;
221	buf[2] = 0x8a;
222	buf[3] = 0x64;
223	if (scanaplus_write(devc, (uint8_t *)&buf, 4) < 0)
224	return SR_ERR;
225
226	buf[0] = 0x88;
227	buf[1] = 0x41;
228	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
229	return SR_ERR;
230
231	buf[0] = 0x88;
232	buf[1] = 0x40;
233	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
234	return SR_ERR;
235
236	buf[0] = 0x8d;
237	buf[1] = 0x01;
238	buf[2] = 0x8d;
239	buf[3] = 0x05;
240	buf[4] = 0x8d;
241	buf[5] = 0x01;
242	buf[6] = 0x8d;
243	buf[7] = 0x02;
244	if (scanaplus_write(devc, (uint8_t *)&buf, 8) < 0)
245	return SR_ERR;
246
247	for (i = 0; i < 57; i++) {
248	buf[0] = 0x8d;
249	buf[1] = 0x06;
250	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
251	return SR_ERR;
252
253	buf[0] = 0x8d;
254	buf[1] = 0x02;
255	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
256	return SR_ERR;
257	}
258
259	if (scanaplus_send_device_id(devc) < 0)
260	return SR_ERR;
261
262	buf[0] = 0x88;
263	buf[1] = 0x40;
264	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
265	return SR_ERR;
266
267	return SR_OK;
268	}
269
270	SR_PRIV int scanaplus_start_acquisition(struct dev_context *devc)
271	{
272	uint8_t buf[4];
273
ba7dd8bb	274	/* Threshold and differential channel settings not yet implemented. */
ab4bb6eb UH	275
ab4bb6eb UH	276	buf[0] = 0x89;
ba7dd8bb	277	buf[1] = 0x7f; /* Logic level threshold for channels 1-4. */
ab4bb6eb	278	buf[2] = 0x8a;
ba7dd8bb	279	buf[3] = 0x7f; /* Logic level threshold for channels 5-9. */
ab4bb6eb UH	280	if (scanaplus_write(devc, (uint8_t *)&buf, 4) < 0)
	281	return SR_ERR;
	282
	283	buf[0] = 0x88;
ba7dd8bb	284	buf[1] = 0x40; /* Special config of channels 5/6 and 7/8. */
ab4bb6eb UH	285	/* 0x40: normal, 0x50: ch56 diff, 0x48: ch78 diff, 0x58: ch5678 diff */
	286	if (scanaplus_write(devc, (uint8_t *)&buf, 2) < 0)
	287	return SR_ERR;
	288
	289	if (scanaplus_clear_device_id(devc) < 0)
	290	return SR_ERR;
	291
	292	if (scanaplus_send_device_id(devc) < 0)
	293	return SR_ERR;
	294
	295	return SR_OK;
	296	}
	297
	298	SR_PRIV int scanaplus_receive_data(int fd, int revents, void *cb_data)
	299	{
	300	int bytes_read;
	301	struct sr_dev_inst *sdi;
fdf4a1f5	302	struct dev_context *devc;
ab4bb6eb	303	uint64_t max, n;
fdf4a1f5 UH	304
fdf4a1f5 UH	305	(void)fd;
ab4bb6eb	306	(void)revents;
fdf4a1f5 UH	307
	308	if (!(sdi = cb_data))
	309	return TRUE;
	310
	311	if (!(devc = sdi->priv))
	312	return TRUE;
	313
ab4bb6eb UH	314	if (!devc->ftdic)
	315	return TRUE;
	316
	317	/* Get a block of data. */
	318	bytes_read = ftdi_read_data(devc->ftdic, devc->compressed_buf,
	319	COMPRESSED_BUF_SIZE);
	320	if (bytes_read < 0) {
	321	sr_err("Failed to read FTDI data (%d): %s.",
	322	bytes_read, ftdi_get_error_string(devc->ftdic));
695dc859	323	sdi->driver->dev_acquisition_stop(sdi);
ab4bb6eb UH	324	return FALSE;
	325	}
	326	if (bytes_read == 0) {
	327	sr_spew("Received 0 bytes, nothing to do.");
	328	return TRUE;
	329	}
	330
	331	/*
	332	* After a ScanaPLUS acquisition starts, a bunch of samples will be
	333	* returned as all-zero, no matter which signals are actually present
ba7dd8bb	334	* on the channels. This is probably due to the FPGA reconfiguring some
ab4bb6eb UH	335	* of its internal state/config during this time.
	336	*
	337	* As far as we know there is apparently no way for the PC-side to
	338	* know when this "reconfiguration" starts or ends. The FTDI chip
	339	* will return all-zero "dummy" samples during this time, which is
	340	* indistinguishable from actual all-zero samples.
	341	*
	342	* We currently simply ignore the first 64kB of data after an
	343	* acquisition starts. Empirical tests have shown that the
	344	* "reconfigure" time is a lot less than that usually.
	345	*/
	346	if (devc->compressed_bytes_ignored < COMPRESSED_BUF_SIZE) {
	347	/* Ignore the first 64kB of data of every acquisition. */
	348	sr_spew("Ignoring first 64kB chunk of data.");
	349	devc->compressed_bytes_ignored += COMPRESSED_BUF_SIZE;
	350	return TRUE;
	351	}
	352
	353	/* TODO: Handle bytes_read which is not a multiple of 2? */
	354	scanaplus_uncompress_block(devc, bytes_read);
	355
	356	n = devc->samples_sent + (devc->bytes_received / 2);
	357	max = (SR_MHZ(100) / 1000) * devc->limit_msec;
	358
	359	if (devc->limit_samples && (n >= devc->limit_samples)) {
695dc859	360	send_samples(sdi, devc->limit_samples - devc->samples_sent);
ab4bb6eb	361	sr_info("Requested number of samples reached.");
695dc859	362	sdi->driver->dev_acquisition_stop(sdi);
ab4bb6eb UH	363	return TRUE;
ab4bb6eb UH	364	} else if (devc->limit_msec && (n >= max)) {
695dc859	365	send_samples(sdi, max - devc->samples_sent);
ab4bb6eb	366	sr_info("Requested time limit reached.");
695dc859	367	sdi->driver->dev_acquisition_stop(sdi);
ab4bb6eb UH	368	return TRUE;
ab4bb6eb UH	369	} else {
695dc859	370	send_samples(sdi, devc->bytes_received / 2);
fdf4a1f5 UH	371	}
	372
	373	return TRUE;
	374	}