[libsigrok.git] / src / hardware / fx2lafw / dslogic.h

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H
#define LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H

/* Modified protocol commands & flags used by DSLogic */
#define DS_CMD_GET_FW_VERSION		0xb0
#define DS_CMD_GET_REVID_VERSION	0xb1
#define DS_CMD_START			0xb2
#define DS_CMD_FPGA_FW			0xb3
#define DS_CMD_CONFIG			0xb4

#define DS_NUM_TRIGGER_STAGES		16
#define DS_START_FLAGS_STOP		(1 << 7)
#define DS_START_FLAGS_CLK_48MHZ	(1 << 6)
#define DS_START_FLAGS_SAMPLE_WIDE	(1 << 5)

enum dslogic_operation_modes {
	DS_OP_NORMAL,
	DS_OP_INTERNAL_TEST,
	DS_OP_EXTERNAL_TEST,
	DS_OP_LOOPBACK_TEST,
};

struct dslogic_version {
	uint8_t major;
	uint8_t minor;
};

struct dslogic_mode {
	uint8_t flags;
	uint8_t sample_delay_h;
	uint8_t sample_delay_l;
};

struct dslogic_trigger_pos {
	uint32_t real_pos;
	uint32_t ram_saddr;
	uint8_t first_block[504];
};

/*
 * The FPGA is configured with TLV tuples. Length is specified as the
 * number of 16-bit words, and the (type, length) header is in some
 * cases padded with 0xffff.
 */
#define _DS_CFG(variable, wordcnt) ((variable << 8) | wordcnt)
#define _DS_CFG_PAD(variable, wordcnt) ((_DS_CFG(variable, wordcnt) << 16) | 0xffff)
#define DS_CFG_START		0xffffffff
#define DS_CFG_MODE		_DS_CFG(0, 1)
#define DS_CFG_DIVIDER		_DS_CFG_PAD(1, 2)
#define DS_CFG_COUNT		_DS_CFG_PAD(3, 2)
#define DS_CFG_TRIG_POS		_DS_CFG_PAD(5, 2)
#define DS_CFG_TRIG_GLB		_DS_CFG(7, 1)
#define DS_CFG_TRIG_ADP		_DS_CFG_PAD(10, 2)
#define DS_CFG_TRIG_SDA		_DS_CFG_PAD(12, 2)
#define DS_CFG_TRIG_MASK0	_DS_CFG_PAD(16, 16)
#define DS_CFG_TRIG_MASK1	_DS_CFG_PAD(17, 16)
#define DS_CFG_TRIG_VALUE0	_DS_CFG_PAD(20, 16)
#define DS_CFG_TRIG_VALUE1	_DS_CFG_PAD(21, 16)
#define DS_CFG_TRIG_EDGE0	_DS_CFG_PAD(24, 16)
#define DS_CFG_TRIG_EDGE1	_DS_CFG_PAD(25, 16)
#define DS_CFG_TRIG_COUNT0	_DS_CFG_PAD(28, 16)
#define DS_CFG_TRIG_COUNT1	_DS_CFG_PAD(29, 16)
#define DS_CFG_TRIG_LOGIC0	_DS_CFG_PAD(32, 16)
#define DS_CFG_TRIG_LOGIC1	_DS_CFG_PAD(33, 16)
#define DS_CFG_END		0x00000000

struct dslogic_fpga_config {
	uint32_t sync;
	uint16_t mode_header;
	uint16_t mode;
	uint32_t divider_header;
	uint32_t divider;
	uint32_t count_header;
	uint32_t count;
	uint32_t trig_pos_header;
	uint32_t trig_pos;
	uint16_t trig_glb_header;
	uint16_t trig_glb;
	uint32_t trig_adp_header;
	uint32_t trig_adp;
	uint32_t trig_sda_header;
	uint32_t trig_sda;
	uint32_t trig_mask0_header;
	uint16_t trig_mask0[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_mask1_header;
	uint16_t trig_mask1[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_value0_header;
	uint16_t trig_value0[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_value1_header;
	uint16_t trig_value1[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_edge0_header;
	uint16_t trig_edge0[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_edge1_header;
	uint16_t trig_edge1[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_count0_header;
	uint16_t trig_count0[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_count1_header;
	uint16_t trig_count1[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_logic0_header;
	uint16_t trig_logic0[DS_NUM_TRIGGER_STAGES];
	uint32_t trig_logic1_header;
	uint16_t trig_logic1[DS_NUM_TRIGGER_STAGES];
	uint32_t end_sync;
};

SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
		const char *name);
SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);

#endif
Commit	Line	Data
b9d53092 BV	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
	5	* Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
	6	*
	7	* This program is free software: you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation, either version 3 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
6fcf3f0a	21	#ifndef LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H
	22	#define LIBSIGROK_HARDWARE_FX2LAFW_DSLOGIC_H
	23
b9d53092 BV	24	/* Modified protocol commands & flags used by DSLogic */
	25	#define DS_CMD_GET_FW_VERSION 0xb0
	26	#define DS_CMD_GET_REVID_VERSION 0xb1
6fcf3f0a	27	#define DS_CMD_START 0xb2
	28	#define DS_CMD_FPGA_FW 0xb3
	29	#define DS_CMD_CONFIG 0xb4
b9d53092	30
6fcf3f0a	31	#define DS_NUM_TRIGGER_STAGES 16
	32	#define DS_START_FLAGS_STOP (1 << 7)
	33	#define DS_START_FLAGS_CLK_48MHZ (1 << 6)
	34	#define DS_START_FLAGS_SAMPLE_WIDE (1 << 5)
b9d53092 BV	35
	36	enum dslogic_operation_modes {
	37	DS_OP_NORMAL,
	38	DS_OP_INTERNAL_TEST,
	39	DS_OP_EXTERNAL_TEST,
	40	DS_OP_LOOPBACK_TEST,
	41	};
	42
	43	struct dslogic_version {
	44	uint8_t major;
	45	uint8_t minor;
	46	};
	47
	48	struct dslogic_mode {
	49	uint8_t flags;
	50	uint8_t sample_delay_h;
	51	uint8_t sample_delay_l;
	52	};
	53
	54	struct dslogic_trigger_pos {
	55	uint32_t real_pos;
	56	uint32_t ram_saddr;
	57	uint8_t first_block[504];
	58	};
	59
	60	/*
	61	* The FPGA is configured with TLV tuples. Length is specified as the
	62	* number of 16-bit words, and the (type, length) header is in some
	63	* cases padded with 0xffff.
	64	*/
	65	#define _DS_CFG(variable, wordcnt) ((variable << 8) \| wordcnt)
	66	#define _DS_CFG_PAD(variable, wordcnt) ((_DS_CFG(variable, wordcnt) << 16) \| 0xffff)
	67	#define DS_CFG_START 0xffffffff
6fcf3f0a	68	#define DS_CFG_MODE _DS_CFG(0, 1)
b9d53092 BV	69	#define DS_CFG_DIVIDER _DS_CFG_PAD(1, 2)
	70	#define DS_CFG_COUNT _DS_CFG_PAD(3, 2)
	71	#define DS_CFG_TRIG_POS _DS_CFG_PAD(5, 2)
	72	#define DS_CFG_TRIG_GLB _DS_CFG(7, 1)
	73	#define DS_CFG_TRIG_ADP _DS_CFG_PAD(10, 2)
	74	#define DS_CFG_TRIG_SDA _DS_CFG_PAD(12, 2)
	75	#define DS_CFG_TRIG_MASK0 _DS_CFG_PAD(16, 16)
	76	#define DS_CFG_TRIG_MASK1 _DS_CFG_PAD(17, 16)
	77	#define DS_CFG_TRIG_VALUE0 _DS_CFG_PAD(20, 16)
	78	#define DS_CFG_TRIG_VALUE1 _DS_CFG_PAD(21, 16)
	79	#define DS_CFG_TRIG_EDGE0 _DS_CFG_PAD(24, 16)
	80	#define DS_CFG_TRIG_EDGE1 _DS_CFG_PAD(25, 16)
	81	#define DS_CFG_TRIG_COUNT0 _DS_CFG_PAD(28, 16)
	82	#define DS_CFG_TRIG_COUNT1 _DS_CFG_PAD(29, 16)
	83	#define DS_CFG_TRIG_LOGIC0 _DS_CFG_PAD(32, 16)
	84	#define DS_CFG_TRIG_LOGIC1 _DS_CFG_PAD(33, 16)
6fcf3f0a	85	#define DS_CFG_END 0x00000000
b9d53092 BV	86
	87	struct dslogic_fpga_config {
	88	uint32_t sync;
	89	uint16_t mode_header;
	90	uint16_t mode;
	91	uint32_t divider_header;
	92	uint32_t divider;
	93	uint32_t count_header;
	94	uint32_t count;
	95	uint32_t trig_pos_header;
	96	uint32_t trig_pos;
	97	uint16_t trig_glb_header;
	98	uint16_t trig_glb;
	99	uint32_t trig_adp_header;
	100	uint32_t trig_adp;
	101	uint32_t trig_sda_header;
	102	uint32_t trig_sda;
	103	uint32_t trig_mask0_header;
	104	uint16_t trig_mask0[DS_NUM_TRIGGER_STAGES];
	105	uint32_t trig_mask1_header;
	106	uint16_t trig_mask1[DS_NUM_TRIGGER_STAGES];
	107	uint32_t trig_value0_header;
	108	uint16_t trig_value0[DS_NUM_TRIGGER_STAGES];
	109	uint32_t trig_value1_header;
	110	uint16_t trig_value1[DS_NUM_TRIGGER_STAGES];
	111	uint32_t trig_edge0_header;
	112	uint16_t trig_edge0[DS_NUM_TRIGGER_STAGES];
	113	uint32_t trig_edge1_header;
	114	uint16_t trig_edge1[DS_NUM_TRIGGER_STAGES];
	115	uint32_t trig_count0_header;
	116	uint16_t trig_count0[DS_NUM_TRIGGER_STAGES];
	117	uint32_t trig_count1_header;
	118	uint16_t trig_count1[DS_NUM_TRIGGER_STAGES];
	119	uint32_t trig_logic0_header;
	120	uint16_t trig_logic0[DS_NUM_TRIGGER_STAGES];
	121	uint32_t trig_logic1_header;
	122	uint16_t trig_logic1[DS_NUM_TRIGGER_STAGES];
	123	uint32_t end_sync;
	124	};
	125
8e2d6c9d DE	126	SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
	127	const char *name);
	128	SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
	129	SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
	130	SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);
6fcf3f0a	131
6fcf3f0a	132	#endif