]> sigrok.org Git - libsigrok.git/blame - hardware/sysclk-lwla/protocol.h
sysclk-lwla: Implement support for the LWLA1034.
[libsigrok.git] / hardware / sysclk-lwla / protocol.h
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1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
21#define LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
22
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23/* Message logging helpers with subsystem-specific prefix string. */
24#define LOG_PREFIX "sysclk-lwla"
25
26#include "lwla.h"
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27#include "libsigrok.h"
28#include "libsigrok-internal.h"
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29#include <stdint.h>
30#include <glib.h>
aeaad0b0 31
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32/* For now, only the LWLA1034 is supported.
33 */
34#define VENDOR_NAME "SysClk"
35#define MODEL_NAME "LWLA1034"
36
37#define USB_VID_PID "2961.6689"
38#define USB_INTERFACE 0
39#define USB_TIMEOUT 3000 /* ms */
40
41#define NUM_PROBES 34
42#define TRIGGER_TYPES "01fr"
43
44/** Unit and packet size for the sigrok logic datafeed.
45 */
46#define UNIT_SIZE ((NUM_PROBES + 7) / 8)
47#define PACKET_SIZE (10000 * UNIT_SIZE) /* bytes */
48
49/** Size of the acquisition buffer in device memory units.
50 */
51#define MEMORY_DEPTH (256 * 1024) /* 256k x 36 bit */
52
53/** Number of device memory units (36 bit) to read at a time. Slices of 8
54 * consecutive 36-bit words are mapped to 9 32-bit words each, so the chunk
55 * length should be a multiple of 8 to ensure alignment to slice boundaries.
56 *
57 * Experimentation has shown that reading chunks larger than about 1024 bytes
58 * is unreliable. The threshold seems to relate to the buffer size on the FX2
59 * USB chip: The configured endpoint buffer size is 512, and with double or
60 * triple buffering enabled a multiple of 512 bytes can be kept in fly.
61 *
62 * The vendor software limits reads to 120 words (15 slices, 540 bytes) at
63 * a time. So far, it appears safe to increase this to 224 words (28 slices,
64 * 1008 bytes), thus making the most of two 512 byte buffers.
65 */
66#define READ_CHUNK_LEN (28 * 8)
67
68/** Calculate the required buffer size in 16-bit units for reading a given
69 * number of device memory words. Rounded to a multiple of 8 device words.
70 */
71#define LWLA1034_MEMBUF_LEN(count) (((count) + 7) / 8 * 18)
72
73/** Maximum number of 16-bit words sent at a time during acquisition.
74 * Used for allocating the libusb transfer buffer.
75 */
76#define MAX_ACQ_SEND_WORDS 8 /* 5 for memory read request plus stuffing */
77
78/** Maximum number of 16-bit words received at a time during acquisition.
79 * Round to the next multiple of the endpoint buffer size to avoid nasty
80 * transfer overflow conditions on hiccups.
81 */
82#define MAX_ACQ_RECV_WORDS ((READ_CHUNK_LEN / 4 * 9 + 255) / 256 * 256)
83
84/** Maximum length of a register write sequence.
85 */
86#define MAX_REG_WRITE_SEQ_LEN 5
87
88/** Default configured samplerate.
89 */
90#define DEFAULT_SAMPLERATE SR_MHZ(125)
91
92/** LWLA clock sources.
93 */
94enum clock_source {
95 CLOCK_SOURCE_NONE,
96 CLOCK_SOURCE_INT,
97 CLOCK_SOURCE_EXT_RISE,
98 CLOCK_SOURCE_EXT_FALL,
99};
100
101/** LWLA device states.
102 */
103enum device_state {
104 STATE_IDLE = 0,
105
106 STATE_START_CAPTURE,
107
108 STATE_STATUS_WAIT,
109 STATE_STATUS_REQUEST,
110 STATE_STATUS_RESPONSE,
111
112 STATE_STOP_CAPTURE,
113
114 STATE_LENGTH_REQUEST,
115 STATE_LENGTH_RESPONSE,
116
117 STATE_READ_PREPARE,
118 STATE_READ_REQUEST,
119 STATE_READ_RESPONSE,
120 STATE_READ_END,
121};
122
123/** LWLA run-length encoding states.
124 */
125enum rle_state {
126 RLE_STATE_DATA,
127 RLE_STATE_LEN
128};
129
130/** LWLA sample acquisition and decompression state.
131 */
132struct acquisition_state {
133 uint64_t sample;
134 uint64_t run_len;
135
136 /** Number of samples acquired so far. */
137 uint64_t captured_samples;
138 /** Number of samples sent to the session bus. */
139 uint64_t transferred_samples;
140
141 /** Capture memory fill level. */
142 size_t mem_addr_fill;
aeaad0b0 143
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144 size_t mem_addr_done;
145 size_t mem_addr_next;
146 size_t mem_addr_stop;
147
148 size_t out_offset;
149
150 struct libusb_transfer *xfer_in;
151 struct libusb_transfer *xfer_out;
152
153 unsigned int capture_flags;
154
155 enum rle_state rle;
156
157 /* Payload data buffers for outgoing and incoming transfers. */
158 uint16_t xfer_buf_out[MAX_ACQ_SEND_WORDS];
159 uint16_t xfer_buf_in[MAX_ACQ_RECV_WORDS];
160
161 /* Payload buffer for sigrok logic packets. */
162 uint8_t out_packet[PACKET_SIZE];
163};
164
165/** Private, per-device-instance driver context.
166 */
aeaad0b0 167struct dev_context {
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168 /** The samplerate selected by the user. */
169 uint64_t samplerate;
170
171 /** The maximimum number of samples to acquire. */
172 uint64_t limit_samples;
173
174 /** Channels to use. */
175 uint64_t channel_mask;
176
177 uint64_t trigger_mask;
178 uint64_t trigger_edge_mask;
179 uint64_t trigger_values;
aeaad0b0 180
5874e88d 181 struct acquisition_state *acquisition;
aeaad0b0 182
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183 struct regval_pair reg_write_seq[MAX_REG_WRITE_SEQ_LEN];
184 int reg_write_pos;
185 int reg_write_len;
aeaad0b0 186
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187 enum device_state state;
188 enum device_state next_state;
aeaad0b0 189
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190 /** The currently configured clock source of the device. */
191 enum clock_source cur_clock_source;
192 /** The clock source selected by the user. */
193 enum clock_source selected_clock_source;
194
195 /* Indicates that stopping the acquisition is currently in progress. */
196 gboolean stopping_in_progress;
197
198 /* Indicates whether a transfer failed. */
199 gboolean transfer_error;
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200};
201
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202SR_PRIV struct acquisition_state *lwla_alloc_acquisition_state(void);
203SR_PRIV void lwla_free_acquisition_state(struct acquisition_state *acq);
204
205SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi);
206SR_PRIV int lwla_set_clock_source(const struct sr_dev_inst *sdi);
207SR_PRIV int lwla_setup_acquisition(const struct sr_dev_inst *sdi);
208SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi);
209SR_PRIV int lwla_abort_acquisition(const struct sr_dev_inst *sdi);
210
211SR_PRIV int lwla_receive_data(int fd, int revents, void *cb_data);
aeaad0b0 212
5874e88d 213#endif /* !LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H */