[libsigrok.git] / hardware / sysclk-lwla / protocol.h

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
#define LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H

#define LOG_PREFIX "sysclk-lwla"

#include "lwla.h"
#include "libsigrok.h"
#include "libsigrok-internal.h"
#include <stdint.h>
#include <glib.h>

/* For now, only the LWLA1034 is supported.
 */
#define VENDOR_NAME	"SysClk"
#define MODEL_NAME	"LWLA1034"

#define USB_VID_PID	"2961.6689"
#define USB_INTERFACE	0
#define USB_TIMEOUT	3000 /* ms */

#define NUM_PROBES	34
#define TRIGGER_TYPES	"01fr"

/* Bit mask covering all 34 channels.
 */
#define ALL_CHANNELS_MASK (((uint64_t)1 << NUM_PROBES) - 1)

/** Unit and packet size for the sigrok logic datafeed.
 */
#define UNIT_SIZE	((NUM_PROBES + 7) / 8)
#define PACKET_LENGTH	10000	/* units */

/** Size of the acquisition buffer in device memory units.
 */
#define MEMORY_DEPTH	(256 * 1024)	/* 256k x 36 bit */

/** Number of device memory units (36 bit) to read at a time.  Slices of 8
 * consecutive 36-bit words are mapped to 9 32-bit words each, so the chunk
 * length should be a multiple of 8 to ensure alignment to slice boundaries.
 *
 * Experimentation has shown that reading chunks larger than about 1024 bytes
 * is unreliable.  The threshold seems to relate to the buffer size on the FX2
 * USB chip:  The configured endpoint buffer size is 512, and with double or
 * triple buffering enabled a multiple of 512 bytes can be kept in fly.
 *
 * The vendor software limits reads to 120 words (15 slices, 540 bytes) at
 * a time.  So far, it appears safe to increase this to 224 words (28 slices,
 * 1008 bytes), thus making the most of two 512 byte buffers.
 */
#define READ_CHUNK_LEN	(28 * 8)

/** Calculate the required buffer size in 32-bit units for reading a given
 * number of device memory words.  Rounded to a multiple of 8 device words.
 */
#define LWLA1034_MEMBUF_LEN(count) (((count) + 7) / 8 * 9)

/** Maximum number of 16-bit words sent at a time during acquisition.
 * Used for allocating the libusb transfer buffer.
 */
#define MAX_ACQ_SEND_WORDS	8 /* 5 for memory read request plus stuffing */

/** Maximum number of 32-bit words received at a time during acquisition.
 * Round to the next multiple of the endpoint buffer size to avoid nasty
 * transfer overflow conditions on hiccups.
 */
#define MAX_ACQ_RECV_LEN	((READ_CHUNK_LEN / 8 * 9 + 127) / 128 * 128)

/** Maximum length of a register write sequence.
 */
#define MAX_REG_WRITE_SEQ_LEN   5

/** Default configured samplerate.
 */
#define DEFAULT_SAMPLERATE	SR_MHZ(125)

/** Maximum configurable sample count limit.
 */
#define MAX_LIMIT_SAMPLES	(UINT64_C(1) << 48)

/** Maximum configurable capture duration in milliseconds.
 */
#define MAX_LIMIT_MSEC		(UINT64_C(1) << 32)

/** LWLA1034 FPGA clock configurations.
 */
enum clock_config {
	CONF_CLOCK_NONE,
	CONF_CLOCK_INT,
	CONF_CLOCK_EXT_RISE,
	CONF_CLOCK_EXT_FALL,
};

/** Available clock sources.
 */
enum clock_source {
	CLOCK_INTERNAL,
	CLOCK_EXT_CLK,
};

/** Available trigger sources.
 */
enum trigger_source {
	TRIGGER_CHANNELS = 0,
	TRIGGER_EXT_TRG,
};

/** Available edge choices for the external clock and trigger inputs.
 */
enum signal_edge {
	EDGE_POSITIVE = 0,
	EDGE_NEGATIVE,
};

/** LWLA device states.
 */
enum device_state {
	STATE_IDLE = 0,

	STATE_START_CAPTURE,

	STATE_STATUS_WAIT,
	STATE_STATUS_REQUEST,
	STATE_STATUS_RESPONSE,

	STATE_STOP_CAPTURE,

	STATE_LENGTH_REQUEST,
	STATE_LENGTH_RESPONSE,

	STATE_READ_PREPARE,
	STATE_READ_REQUEST,
	STATE_READ_RESPONSE,
	STATE_READ_END,
};

/** LWLA run-length encoding states.
 */
enum rle_state {
	RLE_STATE_DATA,
	RLE_STATE_LEN
};

/** LWLA sample acquisition and decompression state.
 */
struct acquisition_state {
	uint64_t sample;
	uint64_t run_len;

	/** Maximum number of samples to process. */
	uint64_t samples_max;
	/** Number of samples sent to the session bus. */
	uint64_t samples_done;

	/** Maximum duration of capture, in milliseconds. */
	uint64_t duration_max;
	/** Running capture duration since trigger event. */
	uint64_t duration_now;

	/** Capture memory fill level. */
	size_t mem_addr_fill;

	size_t mem_addr_done;
	size_t mem_addr_next;
	size_t mem_addr_stop;

	size_t out_index;

	struct libusb_transfer *xfer_in;
	struct libusb_transfer *xfer_out;

	unsigned int capture_flags;

	enum rle_state rle;

	/** Whether to bypass the clock divider. */
	gboolean bypass_clockdiv;

	/* Payload data buffers for incoming and outgoing transfers. */
	uint32_t xfer_buf_in[MAX_ACQ_RECV_LEN];
	uint16_t xfer_buf_out[MAX_ACQ_SEND_WORDS];

	/* Payload buffer for sigrok logic packets. */
	uint8_t out_packet[PACKET_LENGTH * UNIT_SIZE];
};

/** Private, per-device-instance driver context.
 */
struct dev_context {
	/** The samplerate selected by the user. */
	uint64_t samplerate;

	/** The maximimum sampling duration, in milliseconds. */
	uint64_t limit_msec;

	/** The maximimum number of samples to acquire. */
	uint64_t limit_samples;

	/** Channels to use. */
	uint64_t channel_mask;

	uint64_t trigger_mask;
	uint64_t trigger_edge_mask;
	uint64_t trigger_values;

	struct acquisition_state *acquisition;

	struct regval_pair reg_write_seq[MAX_REG_WRITE_SEQ_LEN];
	int reg_write_pos;
	int reg_write_len;

	enum device_state state;

	/** The currently active clock configuration of the device. */
	enum clock_config cur_clock_config;

	/** Clock source configuration setting. */
	enum clock_source cfg_clock_source;
	/** Clock edge configuration setting. */
	enum signal_edge cfg_clock_edge;

	/** Trigger source configuration setting. */
	enum trigger_source cfg_trigger_source;
	/** Trigger slope configuration setting. */
	enum signal_edge cfg_trigger_slope;

	/* Indicates that stopping the acquisition is currently in progress. */
	gboolean stopping_in_progress;

	/* Indicates whether a transfer failed. */
	gboolean transfer_error;
};

SR_PRIV struct acquisition_state *lwla_alloc_acquisition_state(void);
SR_PRIV void lwla_free_acquisition_state(struct acquisition_state *acq);

SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi);
SR_PRIV int lwla_set_clock_config(const struct sr_dev_inst *sdi);
SR_PRIV int lwla_setup_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi);
SR_PRIV int lwla_abort_acquisition(const struct sr_dev_inst *sdi);

SR_PRIV int lwla_receive_data(int fd, int revents, void *cb_data);

#endif /* !LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H */
Commit	Line	Data
aeaad0b0 DE	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com>
	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation, either version 3 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#ifndef LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
	21	#define LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
	22
5874e88d DE	23	#define LOG_PREFIX "sysclk-lwla"
	24
	25	#include "lwla.h"
aeaad0b0 DE	26	#include "libsigrok.h"
aeaad0b0 DE	27	#include "libsigrok-internal.h"
5874e88d DE	28	#include <stdint.h>
5874e88d DE	29	#include <glib.h>
aeaad0b0	30
5874e88d DE	31	/* For now, only the LWLA1034 is supported.
	32	*/
	33	#define VENDOR_NAME "SysClk"
	34	#define MODEL_NAME "LWLA1034"
	35
	36	#define USB_VID_PID "2961.6689"
	37	#define USB_INTERFACE 0
	38	#define USB_TIMEOUT 3000 /* ms */
	39
	40	#define NUM_PROBES 34
	41	#define TRIGGER_TYPES "01fr"
	42
43db3436 DE	43	/* Bit mask covering all 34 channels.
	44	*/
	45	#define ALL_CHANNELS_MASK (((uint64_t)1 << NUM_PROBES) - 1)
	46
5874e88d DE	47	/** Unit and packet size for the sigrok logic datafeed.
	48	*/
	49	#define UNIT_SIZE ((NUM_PROBES + 7) / 8)
2cfd16a3	50	#define PACKET_LENGTH 10000 /* units */
5874e88d DE	51
	52	/** Size of the acquisition buffer in device memory units.
	53	*/
	54	#define MEMORY_DEPTH (256 * 1024) /* 256k x 36 bit */
	55
	56	/** Number of device memory units (36 bit) to read at a time. Slices of 8
	57	* consecutive 36-bit words are mapped to 9 32-bit words each, so the chunk
	58	* length should be a multiple of 8 to ensure alignment to slice boundaries.
	59	*
	60	* Experimentation has shown that reading chunks larger than about 1024 bytes
	61	* is unreliable. The threshold seems to relate to the buffer size on the FX2
	62	* USB chip: The configured endpoint buffer size is 512, and with double or
	63	* triple buffering enabled a multiple of 512 bytes can be kept in fly.
	64	*
	65	* The vendor software limits reads to 120 words (15 slices, 540 bytes) at
	66	* a time. So far, it appears safe to increase this to 224 words (28 slices,
	67	* 1008 bytes), thus making the most of two 512 byte buffers.
	68	*/
	69	#define READ_CHUNK_LEN (28 * 8)
	70
e0df15d4	71	/** Calculate the required buffer size in 32-bit units for reading a given
5874e88d DE	72	* number of device memory words. Rounded to a multiple of 8 device words.
5874e88d DE	73	*/
e0df15d4	74	#define LWLA1034_MEMBUF_LEN(count) (((count) + 7) / 8 * 9)
5874e88d DE	75
	76	/** Maximum number of 16-bit words sent at a time during acquisition.
	77	* Used for allocating the libusb transfer buffer.
	78	*/
	79	#define MAX_ACQ_SEND_WORDS 8 /* 5 for memory read request plus stuffing */
	80
e0df15d4	81	/** Maximum number of 32-bit words received at a time during acquisition.
5874e88d DE	82	* Round to the next multiple of the endpoint buffer size to avoid nasty
	83	* transfer overflow conditions on hiccups.
	84	*/
e0df15d4	85	#define MAX_ACQ_RECV_LEN ((READ_CHUNK_LEN / 8 * 9 + 127) / 128 * 128)
5874e88d DE	86
	87	/** Maximum length of a register write sequence.
	88	*/
	89	#define MAX_REG_WRITE_SEQ_LEN 5
	90
	91	/** Default configured samplerate.
	92	*/
	93	#define DEFAULT_SAMPLERATE SR_MHZ(125)
	94
29d58767 DE	95	/** Maximum configurable sample count limit.
	96	*/
	97	#define MAX_LIMIT_SAMPLES (UINT64_C(1) << 48)
	98
	99	/** Maximum configurable capture duration in milliseconds.
	100	*/
	101	#define MAX_LIMIT_MSEC (UINT64_C(1) << 32)
	102
6358f0a9 DE	103	/** LWLA1034 FPGA clock configurations.
	104	*/
	105	enum clock_config {
	106	CONF_CLOCK_NONE,
	107	CONF_CLOCK_INT,
	108	CONF_CLOCK_EXT_RISE,
	109	CONF_CLOCK_EXT_FALL,
	110	};
	111
	112	/** Available clock sources.
5874e88d DE	113	*/
5874e88d DE	114	enum clock_source {
6358f0a9 DE	115	CLOCK_INTERNAL,
6358f0a9 DE	116	CLOCK_EXT_CLK,
5874e88d DE	117	};
5874e88d DE	118
e6e54bd2 DE	119	/** Available trigger sources.
	120	*/
	121	enum trigger_source {
	122	TRIGGER_CHANNELS = 0,
	123	TRIGGER_EXT_TRG,
	124	};
	125
6358f0a9	126	/** Available edge choices for the external clock and trigger inputs.
e6e54bd2	127	*/
6358f0a9 DE	128	enum signal_edge {
	129	EDGE_POSITIVE = 0,
	130	EDGE_NEGATIVE,
e6e54bd2 DE	131	};
e6e54bd2 DE	132
5874e88d DE	133	/** LWLA device states.
	134	*/
	135	enum device_state {
	136	STATE_IDLE = 0,
	137
	138	STATE_START_CAPTURE,
	139
	140	STATE_STATUS_WAIT,
	141	STATE_STATUS_REQUEST,
	142	STATE_STATUS_RESPONSE,
	143
	144	STATE_STOP_CAPTURE,
	145
	146	STATE_LENGTH_REQUEST,
	147	STATE_LENGTH_RESPONSE,
	148
	149	STATE_READ_PREPARE,
	150	STATE_READ_REQUEST,
	151	STATE_READ_RESPONSE,
	152	STATE_READ_END,
	153	};
	154
	155	/** LWLA run-length encoding states.
	156	*/
	157	enum rle_state {
	158	RLE_STATE_DATA,
	159	RLE_STATE_LEN
	160	};
	161
	162	/** LWLA sample acquisition and decompression state.
	163	*/
	164	struct acquisition_state {
	165	uint64_t sample;
	166	uint64_t run_len;
	167
29d58767 DE	168	/** Maximum number of samples to process. */
29d58767 DE	169	uint64_t samples_max;
5874e88d	170	/** Number of samples sent to the session bus. */
29d58767 DE	171	uint64_t samples_done;
	172
	173	/** Maximum duration of capture, in milliseconds. */
	174	uint64_t duration_max;
	175	/** Running capture duration since trigger event. */
	176	uint64_t duration_now;
5874e88d DE	177
	178	/** Capture memory fill level. */
	179	size_t mem_addr_fill;
aeaad0b0	180
5874e88d DE	181	size_t mem_addr_done;
	182	size_t mem_addr_next;
	183	size_t mem_addr_stop;
	184
2cfd16a3	185	size_t out_index;
5874e88d DE	186
	187	struct libusb_transfer *xfer_in;
	188	struct libusb_transfer *xfer_out;
	189
	190	unsigned int capture_flags;
	191
	192	enum rle_state rle;
	193
29d58767 DE	194	/** Whether to bypass the clock divider. */
	195	gboolean bypass_clockdiv;
	196
e0df15d4 DE	197	/* Payload data buffers for incoming and outgoing transfers. */
e0df15d4 DE	198	uint32_t xfer_buf_in[MAX_ACQ_RECV_LEN];
5874e88d	199	uint16_t xfer_buf_out[MAX_ACQ_SEND_WORDS];
5874e88d DE	200
5874e88d DE	201	/* Payload buffer for sigrok logic packets. */
2cfd16a3	202	uint8_t out_packet[PACKET_LENGTH * UNIT_SIZE];
5874e88d DE	203	};
	204
	205	/** Private, per-device-instance driver context.
	206	*/
aeaad0b0	207	struct dev_context {
5874e88d DE	208	/** The samplerate selected by the user. */
	209	uint64_t samplerate;
	210
29d58767 DE	211	/** The maximimum sampling duration, in milliseconds. */
	212	uint64_t limit_msec;
	213
5874e88d DE	214	/** The maximimum number of samples to acquire. */
	215	uint64_t limit_samples;
	216
	217	/** Channels to use. */
	218	uint64_t channel_mask;
	219
	220	uint64_t trigger_mask;
	221	uint64_t trigger_edge_mask;
	222	uint64_t trigger_values;
aeaad0b0	223
5874e88d	224	struct acquisition_state *acquisition;
aeaad0b0	225
5874e88d DE	226	struct regval_pair reg_write_seq[MAX_REG_WRITE_SEQ_LEN];
	227	int reg_write_pos;
	228	int reg_write_len;
aeaad0b0	229
5874e88d	230	enum device_state state;
aeaad0b0	231
6358f0a9 DE	232	/** The currently active clock configuration of the device. */
	233	enum clock_config cur_clock_config;
	234
	235	/** Clock source configuration setting. */
	236	enum clock_source cfg_clock_source;
	237	/** Clock edge configuration setting. */
	238	enum signal_edge cfg_clock_edge;
5874e88d	239
e6e54bd2 DE	240	/** Trigger source configuration setting. */
	241	enum trigger_source cfg_trigger_source;
	242	/** Trigger slope configuration setting. */
6358f0a9	243	enum signal_edge cfg_trigger_slope;
e6e54bd2	244
5874e88d DE	245	/* Indicates that stopping the acquisition is currently in progress. */
	246	gboolean stopping_in_progress;
	247
	248	/* Indicates whether a transfer failed. */
	249	gboolean transfer_error;
aeaad0b0 DE	250	};
aeaad0b0 DE	251
5874e88d DE	252	SR_PRIV struct acquisition_state *lwla_alloc_acquisition_state(void);
	253	SR_PRIV void lwla_free_acquisition_state(struct acquisition_state *acq);
	254
	255	SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi);
6358f0a9	256	SR_PRIV int lwla_set_clock_config(const struct sr_dev_inst *sdi);
5874e88d DE	257	SR_PRIV int lwla_setup_acquisition(const struct sr_dev_inst *sdi);
	258	SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi);
	259	SR_PRIV int lwla_abort_acquisition(const struct sr_dev_inst *sdi);
	260
	261	SR_PRIV int lwla_receive_data(int fd, int revents, void *cb_data);
aeaad0b0	262
5874e88d	263	#endif /* !LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H */