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aeaad0b0 DE |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com> | |
5 | * | |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 3 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "protocol.h" | |
5874e88d | 21 | #include <string.h> |
aeaad0b0 | 22 | |
5874e88d DE |
23 | /* Bit mask covering all 34 channels. */ |
24 | #define ALL_CHANNELS_MASK (((uint64_t)1 << NUM_PROBES) - 1) | |
25 | ||
26 | /* Bit mask for the RLE repeat-count-follows flag. */ | |
27 | #define RLE_FLAG_LEN_FOLLOWS ((uint64_t)1 << 35) | |
28 | ||
29 | /* Start address of capture status memory area to read. */ | |
30 | #define CAP_STAT_ADDR 5 | |
31 | ||
32 | /* Number of 64-bit words read from the capture status memory. */ | |
33 | #define CAP_STAT_LEN 5 | |
34 | ||
35 | /* The bitstream filenames are indexed by the clock source enumeration. | |
36 | */ | |
37 | static const char *const bitstream_map[] = { | |
38 | FIRMWARE_DIR "/sysclk-lwla1034-off.bitstream", | |
39 | FIRMWARE_DIR "/sysclk-lwla1034-int.bitstream", | |
40 | FIRMWARE_DIR "/sysclk-lwla1034-extpos.bitstream", | |
41 | FIRMWARE_DIR "/sysclk-lwla1034-extneg.bitstream", | |
42 | }; | |
43 | ||
44 | /* Submit an already filled-in USB transfer. | |
45 | */ | |
46 | static int submit_transfer(struct dev_context *devc, | |
47 | struct libusb_transfer *xfer) | |
48 | { | |
49 | int ret; | |
50 | ||
51 | ret = libusb_submit_transfer(xfer); | |
52 | ||
53 | if (ret != 0) { | |
54 | sr_err("Submit transfer failed: %s.", libusb_error_name(ret)); | |
55 | devc->transfer_error = TRUE; | |
56 | return SR_ERR; | |
57 | } | |
58 | ||
59 | return SR_OK; | |
60 | } | |
61 | ||
62 | /* Set up the LWLA in preparation for an acquisition session. | |
63 | */ | |
64 | static int capture_setup(const struct sr_dev_inst *sdi) | |
aeaad0b0 | 65 | { |
aeaad0b0 | 66 | struct dev_context *devc; |
5874e88d DE |
67 | uint64_t divider_count; |
68 | uint64_t memory_limit; | |
69 | uint16_t command[3 + 10*4]; | |
aeaad0b0 | 70 | |
5874e88d | 71 | devc = sdi->priv; |
aeaad0b0 | 72 | |
5874e88d DE |
73 | command[0] = LWLA_WORD(CMD_CAP_SETUP); |
74 | command[1] = LWLA_WORD(0); /* address */ | |
75 | command[2] = LWLA_WORD(10); /* length */ | |
76 | ||
77 | command[3] = LWLA_WORD_0(devc->channel_mask); | |
78 | command[4] = LWLA_WORD_1(devc->channel_mask); | |
79 | command[5] = LWLA_WORD_2(devc->channel_mask); | |
80 | command[6] = LWLA_WORD_3(devc->channel_mask); | |
81 | ||
82 | /* Set the clock divide counter maximum for samplerates of up to | |
83 | * 100 MHz. At the highest samplerate of 125 MHz the clock divider | |
84 | * is bypassed. | |
85 | */ | |
86 | if (devc->samplerate > 0 && devc->samplerate < SR_MHZ(100)) | |
87 | divider_count = SR_MHZ(100) / devc->samplerate - 1; | |
88 | else | |
89 | divider_count = 0; | |
90 | ||
91 | command[7] = LWLA_WORD_0(divider_count); | |
92 | command[8] = LWLA_WORD_1(divider_count); | |
93 | command[9] = LWLA_WORD_2(divider_count); | |
94 | command[10] = LWLA_WORD_3(divider_count); | |
95 | ||
96 | command[11] = LWLA_WORD_0(devc->trigger_values); | |
97 | command[12] = LWLA_WORD_1(devc->trigger_values); | |
98 | command[13] = LWLA_WORD_2(devc->trigger_values); | |
99 | command[14] = LWLA_WORD_3(devc->trigger_values); | |
100 | ||
101 | command[15] = LWLA_WORD_0(devc->trigger_edge_mask); | |
102 | command[16] = LWLA_WORD_1(devc->trigger_edge_mask); | |
103 | command[17] = LWLA_WORD_2(devc->trigger_edge_mask); | |
104 | command[18] = LWLA_WORD_3(devc->trigger_edge_mask); | |
105 | ||
106 | command[19] = LWLA_WORD_0(devc->trigger_mask); | |
107 | command[20] = LWLA_WORD_1(devc->trigger_mask); | |
108 | command[21] = LWLA_WORD_2(devc->trigger_mask); | |
109 | command[22] = LWLA_WORD_3(devc->trigger_mask); | |
110 | ||
111 | /* Set the capture memory full threshold. This is slightly less | |
112 | * than the actual maximum, most likely in order to compensate for | |
113 | * pipeline latency. | |
114 | */ | |
115 | memory_limit = MEMORY_DEPTH - 16; | |
116 | ||
117 | command[23] = LWLA_WORD_0(memory_limit); | |
118 | command[24] = LWLA_WORD_1(memory_limit); | |
119 | command[25] = LWLA_WORD_2(memory_limit); | |
120 | command[26] = LWLA_WORD_3(memory_limit); | |
121 | ||
122 | /* Fill remaining 64-bit words with zeroes. */ | |
123 | memset(&command[27], 0, 16 * sizeof(uint16_t)); | |
124 | ||
125 | return lwla_send_command(sdi->conn, command, G_N_ELEMENTS(command)); | |
126 | } | |
127 | ||
128 | /* Issue a register write command as an asynchronous USB transfer. | |
129 | */ | |
130 | static int issue_write_reg(const struct sr_dev_inst *sdi, | |
131 | unsigned int reg, unsigned int value) | |
132 | { | |
133 | struct dev_context *devc; | |
134 | struct acquisition_state *acq; | |
135 | ||
136 | devc = sdi->priv; | |
137 | acq = devc->acquisition; | |
138 | ||
139 | acq->xfer_buf_out[0] = LWLA_WORD(CMD_WRITE_REG); | |
140 | acq->xfer_buf_out[1] = LWLA_WORD(reg); | |
141 | acq->xfer_buf_out[2] = LWLA_WORD_0(value); | |
142 | acq->xfer_buf_out[3] = LWLA_WORD_1(value); | |
143 | ||
144 | acq->xfer_out->length = 4 * sizeof(uint16_t); | |
145 | ||
146 | return submit_transfer(devc, acq->xfer_out); | |
147 | } | |
148 | ||
149 | /* Issue a register write command as an asynchronous USB transfer for the | |
150 | * next register/value pair of the currently active register write sequence. | |
151 | */ | |
152 | static int issue_next_write_reg(const struct sr_dev_inst *sdi) | |
153 | { | |
154 | struct dev_context *devc; | |
155 | struct regval_pair *regval; | |
156 | int ret; | |
157 | ||
158 | devc = sdi->priv; | |
159 | ||
160 | if (devc->reg_write_pos >= devc->reg_write_len) { | |
161 | sr_err("Already written all registers in sequence."); | |
162 | return SR_ERR_BUG; | |
163 | } | |
164 | regval = &devc->reg_write_seq[devc->reg_write_pos]; | |
165 | ||
166 | ret = issue_write_reg(sdi, regval->reg, regval->val); | |
167 | if (ret != SR_OK) | |
168 | return ret; | |
169 | ||
170 | ++devc->reg_write_pos; | |
171 | return SR_OK; | |
172 | } | |
173 | ||
174 | /* Issue a capture status request as an asynchronous USB transfer. | |
175 | */ | |
176 | static void request_capture_status(const struct sr_dev_inst *sdi) | |
177 | { | |
178 | struct dev_context *devc; | |
179 | struct acquisition_state *acq; | |
180 | ||
181 | devc = sdi->priv; | |
182 | acq = devc->acquisition; | |
183 | ||
184 | acq->xfer_buf_out[0] = LWLA_WORD(CMD_CAP_STATUS); | |
185 | acq->xfer_buf_out[1] = LWLA_WORD(CAP_STAT_ADDR); | |
186 | acq->xfer_buf_out[2] = LWLA_WORD(CAP_STAT_LEN); | |
187 | ||
188 | acq->xfer_out->length = 3 * sizeof(uint16_t); | |
189 | ||
190 | if (submit_transfer(devc, acq->xfer_out) == SR_OK) | |
191 | devc->state = STATE_STATUS_REQUEST; | |
192 | } | |
193 | ||
194 | /* Issue a request for the capture buffer fill level as | |
195 | * an asynchronous USB transfer. | |
196 | */ | |
197 | static void request_capture_length(const struct sr_dev_inst *sdi) | |
198 | { | |
199 | struct dev_context *devc; | |
200 | struct acquisition_state *acq; | |
201 | ||
202 | devc = sdi->priv; | |
203 | acq = devc->acquisition; | |
204 | ||
205 | acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_REG); | |
206 | acq->xfer_buf_out[1] = LWLA_WORD(REG_MEM_FILL); | |
207 | ||
208 | acq->xfer_out->length = 2 * sizeof(uint16_t); | |
209 | ||
210 | if (submit_transfer(devc, acq->xfer_out) == SR_OK) | |
211 | devc->state = STATE_LENGTH_REQUEST; | |
212 | } | |
213 | ||
214 | /* Initiate the capture memory read operation: Reset the acquisition state | |
215 | * and start a sequence of register writes in order to set up the device for | |
216 | * reading from the capture buffer. | |
217 | */ | |
218 | static void issue_read_start(const struct sr_dev_inst *sdi) | |
219 | { | |
220 | struct dev_context *devc; | |
221 | struct acquisition_state *acq; | |
222 | struct regval_pair *regvals; | |
223 | ||
224 | devc = sdi->priv; | |
225 | acq = devc->acquisition; | |
226 | ||
227 | /* Reset RLE state. */ | |
228 | acq->rle = RLE_STATE_DATA; | |
229 | acq->sample = 0; | |
230 | acq->run_len = 0; | |
231 | ||
232 | acq->captured_samples = 0; | |
233 | acq->transferred_samples = 0; | |
234 | ||
235 | /* For some reason, the start address is 4 rather than 0. */ | |
236 | acq->mem_addr_done = 4; | |
237 | acq->mem_addr_next = 4; | |
238 | acq->mem_addr_stop = acq->mem_addr_fill; | |
239 | ||
240 | /* Byte offset into the packet output buffer. */ | |
241 | acq->out_offset = 0; | |
242 | ||
243 | regvals = devc->reg_write_seq; | |
244 | ||
245 | regvals[0].reg = REG_DIV_BYPASS; | |
246 | regvals[0].val = 1; | |
247 | ||
248 | regvals[1].reg = REG_MEM_CTRL2; | |
249 | regvals[1].val = 2; | |
250 | ||
251 | regvals[2].reg = REG_MEM_CTRL4; | |
252 | regvals[2].val = 4; | |
253 | ||
254 | devc->reg_write_pos = 0; | |
255 | devc->reg_write_len = 3; | |
256 | ||
257 | if (issue_next_write_reg(sdi) == SR_OK) | |
258 | devc->state = STATE_READ_PREPARE; | |
259 | } | |
260 | ||
261 | static void issue_read_end(const struct sr_dev_inst *sdi) | |
262 | { | |
263 | struct dev_context *devc; | |
264 | ||
265 | devc = sdi->priv; | |
266 | ||
267 | if (issue_write_reg(sdi, REG_DIV_BYPASS, 0) == SR_OK) | |
268 | devc->state = STATE_READ_END; | |
269 | } | |
270 | ||
271 | /* Decode an incoming reponse to a buffer fill level request and act on it | |
272 | * as appropriate. Note that this function changes the device context state. | |
273 | */ | |
274 | static void process_capture_length(const struct sr_dev_inst *sdi) | |
275 | { | |
276 | struct dev_context *devc; | |
277 | struct acquisition_state *acq; | |
278 | ||
279 | devc = sdi->priv; | |
280 | acq = devc->acquisition; | |
281 | ||
282 | if (acq->xfer_in->actual_length != 4) { | |
283 | sr_err("Received size %d doesn't match expected size 4.", | |
284 | acq->xfer_in->actual_length); | |
285 | devc->transfer_error = TRUE; | |
286 | return; | |
287 | } | |
288 | acq->mem_addr_fill = LWLA_READ32(acq->xfer_buf_in); | |
289 | ||
290 | sr_dbg("%lu words in capture buffer.", | |
291 | (unsigned long)acq->mem_addr_fill); | |
292 | ||
293 | if (acq->mem_addr_fill > 0 && sdi->status == SR_ST_ACTIVE) | |
294 | issue_read_start(sdi); | |
295 | else | |
296 | issue_read_end(sdi); | |
297 | } | |
298 | ||
299 | /* Initiate a sequence of register write commands with the effect of | |
300 | * cancelling a running capture operation. This sets a new device state | |
301 | * if issuing the first command succeeds. | |
302 | */ | |
303 | static void issue_stop_capture(const struct sr_dev_inst *sdi) | |
304 | { | |
305 | struct dev_context *devc; | |
306 | struct regval_pair *regvals; | |
307 | ||
308 | devc = sdi->priv; | |
309 | ||
310 | if (devc->stopping_in_progress) | |
311 | return; | |
312 | ||
313 | regvals = devc->reg_write_seq; | |
314 | ||
315 | regvals[0].reg = REG_CMD_CTRL2; | |
316 | regvals[0].val = 10; | |
317 | ||
318 | regvals[1].reg = REG_CMD_CTRL3; | |
319 | regvals[1].val = 0; | |
320 | ||
321 | regvals[2].reg = REG_CMD_CTRL4; | |
322 | regvals[2].val = 0; | |
323 | ||
324 | regvals[3].reg = REG_CMD_CTRL1; | |
325 | regvals[3].val = 0; | |
326 | ||
327 | regvals[4].reg = REG_DIV_BYPASS; | |
328 | regvals[4].val = 0; | |
329 | ||
330 | devc->reg_write_pos = 0; | |
331 | devc->reg_write_len = 5; | |
332 | ||
333 | if (issue_next_write_reg(sdi) == SR_OK) { | |
334 | devc->stopping_in_progress = TRUE; | |
335 | devc->state = STATE_STOP_CAPTURE; | |
336 | } | |
337 | } | |
338 | ||
339 | /* Decode an incoming capture status reponse and act on it as appropriate. | |
340 | * Note that this function changes the device state. | |
341 | */ | |
342 | static void process_capture_status(const struct sr_dev_inst *sdi) | |
343 | { | |
344 | struct dev_context *devc; | |
345 | struct acquisition_state *acq; | |
346 | ||
347 | devc = sdi->priv; | |
348 | acq = devc->acquisition; | |
349 | ||
350 | if (acq->xfer_in->actual_length != CAP_STAT_LEN * 8) { | |
351 | sr_err("Received size %d doesn't match expected size %d.", | |
352 | acq->xfer_in->actual_length, CAP_STAT_LEN * 8); | |
353 | devc->transfer_error = TRUE; | |
354 | return; | |
355 | } | |
356 | ||
357 | /* TODO: Find out the actual bit width of these fields as stored | |
358 | * in the FPGA. These fields are definitely less than 64 bit wide | |
359 | * internally, and the unused bits occasionally even contain garbage. | |
360 | */ | |
361 | acq->mem_addr_fill = LWLA_READ32(&acq->xfer_buf_in[0]); | |
362 | acq->captured_samples = LWLA_READ32(&acq->xfer_buf_in[8]) | |
363 | * (uint64_t)100000; | |
364 | acq->capture_flags = LWLA_READ32(&acq->xfer_buf_in[16]) | |
365 | & STATUS_FLAG_MASK; | |
366 | ||
367 | sr_spew("Captured %lu words, %" PRIu64 " samples, flags 0x%02X", | |
368 | (unsigned long)acq->mem_addr_fill, | |
369 | acq->captured_samples, acq->capture_flags); | |
370 | ||
371 | if (acq->captured_samples >= devc->limit_samples) { | |
372 | issue_stop_capture(sdi); | |
373 | return; | |
374 | } | |
375 | devc->state = STATE_STATUS_WAIT; | |
376 | ||
377 | if ((acq->capture_flags & STATUS_TRIGGERED) == 0) { | |
378 | sr_spew("Waiting for trigger."); | |
379 | } else if ((acq->capture_flags & STATUS_MEM_AVAIL) == 0) { | |
380 | sr_dbg("Capture memory filled."); | |
381 | request_capture_length(sdi); | |
382 | } else if ((acq->capture_flags & STATUS_CAPTURING) != 0) { | |
383 | sr_spew("Sampling in progress."); | |
384 | } | |
385 | } | |
386 | ||
387 | /* Issue a capture buffer read request as an asynchronous USB transfer. | |
388 | * The address and size of the memory area to read are derived from the | |
389 | * current acquisition state. | |
390 | */ | |
391 | static void request_read_mem(const struct sr_dev_inst *sdi) | |
392 | { | |
393 | struct dev_context *devc; | |
394 | struct acquisition_state *acq; | |
395 | size_t count; | |
396 | ||
397 | devc = sdi->priv; | |
398 | acq = devc->acquisition; | |
399 | ||
400 | if (acq->mem_addr_next >= acq->mem_addr_stop) | |
401 | return; | |
402 | ||
403 | /* Always read a multiple of 8 device words. */ | |
404 | count = (acq->mem_addr_stop - acq->mem_addr_next + 7) / 8 * 8; | |
405 | count = MIN(count, READ_CHUNK_LEN); | |
406 | ||
407 | acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM); | |
408 | acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next); | |
409 | acq->xfer_buf_out[2] = LWLA_WORD_1(acq->mem_addr_next); | |
410 | acq->xfer_buf_out[3] = LWLA_WORD_0(count); | |
411 | acq->xfer_buf_out[4] = LWLA_WORD_1(count); | |
412 | ||
413 | acq->xfer_out->length = 5 * sizeof(uint16_t); | |
414 | ||
415 | if (submit_transfer(devc, acq->xfer_out) == SR_OK) { | |
416 | acq->mem_addr_next += count; | |
417 | devc->state = STATE_READ_REQUEST; | |
418 | } | |
419 | } | |
420 | ||
421 | /* Send a packet of logic samples to the session bus. The payload is taken | |
422 | * from the acquisition state. The return value indicates whether to stop | |
423 | * reading more samples. | |
424 | */ | |
425 | static gboolean send_logic_packet(const struct sr_dev_inst *sdi) | |
426 | { | |
427 | uint64_t samples; | |
428 | struct dev_context *devc; | |
429 | struct acquisition_state *acq; | |
430 | struct sr_datafeed_packet packet; | |
431 | struct sr_datafeed_logic logic; | |
432 | int last; | |
433 | ||
434 | devc = sdi->priv; | |
435 | acq = devc->acquisition; | |
aeaad0b0 | 436 | |
5874e88d | 437 | if (acq->transferred_samples >= devc->limit_samples) |
aeaad0b0 DE |
438 | return TRUE; |
439 | ||
5874e88d DE |
440 | packet.type = SR_DF_LOGIC; |
441 | packet.payload = &logic; | |
442 | logic.unitsize = UNIT_SIZE; | |
443 | logic.data = acq->out_packet; | |
444 | logic.length = acq->out_offset; | |
445 | ||
446 | samples = acq->out_offset / UNIT_SIZE; | |
447 | last = FALSE; | |
448 | ||
449 | /* Cut the packet short if necessary. */ | |
450 | if (acq->transferred_samples + samples >= devc->limit_samples) { | |
451 | samples = devc->limit_samples - acq->transferred_samples; | |
452 | logic.length = samples * UNIT_SIZE; | |
453 | last = TRUE; | |
454 | } | |
455 | acq->transferred_samples += samples; | |
456 | acq->out_offset = 0; | |
457 | ||
458 | /* Send off logic datafeed packet. */ | |
459 | sr_session_send(sdi, &packet); | |
460 | ||
461 | return last; | |
462 | } | |
463 | ||
464 | /* Demangle and decompress incoming sample data from the capture buffer. | |
465 | * The data chunk is taken from the acquisition state, and is expected to | |
466 | * contain a multiple of 8 device words. | |
467 | * All data currently in the acquisition buffer will be processed. Packets | |
468 | * of decoded samples are sent off to the session bus whenever the output | |
469 | * buffer becomes full while decoding. | |
470 | */ | |
471 | static int process_sample_data(const struct sr_dev_inst *sdi) | |
472 | { | |
473 | uint64_t sample; | |
474 | uint64_t run_len; | |
475 | uint64_t high_nibbles; | |
476 | uint64_t word; | |
477 | struct dev_context *devc; | |
478 | struct acquisition_state *acq; | |
479 | uint8_t *out_p; | |
480 | uint16_t *slice; | |
481 | size_t expect_len; | |
482 | size_t actual_len; | |
483 | size_t in_words_left; | |
484 | size_t si; | |
485 | ||
486 | devc = sdi->priv; | |
487 | acq = devc->acquisition; | |
488 | ||
489 | if (acq->mem_addr_done >= acq->mem_addr_stop | |
490 | || acq->transferred_samples >= devc->limit_samples) | |
491 | return SR_OK; | |
492 | ||
493 | in_words_left = MIN(acq->mem_addr_stop - acq->mem_addr_done, | |
494 | READ_CHUNK_LEN); | |
495 | expect_len = LWLA1034_MEMBUF_LEN(in_words_left) * sizeof(uint16_t); | |
496 | actual_len = acq->xfer_in->actual_length; | |
497 | ||
498 | if (actual_len != expect_len) { | |
499 | sr_err("Received size %lu does not match expected size %lu.", | |
500 | (unsigned long)actual_len, (unsigned long)expect_len); | |
501 | devc->transfer_error = TRUE; | |
502 | return SR_ERR; | |
503 | } | |
504 | acq->mem_addr_done += in_words_left; | |
505 | slice = acq->xfer_buf_in; | |
506 | si = 0; /* word index within slice */ | |
507 | ||
508 | for (;;) { | |
509 | sample = acq->sample; | |
510 | /* Expand run-length samples into session packet. */ | |
511 | for (run_len = acq->run_len; run_len > 0; --run_len) { | |
512 | out_p = &acq->out_packet[acq->out_offset]; | |
513 | out_p[0] = sample & 0xFF; | |
514 | out_p[1] = (sample >> 8) & 0xFF; | |
515 | out_p[2] = (sample >> 16) & 0xFF; | |
516 | out_p[3] = (sample >> 24) & 0xFF; | |
517 | out_p[4] = (sample >> 32) & 0xFF; | |
518 | acq->out_offset += UNIT_SIZE; | |
519 | ||
520 | /* Send out packet if it is full. */ | |
521 | if (acq->out_offset > PACKET_SIZE - UNIT_SIZE) | |
522 | if (send_logic_packet(sdi)) | |
523 | return SR_OK; /* sample limit reached */ | |
524 | } | |
525 | acq->run_len = 0; | |
526 | ||
527 | if (in_words_left == 0) | |
528 | break; /* done with current chunk */ | |
529 | ||
530 | /* Now work on the current slice. */ | |
531 | high_nibbles = LWLA_READ32(&slice[8 * 2]); | |
532 | word = LWLA_READ32(&slice[si * 2]); | |
533 | word |= (high_nibbles << (4 * si + 4)) & ((uint64_t)0xF << 32); | |
534 | ||
535 | if (acq->rle == RLE_STATE_DATA) { | |
536 | acq->sample = word & ALL_CHANNELS_MASK; | |
537 | acq->run_len = ((word >> NUM_PROBES) & 1) + 1; | |
538 | if (word & RLE_FLAG_LEN_FOLLOWS) | |
539 | acq->rle = RLE_STATE_LEN; | |
540 | } else { | |
541 | acq->run_len += word << 1; | |
542 | acq->rle = RLE_STATE_DATA; | |
543 | } | |
544 | ||
545 | /* Move to next word. */ | |
546 | if (++si >= 8) { | |
547 | si = 0; | |
548 | slice += 9 * 2; | |
549 | } | |
550 | --in_words_left; | |
551 | } | |
552 | ||
553 | /* Send out partially filled packet if it is the last one. */ | |
554 | if (acq->mem_addr_done >= acq->mem_addr_stop && acq->out_offset > 0) | |
555 | send_logic_packet(sdi); | |
556 | ||
557 | return SR_OK; | |
558 | } | |
559 | ||
560 | /* Finish an acquisition session. This sends the end packet to the session | |
561 | * bus and removes the listener for asynchronous USB transfers. | |
562 | */ | |
563 | static void end_acquisition(struct sr_dev_inst *sdi) | |
564 | { | |
565 | struct drv_context *drvc; | |
566 | struct dev_context *devc; | |
567 | struct sr_datafeed_packet packet; | |
568 | ||
569 | drvc = sdi->driver->priv; | |
570 | devc = sdi->priv; | |
571 | ||
572 | if (devc->state == STATE_IDLE) | |
573 | return; | |
574 | ||
575 | devc->state = STATE_IDLE; | |
576 | ||
577 | /* Remove USB file descriptors from polling. */ | |
578 | usb_source_remove(drvc->sr_ctx); | |
579 | ||
580 | packet.type = SR_DF_END; | |
581 | sr_session_send(sdi, &packet); | |
582 | ||
583 | lwla_free_acquisition_state(devc->acquisition); | |
584 | devc->acquisition = NULL; | |
585 | ||
586 | sdi->status = SR_ST_ACTIVE; | |
587 | } | |
588 | ||
589 | /* USB output transfer completion callback. | |
590 | */ | |
591 | static void receive_transfer_out(struct libusb_transfer *transfer) | |
592 | { | |
593 | struct sr_dev_inst *sdi; | |
594 | struct dev_context *devc; | |
595 | ||
596 | sdi = transfer->user_data; | |
597 | devc = sdi->priv; | |
598 | ||
599 | if (transfer->status != LIBUSB_TRANSFER_COMPLETED) { | |
600 | sr_err("Transfer to device failed: %d.", transfer->status); | |
601 | devc->transfer_error = TRUE; | |
602 | return; | |
603 | } | |
604 | ||
605 | if (devc->reg_write_pos < devc->reg_write_len) { | |
606 | issue_next_write_reg(sdi); | |
607 | } else { | |
608 | switch (devc->state) { | |
609 | case STATE_START_CAPTURE: | |
610 | devc->state = STATE_STATUS_WAIT; | |
611 | break; | |
612 | case STATE_STATUS_REQUEST: | |
613 | devc->state = STATE_STATUS_RESPONSE; | |
614 | submit_transfer(devc, devc->acquisition->xfer_in); | |
615 | break; | |
616 | case STATE_STOP_CAPTURE: | |
617 | if (sdi->status == SR_ST_ACTIVE) | |
618 | request_capture_length(sdi); | |
619 | else | |
620 | end_acquisition(sdi); | |
621 | break; | |
622 | case STATE_LENGTH_REQUEST: | |
623 | devc->state = STATE_LENGTH_RESPONSE; | |
624 | submit_transfer(devc, devc->acquisition->xfer_in); | |
625 | break; | |
626 | case STATE_READ_PREPARE: | |
627 | request_read_mem(sdi); | |
628 | break; | |
629 | case STATE_READ_REQUEST: | |
630 | devc->state = STATE_READ_RESPONSE; | |
631 | submit_transfer(devc, devc->acquisition->xfer_in); | |
632 | break; | |
633 | case STATE_READ_END: | |
634 | end_acquisition(sdi); | |
635 | break; | |
636 | default: | |
637 | sr_err("Unexpected device state %d.", devc->state); | |
638 | break; | |
639 | } | |
640 | } | |
641 | } | |
642 | ||
643 | /* USB input transfer completion callback. | |
644 | */ | |
645 | static void receive_transfer_in(struct libusb_transfer *transfer) | |
646 | { | |
647 | struct sr_dev_inst *sdi; | |
648 | struct dev_context *devc; | |
649 | struct acquisition_state *acq; | |
650 | ||
651 | sdi = transfer->user_data; | |
652 | devc = sdi->priv; | |
653 | acq = devc->acquisition; | |
654 | ||
655 | if (transfer->status != LIBUSB_TRANSFER_COMPLETED) { | |
656 | sr_err("Transfer from device failed: %d.", transfer->status); | |
657 | devc->transfer_error = TRUE; | |
658 | return; | |
659 | } | |
660 | ||
661 | switch (devc->state) { | |
662 | case STATE_STATUS_RESPONSE: | |
663 | process_capture_status(sdi); | |
664 | break; | |
665 | case STATE_LENGTH_RESPONSE: | |
666 | process_capture_length(sdi); | |
667 | break; | |
668 | case STATE_READ_RESPONSE: | |
669 | if (process_sample_data(sdi) == SR_OK | |
670 | && acq->mem_addr_next < acq->mem_addr_stop | |
671 | && acq->transferred_samples < devc->limit_samples) | |
672 | request_read_mem(sdi); | |
673 | else | |
674 | issue_read_end(sdi); | |
675 | break; | |
676 | default: | |
677 | sr_err("Unexpected device state %d.", devc->state); | |
678 | break; | |
679 | } | |
680 | } | |
681 | ||
682 | /* Initialize the LWLA. This downloads a bitstream into the FPGA | |
683 | * and executes a simple device test sequence. | |
684 | */ | |
685 | SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi) | |
686 | { | |
687 | struct dev_context *devc; | |
688 | int ret; | |
689 | uint32_t value; | |
690 | ||
691 | devc = sdi->priv; | |
692 | ||
693 | /* Select internal clock if it hasn't been set yet */ | |
694 | if (devc->selected_clock_source == CLOCK_SOURCE_NONE) | |
695 | devc->selected_clock_source = CLOCK_SOURCE_INT; | |
696 | ||
697 | /* Force reload of bitstream */ | |
698 | devc->cur_clock_source = CLOCK_SOURCE_NONE; | |
699 | ||
700 | ret = lwla_set_clock_source(sdi); | |
701 | ||
702 | if (ret != SR_OK) | |
703 | return ret; | |
704 | ||
705 | ret = lwla_write_reg(sdi->conn, REG_CMD_CTRL2, 100); | |
706 | if (ret != SR_OK) | |
707 | return ret; | |
708 | ||
709 | ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL1, &value); | |
710 | if (ret != SR_OK) | |
711 | return ret; | |
712 | sr_info("Received test word 0x%08X back.", value); | |
713 | if (value != 0x12345678) | |
714 | return SR_ERR; | |
715 | ||
716 | ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL4, &value); | |
717 | if (ret != SR_OK) | |
718 | return ret; | |
719 | sr_info("Received test word 0x%08X back.", value); | |
720 | if (value != 0x12345678) | |
721 | return SR_ERR; | |
722 | ||
723 | ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL3, &value); | |
724 | if (ret != SR_OK) | |
725 | return ret; | |
726 | sr_info("Received test word 0x%08X back.", value); | |
727 | if (value != 0x87654321) | |
728 | return SR_ERR; | |
729 | ||
730 | return ret; | |
731 | } | |
732 | ||
733 | /* Select the LWLA clock source. If the clock source changed from the | |
734 | * previous setting, this will download a new bitstream to the FPGA. | |
735 | */ | |
736 | SR_PRIV int lwla_set_clock_source(const struct sr_dev_inst *sdi) | |
737 | { | |
738 | struct dev_context *devc; | |
739 | int ret; | |
740 | enum clock_source selected; | |
741 | ||
742 | devc = sdi->priv; | |
743 | selected = devc->selected_clock_source; | |
744 | ||
745 | if (devc->cur_clock_source != selected) { | |
746 | devc->cur_clock_source = CLOCK_SOURCE_NONE; | |
747 | ||
748 | if (selected >= 0 && selected < G_N_ELEMENTS(bitstream_map)) { | |
749 | ret = lwla_send_bitstream(sdi->conn, | |
750 | bitstream_map[selected]); | |
751 | if (ret == SR_OK) | |
752 | devc->cur_clock_source = selected; | |
753 | return ret; | |
754 | } | |
aeaad0b0 | 755 | } |
5874e88d DE |
756 | return SR_OK; |
757 | } | |
758 | ||
759 | /* Configure the LWLA in preparation for an acquisition session. | |
760 | */ | |
761 | SR_PRIV int lwla_setup_acquisition(const struct sr_dev_inst *sdi) | |
762 | { | |
763 | struct dev_context *devc; | |
764 | struct sr_usb_dev_inst *usb; | |
765 | struct regval_pair regvals[7]; | |
766 | int ret; | |
767 | ||
768 | devc = sdi->priv; | |
769 | usb = sdi->conn; | |
770 | ||
771 | regvals[0].reg = REG_MEM_CTRL2; | |
772 | regvals[0].val = 2; | |
773 | ||
774 | regvals[1].reg = REG_MEM_CTRL2; | |
775 | regvals[1].val = 1; | |
776 | ||
777 | regvals[2].reg = REG_CMD_CTRL2; | |
778 | regvals[2].val = 10; | |
779 | ||
780 | regvals[3].reg = REG_CMD_CTRL3; | |
781 | regvals[3].val = 0x74; | |
782 | ||
783 | regvals[4].reg = REG_CMD_CTRL4; | |
784 | regvals[4].val = 0; | |
785 | ||
786 | regvals[5].reg = REG_CMD_CTRL1; | |
787 | regvals[5].val = 0; | |
788 | ||
789 | regvals[6].reg = REG_DIV_BYPASS; | |
790 | regvals[6].val = (devc->samplerate > SR_MHZ(100)) ? 1 : 0; | |
791 | ||
792 | ret = lwla_write_regs(usb, regvals, G_N_ELEMENTS(regvals)); | |
793 | if (ret != SR_OK) | |
794 | return ret; | |
795 | ||
796 | return capture_setup(sdi); | |
797 | } | |
798 | ||
799 | /* Start the capture operation on the LWLA device. Beginning with this | |
800 | * function, all USB transfers will be asynchronous until the end of the | |
801 | * acquisition session. | |
802 | */ | |
803 | SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi) | |
804 | { | |
805 | struct dev_context *devc; | |
806 | struct sr_usb_dev_inst *usb; | |
807 | struct acquisition_state *acq; | |
808 | struct regval_pair *regvals; | |
809 | ||
810 | devc = sdi->priv; | |
811 | usb = sdi->conn; | |
812 | acq = devc->acquisition; | |
813 | ||
814 | libusb_fill_bulk_transfer(acq->xfer_out, usb->devhdl, EP_COMMAND, | |
815 | (unsigned char *)acq->xfer_buf_out, 0, | |
816 | &receive_transfer_out, | |
817 | (struct sr_dev_inst *)sdi, USB_TIMEOUT); | |
818 | ||
819 | libusb_fill_bulk_transfer(acq->xfer_in, usb->devhdl, EP_REPLY, | |
820 | (unsigned char *)acq->xfer_buf_in, | |
821 | sizeof acq->xfer_buf_in, | |
822 | &receive_transfer_in, | |
823 | (struct sr_dev_inst *)sdi, USB_TIMEOUT); | |
824 | ||
825 | regvals = devc->reg_write_seq; | |
826 | ||
827 | regvals[0].reg = REG_CMD_CTRL2; | |
828 | regvals[0].val = 10; | |
829 | ||
830 | regvals[1].reg = REG_CMD_CTRL3; | |
831 | regvals[1].val = 1; | |
832 | ||
833 | regvals[2].reg = REG_CMD_CTRL4; | |
834 | regvals[2].val = 0; | |
835 | ||
836 | regvals[3].reg = REG_CMD_CTRL1; | |
837 | regvals[3].val = 0; | |
838 | ||
839 | devc->reg_write_pos = 0; | |
840 | devc->reg_write_len = 4; | |
841 | ||
842 | devc->state = STATE_START_CAPTURE; | |
843 | ||
844 | return issue_next_write_reg(sdi); | |
845 | } | |
846 | ||
847 | /* Allocate an acquisition state object. | |
848 | */ | |
849 | SR_PRIV struct acquisition_state *lwla_alloc_acquisition_state(void) | |
850 | { | |
851 | struct acquisition_state *acq; | |
852 | ||
853 | acq = g_try_new0(struct acquisition_state, 1); | |
854 | if (!acq) { | |
855 | sr_err("Acquisition state malloc failed."); | |
856 | return NULL; | |
857 | } | |
858 | ||
859 | acq->xfer_in = libusb_alloc_transfer(0); | |
860 | if (!acq->xfer_in) { | |
861 | sr_err("Transfer malloc failed."); | |
862 | g_free(acq); | |
863 | return NULL; | |
864 | } | |
865 | ||
866 | acq->xfer_out = libusb_alloc_transfer(0); | |
867 | if (!acq->xfer_out) { | |
868 | sr_err("Transfer malloc failed."); | |
869 | libusb_free_transfer(acq->xfer_in); | |
870 | g_free(acq); | |
871 | return NULL; | |
872 | } | |
873 | ||
874 | return acq; | |
875 | } | |
876 | ||
877 | /* Deallocate an acquisition state object. | |
878 | */ | |
879 | SR_PRIV void lwla_free_acquisition_state(struct acquisition_state *acq) | |
880 | { | |
881 | if (acq) { | |
882 | libusb_free_transfer(acq->xfer_out); | |
883 | libusb_free_transfer(acq->xfer_in); | |
884 | g_free(acq); | |
885 | } | |
886 | } | |
887 | ||
888 | /* USB I/O source callback. | |
889 | */ | |
890 | SR_PRIV int lwla_receive_data(int fd, int revents, void *cb_data) | |
891 | { | |
892 | struct sr_dev_inst *sdi; | |
893 | struct dev_context *devc; | |
894 | struct drv_context *drvc; | |
895 | struct timeval tv; | |
896 | int ret; | |
897 | ||
898 | (void)fd; | |
899 | ||
900 | sdi = cb_data; | |
901 | devc = sdi->priv; | |
902 | drvc = sdi->driver->priv; | |
903 | ||
904 | if (!devc || !drvc) | |
905 | return FALSE; | |
906 | ||
907 | /* No timeout: return immediately. */ | |
908 | tv.tv_sec = 0; | |
909 | tv.tv_usec = 0; | |
910 | ||
911 | ret = libusb_handle_events_timeout_completed(drvc->sr_ctx->libusb_ctx, | |
912 | &tv, NULL); | |
913 | if (ret != 0) | |
914 | sr_err("Event handling failed: %s.", libusb_error_name(ret)); | |
915 | ||
916 | /* If no event flags are set the timeout must have expired. */ | |
917 | if (revents == 0 && devc->state == STATE_STATUS_WAIT) { | |
918 | if (sdi->status == SR_ST_STOPPING) | |
919 | issue_stop_capture(sdi); | |
920 | else | |
921 | request_capture_status(sdi); | |
922 | } | |
923 | ||
924 | /* Check if an error occurred on a transfer. */ | |
925 | if (devc->transfer_error) | |
926 | end_acquisition(sdi); | |
aeaad0b0 DE |
927 | |
928 | return TRUE; | |
929 | } |