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rigol-ds: On DS1000 with firmware < 0.2.4, use legacy protocol.
[libsigrok.git] / hardware / rigol-ds / api.c
CommitLineData
f4816ac6
ML		 1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2012 Martin Ling <martin-git@earth.li>
88e429c9 5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
bafd4890 6 * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de>
f4816ac6
ML		 7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
e0b7d23c
ML		 22#include <fcntl.h>
23#include <unistd.h>
24#include <stdlib.h>
25#include <string.h>
2b0e4a46 26#include <math.h>
f4816ac6
ML		 27#include <glib.h>
28#include "libsigrok.h"
29#include "libsigrok-internal.h"
30#include "protocol.h"
31
ca55277c
ML		 32static const int32_t hwopts[] = {
33 SR_CONF_CONN,
0dc7b43e 34 SR_CONF_SERIALCOMM
ca55277c
ML		 35};
36
f6a0ac9f 37static const int32_t hwcaps[] = {
1953564a 38 SR_CONF_OSCILLOSCOPE,
1953564a
BV		 39 SR_CONF_TIMEBASE,
40 SR_CONF_TRIGGER_SOURCE,
41 SR_CONF_TRIGGER_SLOPE,
42 SR_CONF_HORIZ_TRIGGERPOS,
d62d7ad1 43 SR_CONF_NUM_TIMEBASE,
c1bcb8cc 44 SR_CONF_LIMIT_FRAMES,
4914dd4b 45 SR_CONF_SAMPLERATE,
f48e0249
ML		 46};
47
48static const int32_t analog_hwcaps[] = {
d62d7ad1 49 SR_CONF_NUM_VDIV,
f48e0249 50 SR_CONF_VDIV,
78bcc55a 51 SR_CONF_COUPLING,
babab622 52 SR_CONF_DATA_SOURCE,
e0b7d23c
ML		 53};
54
f6a0ac9f 55static const uint64_t timebases[][2] = {
e0b7d23c 56 /* nanoseconds */
8e06edf5 57 { 1, 1000000000 },
e0b7d23c
ML		 58 { 2, 1000000000 },
59 { 5, 1000000000 },
60 { 10, 1000000000 },
61 { 20, 1000000000 },
62 { 50, 1000000000 },
63 { 100, 1000000000 },
64 { 500, 1000000000 },
65 /* microseconds */
66 { 1, 1000000 },
67 { 2, 1000000 },
68 { 5, 1000000 },
69 { 10, 1000000 },
70 { 20, 1000000 },
71 { 50, 1000000 },
72 { 100, 1000000 },
73 { 200, 1000000 },
74 { 500, 1000000 },
75 /* milliseconds */
76 { 1, 1000 },
77 { 2, 1000 },
78 { 5, 1000 },
79 { 10, 1000 },
80 { 20, 1000 },
81 { 50, 1000 },
82 { 100, 1000 },
83 { 200, 1000 },
84 { 500, 1000 },
85 /* seconds */
86 { 1, 1 },
87 { 2, 1 },
88 { 5, 1 },
89 { 10, 1 },
90 { 20, 1 },
91 { 50, 1 },
bafd4890
ML		 92 { 100, 1 },
93 { 200, 1 },
94 { 500, 1 },
8e06edf5 95 { 1000, 1 },
e0b7d23c
ML		 96};
97
f6a0ac9f 98static const uint64_t vdivs[][2] = {
bafd4890
ML		 99 /* microvolts */
100 { 500, 1000000 },
e0b7d23c 101 /* millivolts */
bafd4890 102 { 1, 1000 },
e0b7d23c
ML		 103 { 2, 1000 },
104 { 5, 1000 },
105 { 10, 1000 },
106 { 20, 1000 },
107 { 50, 1000 },
108 { 100, 1000 },
109 { 200, 1000 },
110 { 500, 1000 },
111 /* volts */
112 { 1, 1 },
113 { 2, 1 },
114 { 5, 1 },
115 { 10, 1 },
e0b7d23c
ML		 116};
117
bafd4890
ML		 118#define NUM_TIMEBASE ARRAY_SIZE(timebases)
119#define NUM_VDIV ARRAY_SIZE(vdivs)
120
e0b7d23c
ML		 121static const char *trigger_sources[] = {
122 "CH1",
123 "CH2",
821fbcad
ML		 124 "CH3",
125 "CH4",
e0b7d23c
ML		 126 "EXT",
127 "AC Line",
6bb192bc
ML		 128 "D0",
129 "D1",
130 "D2",
131 "D3",
132 "D4",
133 "D5",
134 "D6",
135 "D7",
136 "D8",
137 "D9",
138 "D10",
139 "D11",
140 "D12",
141 "D13",
142 "D14",
143 "D15",
e0b7d23c
ML		 144};
145
146static const char *coupling[] = {
147 "AC",
148 "DC",
149 "GND",
e0b7d23c
ML		 150};
151
babab622
ML		 152/* Do not change the order of entries */
153static const char *data_sources[] = {
154 "Live",
155 "Memory",
156 "Segmented",
157};
158
159/*
160 * name, series, protocol flavor, min timebase, max timebase, min vdiv,
161 * digital channels, number of horizontal divs
162 */
10afee13
ML		 163
164#define RIGOL "Rigol Technologies"
165#define AGILENT "Agilent Technologies"
fcdebbe8
BV		 166#define RIGOL_SHORT "Rigol"
167#define AGILENT_SHORT "Agilent"
10afee13 168
bafd4890 169static const struct rigol_ds_model supported_models[] = {
470140fc
ML		 170 {RIGOL, "DS1052E", RIGOL_DS1000, PROTOCOL_IEEE488_2, {5, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
171 {RIGOL, "DS1102E", RIGOL_DS1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
172 {RIGOL, "DS1152E", RIGOL_DS1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
173 {RIGOL, "DS1052D", RIGOL_DS1000, PROTOCOL_IEEE488_2, {5, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
174 {RIGOL, "DS1102D", RIGOL_DS1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
175 {RIGOL, "DS1152D", RIGOL_DS1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
821fbcad
ML		 176 {RIGOL, "DS2072", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {500, 1}, {500, 1000000}, 2, false, 14},
177 {RIGOL, "DS2102", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {500, 1}, {500, 1000000}, 2, false, 14},
178 {RIGOL, "DS2202", RIGOL_DS2000, PROTOCOL_IEEE488_2, {2, 1000000000}, {500, 1}, {500, 1000000}, 2, false, 14},
036d378a
AJ		 179 {RIGOL, "DS2302", RIGOL_DS2000, PROTOCOL_IEEE488_2, {1, 1000000000}, {1000, 1}, {500, 1000000}, 2, false, 14},
180 {RIGOL, "DS2072A", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {1000, 1}, {500, 1000000}, 2, false, 14},
181 {RIGOL, "DS2102A", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {1000, 1}, {500, 1000000}, 2, false, 14},
182 {RIGOL, "DS2202A", RIGOL_DS2000, PROTOCOL_IEEE488_2, {2, 1000000000}, {1000, 1}, {500, 1000000}, 2, false, 14},
183 {RIGOL, "DS2302A", RIGOL_DS2000, PROTOCOL_IEEE488_2, {1, 1000000000}, {1000, 1}, {500, 1000000}, 2, false, 14},
821fbcad
ML		 184 {RIGOL, "VS5022", RIGOL_VS5000, PROTOCOL_LEGACY, {20, 1000000000}, {50, 1}, {2, 1000}, 2, false, 14},
185 {RIGOL, "VS5022D", RIGOL_VS5000, PROTOCOL_LEGACY, {20, 1000000000}, {50, 1}, {2, 1000}, 2, true, 14},
186 {RIGOL, "VS5042", RIGOL_VS5000, PROTOCOL_LEGACY, {10, 1000000000}, {50, 1}, {2, 1000}, 2, false, 14},
187 {RIGOL, "VS5042D", RIGOL_VS5000, PROTOCOL_LEGACY, {10, 1000000000}, {50, 1}, {2, 1000}, 2, true, 14},
188 {RIGOL, "VS5062", RIGOL_VS5000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, 2, false, 14},
189 {RIGOL, "VS5062D", RIGOL_VS5000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, 2, true, 14},
190 {RIGOL, "VS5102", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 14},
191 {RIGOL, "VS5102D", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 14},
192 {RIGOL, "VS5202", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 14},
193 {RIGOL, "VS5202D", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 14},
227a0981
ML		 194 {AGILENT, "DSO1002A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {5, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
195 {AGILENT, "DSO1004A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {5, 1000000000}, {50, 1}, {2, 1000}, 4, false, 12},
196 {AGILENT, "DSO1012A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
821fbcad 197 {AGILENT, "DSO1014A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 4, false, 12},
227a0981
ML		 198 {AGILENT, "DSO1022A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
199 {AGILENT, "DSO1024A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 4, false, 12},
512bb890
BV		 200};
201
3086efdd
ML		 202SR_PRIV struct sr_dev_driver rigol_ds_driver_info;
203static struct sr_dev_driver *di = &rigol_ds_driver_info;
f4816ac6 204
fa85f376 205static void clear_helper(void *priv)
f4816ac6 206{
f4816ac6 207 struct dev_context *devc;
f4816ac6 208
ba358ffd 209 devc = priv;
babab622
ML		 210 g_free(devc->data);
211 g_free(devc->buffer);
fa85f376
UH		 212 g_free(devc->coupling[0]);
213 g_free(devc->coupling[1]);
214 g_free(devc->trigger_source);
215 g_free(devc->trigger_slope);
ba358ffd
BV		 216 g_slist_free(devc->analog_groups[0].probes);
217 g_slist_free(devc->analog_groups[1].probes);
218 g_slist_free(devc->digital_group.probes);
fa85f376 219}
f4816ac6 220
3b412e3a 221static int dev_clear(void)
fa85f376
UH		 222{
223 return std_dev_clear(di, clear_helper);
f4816ac6
ML		 224}
225
254dd102
BV		 226static int set_cfg(const struct sr_dev_inst *sdi, const char *format, ...)
227{
254dd102 228 va_list args;
4d7a9a14 229 int ret;
254dd102 230
254dd102 231 va_start(args, format);
4d7a9a14 232 ret = sr_scpi_send_variadic(sdi->conn, format, args);
254dd102 233 va_end(args);
4d7a9a14
ML		 234
235 if (ret != SR_OK)
254dd102
BV		 236 return SR_ERR;
237
51bfe536 238 return sr_scpi_get_opc(sdi->conn);
254dd102
BV		 239}
240
6078d2c9 241static int init(struct sr_context *sr_ctx)
f4816ac6 242{
f6beaac5 243 return std_init(sr_ctx, di, LOG_PREFIX);
f4816ac6
ML		 244}
245
3520422f 246static int probe_port(const char *resource, const char *serialcomm, GSList **devices)
f4816ac6 247{
cc9fd2d2
BV		 248 struct dev_context *devc;
249 struct sr_dev_inst *sdi;
ae1bc1cc
ML		 250 struct sr_scpi_dev_inst *scpi;
251 struct sr_scpi_hw_info *hw_info;
cc9fd2d2 252 struct sr_probe *probe;
8dd0b290 253 long n[3];
f6a0ac9f 254 unsigned int i;
bafd4890 255 const struct rigol_ds_model *model = NULL;
8dd0b290 256 gchar *channel_name, *vendor, **version;
fb6e5ba8 257
46a743c1 258 *devices = NULL;
0dc7b43e 259
c3515cea
AJ		 260 if (!(scpi = scpi_dev_inst_new(resource, serialcomm)))
261 return SR_ERR;
9bd4c956 262
ae1bc1cc 263 if (sr_scpi_open(scpi) != SR_OK) {
10afee13 264 sr_info("Couldn't open SCPI device.");
ae1bc1cc 265 sr_scpi_free(scpi);
9bd4c956 266 return SR_ERR;
ae1bc1cc 267 };
9bd4c956 268
ae1bc1cc
ML		 269 if (sr_scpi_get_hw_id(scpi, &hw_info) != SR_OK) {
270 sr_info("Couldn't get IDN response.");
271 sr_scpi_close(scpi);
272 sr_scpi_free(scpi);
273 return SR_ERR;
ca55277c 274 }
e0b7d23c 275
ca55277c 276 for (i = 0; i < ARRAY_SIZE(supported_models); i++) {
10afee13
ML		 277 if (!strcasecmp(hw_info->manufacturer, supported_models[i].vendor) &&
278 !strcmp(hw_info->model, supported_models[i].name)) {
bafd4890 279 model = &supported_models[i];
ca55277c 280 break;
fb6e5ba8 281 }
ca55277c 282 }
fb6e5ba8 283
fcdebbe8
BV		 284 if (!strcmp(hw_info->manufacturer, RIGOL))
285 vendor = RIGOL_SHORT;
286 else if (!strcmp(hw_info->manufacturer, AGILENT))
287 vendor = AGILENT_SHORT;
288 else
289 vendor = hw_info->manufacturer;
bafd4890 290 if (!model || !(sdi = sr_dev_inst_new(0, SR_ST_ACTIVE,
fcdebbe8 291 vendor, hw_info->model,
ae1bc1cc
ML		 292 hw_info->firmware_version))) {
293 sr_scpi_hw_info_free(hw_info);
b4936bae 294 sr_scpi_close(scpi);
ae1bc1cc 295 sr_scpi_free(scpi);
ca55277c
ML		 296 return SR_ERR_NA;
297 }
fb6e5ba8 298
b4936bae 299 sr_scpi_close(scpi);
ae1bc1cc
ML		 300
301 sdi->conn = scpi;
fb6e5ba8 302
cc9fd2d2 303 sdi->driver = di;
ae1bc1cc 304 sdi->inst_type = SR_INST_SCPI;
512bb890 305
cc9fd2d2 306 if (!(devc = g_try_malloc0(sizeof(struct dev_context))))
ca55277c 307 return SR_ERR_MALLOC;
ae1bc1cc 308
cc9fd2d2 309 devc->limit_frames = 0;
bafd4890 310 devc->model = model;
8dd0b290
BV		 311 devc->protocol = model->protocol;
312
313 /* DS1000 models with firmware before 0.2.4 used the old
314 * legacy protocol. */
315 if (model->series == RIGOL_DS1000) {
316 version = g_strsplit(hw_info->firmware_version, ".", 0);
317 do {
318 if (!version[0] || !version[1] || !version[2])
319 break;
320 if (version[0][0] == 0 || version[1][0] == 0 || version[2][0] == 0)
321 break;
322 for (i = 0; i < 3; i++) {
323 if (sr_atol(version[i], &n[i]) != SR_OK)
324 break;
325 }
326 if (i != 3)
327 break;
328 if (n[0] != 0 || n[1] > 2)
329 break;
330 if (n[1] == 2 && n[2] > 3)
331 break;
332 sr_dbg("Found DS1000 firmware < 0.2.4, using old protocol.");
333 devc->protocol = PROTOCOL_LEGACY;
334 } while(0);
335 g_strfreev(version);
336 }
337
338 sr_scpi_hw_info_free(hw_info);
512bb890 339
821fbcad
ML		 340 for (i = 0; i < model->analog_channels; i++) {
341 if (!(channel_name = g_strdup_printf("CH%d", i + 1)))
ca55277c 342 return SR_ERR_MALLOC;
821fbcad 343 probe = sr_probe_new(i, SR_PROBE_ANALOG, TRUE, channel_name);
ca55277c 344 sdi->probes = g_slist_append(sdi->probes, probe);
3d3a601e
ML		 345 devc->analog_groups[i].name = channel_name;
346 devc->analog_groups[i].probes = g_slist_append(NULL, probe);
347 sdi->probe_groups = g_slist_append(sdi->probe_groups,
348 &devc->analog_groups[i]);
ca55277c 349 }
512bb890 350
bafd4890 351 if (devc->model->has_digital) {
ca55277c
ML		 352 for (i = 0; i < 16; i++) {
353 if (!(channel_name = g_strdup_printf("D%d", i)))
354 return SR_ERR_MALLOC;
355 probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE, channel_name);
356 g_free(channel_name);
357 if (!probe)
358 return SR_ERR_MALLOC;
359 sdi->probes = g_slist_append(sdi->probes, probe);
3d3a601e
ML		 360 devc->digital_group.probes = g_slist_append(
361 devc->digital_group.probes, probe);
512bb890 362 }
b3916147
ML		 363 devc->digital_group.name = "LA";
364 sdi->probe_groups = g_slist_append(sdi->probe_groups,
365 &devc->digital_group);
ca55277c 366 }
bafd4890
ML		 367
368 for (i = 0; i < NUM_TIMEBASE; i++) {
369 if (!memcmp(&devc->model->min_timebase, &timebases[i], sizeof(uint64_t[2])))
370 devc->timebases = &timebases[i];
371 if (!memcmp(&devc->model->max_timebase, &timebases[i], sizeof(uint64_t[2])))
372 devc->num_timebases = &timebases[i] - devc->timebases + 1;
373 }
374
0709197d
ML		 375 for (i = 0; i < NUM_VDIV; i++)
376 if (!memcmp(&devc->model->min_vdiv, &vdivs[i], sizeof(uint64_t[2])))
6ff1394e 377 devc->vdivs = &vdivs[i];
bafd4890 378
babab622
ML		 379 if (!(devc->buffer = g_try_malloc(ACQ_BUFFER_SIZE)))
380 return SR_ERR_MALLOC;
381 if (!(devc->data = g_try_malloc(ACQ_BUFFER_SIZE * sizeof(float))))
382 return SR_ERR_MALLOC;
383
384 devc->data_source = DATA_SOURCE_LIVE;
385
cc9fd2d2
BV		 386 sdi->priv = devc;
387
388 *devices = g_slist_append(NULL, sdi);
512bb890 389
ca55277c
ML		 390 return SR_OK;
391}
512bb890 392
6078d2c9 393static GSList *scan(GSList *options)
ca55277c
ML		 394{
395 struct drv_context *drvc;
ca55277c 396 struct sr_config *src;
cc9fd2d2 397 GSList *l, *devices;
ca55277c 398 GDir *dir;
ca55277c 399 int ret;
cc9fd2d2
BV		 400 const gchar *dev_name;
401 gchar *port = NULL;
0dc7b43e 402 gchar *serialcomm = NULL;
fb6e5ba8 403
ca55277c 404 drvc = di->priv;
d2e0b1fa 405
ca55277c
ML		 406 for (l = options; l; l = l->next) {
407 src = l->data;
0dc7b43e
ML		 408 switch (src->key) {
409 case SR_CONF_CONN:
cc9fd2d2 410 port = (char *)g_variant_get_string(src->data, NULL);
ca55277c 411 break;
0dc7b43e
ML		 412 case SR_CONF_SERIALCOMM:
413 serialcomm = (char *)g_variant_get_string(src->data, NULL);
414 break;
fb6e5ba8 415 }
ca55277c 416 }
fb6e5ba8 417
46a743c1 418 devices = NULL;
cc9fd2d2 419 if (port) {
0dc7b43e
ML		 420 if (probe_port(port, serialcomm, &devices) == SR_ERR_MALLOC) {
421 g_free(port);
422 if (serialcomm)
423 g_free(serialcomm);
ca55277c 424 return NULL;
0dc7b43e 425 }
ca55277c 426 } else {
da970d24
BV		 427 if (!(dir = g_dir_open("/sys/class/usbmisc/", 0, NULL)))
428 if (!(dir = g_dir_open("/sys/class/usb/", 0, NULL)))
429 return NULL;
ca55277c 430 while ((dev_name = g_dir_read_name(dir))) {
cc9fd2d2 431 if (strncmp(dev_name, "usbtmc", 6))
ca55277c 432 continue;
cc9fd2d2 433 port = g_strconcat("/dev/", dev_name, NULL);
0dc7b43e 434 ret = probe_port(port, serialcomm, &devices);
cc9fd2d2 435 g_free(port);
0dc7b43e
ML		 436 if (serialcomm)
437 g_free(serialcomm);
ca55277c
ML		 438 if (ret == SR_ERR_MALLOC) {
439 g_dir_close(dir);
ca55277c 440 return NULL;
6bb192bc
ML		 441 }
442 }
ca55277c
ML		 443 g_dir_close(dir);
444 }
f4816ac6 445
46a743c1
BV		 446 /* Tack a copy of the newly found devices onto the driver list. */
447 l = g_slist_copy(devices);
448 drvc->instances = g_slist_concat(drvc->instances, l);
cc9fd2d2 449
f4816ac6
ML		 450 return devices;
451}
452
6078d2c9 453static GSList *dev_list(void)
f4816ac6 454{
0e94d524 455 return ((struct drv_context *)(di->priv))->instances;
f4816ac6
ML		 456}
457
6078d2c9 458static int dev_open(struct sr_dev_inst *sdi)
f4816ac6 459{
ae1bc1cc 460 struct sr_scpi_dev_inst *scpi = sdi->conn;
9bd4c956 461
ae1bc1cc 462 if (sr_scpi_open(scpi) < 0)
e0b7d23c 463 return SR_ERR;
e0b7d23c 464
3086efdd 465 if (rigol_ds_get_dev_cfg(sdi) != SR_OK)
254dd102 466 return SR_ERR;
f4816ac6 467
46a743c1 468 sdi->status = SR_ST_ACTIVE;
cc9fd2d2 469
f4816ac6
ML		 470 return SR_OK;
471}
472
6078d2c9 473static int dev_close(struct sr_dev_inst *sdi)
f4816ac6 474{
ae1bc1cc
ML		 475 struct sr_scpi_dev_inst *scpi;
476
477 scpi = sdi->conn;
e0b7d23c 478
ae1bc1cc
ML		 479 if (scpi) {
480 if (sr_scpi_close(scpi) < 0)
481 return SR_ERR;
cc9fd2d2
BV		 482 sdi->status = SR_ST_INACTIVE;
483 }
f4816ac6
ML		 484
485 return SR_OK;
486}
487
6078d2c9 488static int cleanup(void)
f4816ac6 489{
3b412e3a 490 return dev_clear();
f4816ac6
ML		 491}
492
5415e602
ML		 493static int analog_frame_size(const struct sr_dev_inst *sdi)
494{
495 struct dev_context *devc = sdi->priv;
496 struct sr_probe *probe;
497 int analog_probes = 0;
498 GSList *l;
499
470140fc
ML		 500 switch (devc->model->series) {
501 case RIGOL_VS5000:
502 return VS5000_ANALOG_LIVE_WAVEFORM_SIZE;
503 case RIGOL_DS1000:
504 return DS1000_ANALOG_LIVE_WAVEFORM_SIZE;
505 default:
5415e602
ML		 506 for (l = sdi->probes; l; l = l->next) {
507 probe = l->data;
508 if (probe->type == SR_PROBE_ANALOG && probe->enabled)
509 analog_probes++;
510 }
511 if (devc->data_source == DATA_SOURCE_MEMORY) {
512 if (analog_probes == 1)
513 return DS2000_ANALOG_MEM_WAVEFORM_SIZE_1C;
514 else
515 return DS2000_ANALOG_MEM_WAVEFORM_SIZE_2C;
516 } else {
517 if (devc->model->series == AGILENT_DSO1000)
518 return DSO1000_ANALOG_LIVE_WAVEFORM_SIZE;
519 else
520 return DS2000_ANALOG_LIVE_WAVEFORM_SIZE;
521 }
522 }
523}
524
d22250a9
ML		 525static int digital_frame_size(const struct sr_dev_inst *sdi)
526{
527 struct dev_context *devc = sdi->priv;
528
529 switch (devc->model->series) {
530 case RIGOL_VS5000:
531 return VS5000_DIGITAL_WAVEFORM_SIZE;
532 case RIGOL_DS1000:
533 return DS1000_DIGITAL_WAVEFORM_SIZE;
534 default:
535 return 0;
536 }
537}
538
8f996b89
ML		 539static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
540 const struct sr_probe_group *probe_group)
d62d7ad1 541{
e43fdd8d 542 struct dev_context *devc;
2b0e4a46
AJ		 543 struct sr_probe *probe;
544 const char *tmp_str;
c2b394d5 545 uint64_t samplerate;
2b0e4a46
AJ		 546 int analog_channel = -1;
547 float smallest_diff = 0.0000000001;
548 int idx = -1;
549 unsigned i;
d62d7ad1 550
e43fdd8d
BV		 551 if (!sdi || !(devc = sdi->priv))
552 return SR_ERR_ARG;
553
be60a9e4 554 /* If a probe group is specified, it must be a valid one. */
c2b394d5 555 if (probe_group && !g_slist_find(sdi->probe_groups, probe_group)) {
969edf63
ML		 556 sr_err("Invalid probe group specified.");
557 return SR_ERR;
be60a9e4
BV		 558 }
559
2b0e4a46
AJ		 560 if (probe_group) {
561 probe = g_slist_nth_data(probe_group->probes, 0);
562 if (!probe)
563 return SR_ERR;
564 if (probe->type == SR_PROBE_ANALOG) {
565 if (probe->name[2] < '1' || probe->name[2] > '4')
566 return SR_ERR;
567 analog_channel = probe->name[2] - '1';
568 }
569 }
570
d62d7ad1
BV		 571 switch (id) {
572 case SR_CONF_NUM_TIMEBASE:
0709197d 573 *data = g_variant_new_int32(devc->model->num_horizontal_divs);
d62d7ad1
BV		 574 break;
575 case SR_CONF_NUM_VDIV:
72ecba02 576 *data = g_variant_new_int32(NUM_VDIV);
babab622
ML		 577 case SR_CONF_DATA_SOURCE:
578 if (devc->data_source == DATA_SOURCE_LIVE)
579 *data = g_variant_new_string("Live");
580 else if (devc->data_source == DATA_SOURCE_MEMORY)
581 *data = g_variant_new_string("Memory");
582 else
583 *data = g_variant_new_string("Segmented");
584 break;
4914dd4b
ML		 585 case SR_CONF_SAMPLERATE:
586 if (devc->data_source == DATA_SOURCE_LIVE) {
c2b394d5 587 samplerate = analog_frame_size(sdi) /
4914dd4b
ML		 588 (devc->timebase * devc->model->num_horizontal_divs);
589 *data = g_variant_new_uint64(samplerate);
c2b394d5 590 } else {
4914dd4b 591 return SR_ERR_NA;
c2b394d5 592 }
4914dd4b 593 break;
2b0e4a46
AJ		 594 case SR_CONF_TRIGGER_SOURCE:
595 if (!strcmp(devc->trigger_source, "ACL"))
596 tmp_str = "AC Line";
597 else if (!strcmp(devc->trigger_source, "CHAN1"))
598 tmp_str = "CH1";
599 else if (!strcmp(devc->trigger_source, "CHAN2"))
600 tmp_str = "CH2";
601 else if (!strcmp(devc->trigger_source, "CHAN3"))
602 tmp_str = "CH3";
603 else if (!strcmp(devc->trigger_source, "CHAN4"))
604 tmp_str = "CH4";
605 else
606 tmp_str = devc->trigger_source;
607 *data = g_variant_new_string(tmp_str);
608 break;
609 case SR_CONF_TIMEBASE:
610 for (i = 0; i < devc->num_timebases; i++) {
611 float tb = (float)devc->timebases[i][0] / devc->timebases[i][1];
612 float diff = fabs(devc->timebase - tb);
613 if (diff < smallest_diff) {
614 smallest_diff = diff;
615 idx = i;
616 }
617 }
618 if (idx < 0)
619 return SR_ERR_NA;
620 *data = g_variant_new("(tt)", devc->timebases[idx][0],
621 devc->timebases[idx][1]);
622 break;
623 case SR_CONF_VDIV:
624 if (analog_channel < 0)
625 return SR_ERR_NA;
626 for (i = 0; i < ARRAY_SIZE(vdivs); i++) {
627 float vdiv = (float)vdivs[i][0] / vdivs[i][1];
628 float diff = fabs(devc->vdiv[analog_channel] - vdiv);
629 if (diff < smallest_diff) {
630 smallest_diff = diff;
631 idx = i;
632 }
633 }
634 if (idx < 0)
635 return SR_ERR_NA;
636 *data = g_variant_new("(tt)", vdivs[idx][0], vdivs[idx][1]);
637 break;
638 case SR_CONF_COUPLING:
639 if (analog_channel < 0)
640 return SR_ERR_NA;
641 *data = g_variant_new_string(devc->coupling[analog_channel]);
642 break;
d62d7ad1 643 default:
bd6fbf62 644 return SR_ERR_NA;
d62d7ad1
BV		 645 }
646
647 return SR_OK;
648}
649
8f996b89
ML		 650static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi,
651 const struct sr_probe_group *probe_group)
f4816ac6 652{
29d957ce 653 struct dev_context *devc;
f6a0ac9f 654 uint64_t tmp_u64, p, q;
254dd102 655 double t_dbl;
f48e0249 656 unsigned int i, j;
254dd102
BV		 657 int ret;
658 const char *tmp_str;
889ef4a0 659 char buffer[16];
f4816ac6 660
e43fdd8d
BV		 661 if (!(devc = sdi->priv))
662 return SR_ERR_ARG;
29d957ce 663
e73ffd42
BV		 664 if (sdi->status != SR_ST_ACTIVE)
665 return SR_ERR_DEV_CLOSED;
f4816ac6 666
be60a9e4 667 /* If a probe group is specified, it must be a valid one. */
c2b394d5 668 if (probe_group && !g_slist_find(sdi->probe_groups, probe_group)) {
969edf63
ML		 669 sr_err("Invalid probe group specified.");
670 return SR_ERR;
be60a9e4
BV		 671 }
672
f4816ac6 673 ret = SR_OK;
035a1078 674 switch (id) {
1953564a 675 case SR_CONF_LIMIT_FRAMES:
f6a0ac9f 676 devc->limit_frames = g_variant_get_uint64(data);
e0b7d23c 677 break;
1953564a 678 case SR_CONF_TRIGGER_SLOPE:
f6a0ac9f 679 tmp_u64 = g_variant_get_uint64(data);
254dd102
BV		 680 if (tmp_u64 != 0 && tmp_u64 != 1)
681 return SR_ERR;
682 g_free(devc->trigger_slope);
683 devc->trigger_slope = g_strdup(tmp_u64 ? "POS" : "NEG");
684 ret = set_cfg(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope);
e0b7d23c 685 break;
1953564a 686 case SR_CONF_HORIZ_TRIGGERPOS:
254dd102
BV		 687 t_dbl = g_variant_get_double(data);
688 if (t_dbl < 0.0 || t_dbl > 1.0)
689 return SR_ERR;
690 devc->horiz_triggerpos = t_dbl;
691 /* We have the trigger offset as a percentage of the frame, but
692 * need to express this in seconds. */
bafd4890 693 t_dbl = -(devc->horiz_triggerpos - 0.5) * devc->timebase * devc->num_timebases;
889ef4a0
AJ		 694 g_ascii_formatd(buffer, sizeof(buffer), "%.6f", t_dbl);
695 ret = set_cfg(sdi, ":TIM:OFFS %s", buffer);
e0b7d23c 696 break;
1953564a 697 case SR_CONF_TIMEBASE:
f6a0ac9f 698 g_variant_get(data, "(tt)", &p, &q);
bafd4890
ML		 699 for (i = 0; i < devc->num_timebases; i++) {
700 if (devc->timebases[i][0] == p && devc->timebases[i][1] == q) {
254dd102 701 devc->timebase = (float)p / q;
889ef4a0
AJ		 702 g_ascii_formatd(buffer, sizeof(buffer), "%.9f",
703 devc->timebase);
704 ret = set_cfg(sdi, ":TIM:SCAL %s", buffer);
f6a0ac9f
BV		 705 break;
706 }
707 }
bafd4890 708 if (i == devc->num_timebases)
254dd102 709 ret = SR_ERR_ARG;
e0b7d23c 710 break;
1953564a 711 case SR_CONF_TRIGGER_SOURCE:
f6a0ac9f 712 tmp_str = g_variant_get_string(data, NULL);
254dd102
BV		 713 for (i = 0; i < ARRAY_SIZE(trigger_sources); i++) {
714 if (!strcmp(trigger_sources[i], tmp_str)) {
715 g_free(devc->trigger_source);
716 devc->trigger_source = g_strdup(trigger_sources[i]);
717 if (!strcmp(devc->trigger_source, "AC Line"))
718 tmp_str = "ACL";
719 else if (!strcmp(devc->trigger_source, "CH1"))
720 tmp_str = "CHAN1";
721 else if (!strcmp(devc->trigger_source, "CH2"))
722 tmp_str = "CHAN2";
821fbcad
ML		 723 else if (!strcmp(devc->trigger_source, "CH3"))
724 tmp_str = "CHAN3";
725 else if (!strcmp(devc->trigger_source, "CH4"))
726 tmp_str = "CHAN4";
254dd102
BV		 727 else
728 tmp_str = (char *)devc->trigger_source;
729 ret = set_cfg(sdi, ":TRIG:EDGE:SOUR %s", tmp_str);
730 break;
731 }
4e108ace 732 }
254dd102
BV		 733 if (i == ARRAY_SIZE(trigger_sources))
734 ret = SR_ERR_ARG;
e0b7d23c 735 break;
1953564a 736 case SR_CONF_VDIV:
be60a9e4
BV		 737 if (!probe_group) {
738 sr_err("No probe group specified.");
739 return SR_ERR_PROBE_GROUP;
740 }
f6a0ac9f 741 g_variant_get(data, "(tt)", &p, &q);
f48e0249 742 for (i = 0; i < 2; i++) {
78bcc55a
BV		 743 if (probe_group == &devc->analog_groups[i]) {
744 for (j = 0; j < ARRAY_SIZE(vdivs); j++) {
f48e0249
ML		 745 if (vdivs[j][0] != p || vdivs[j][1] != q)
746 continue;
747 devc->vdiv[i] = (float)p / q;
889ef4a0
AJ		 748 g_ascii_formatd(buffer, sizeof(buffer), "%.3f",
749 devc->vdiv[i]);
750 return set_cfg(sdi, ":CHAN%d:SCAL %s", i + 1,
751 buffer);
f48e0249
ML		 752 }
753 return SR_ERR_ARG;
754 }
e0b7d23c 755 }
f48e0249 756 return SR_ERR_NA;
1953564a 757 case SR_CONF_COUPLING:
78bcc55a
BV		 758 if (!probe_group) {
759 sr_err("No probe group specified.");
760 return SR_ERR_PROBE_GROUP;
761 }
f6a0ac9f 762 tmp_str = g_variant_get_string(data, NULL);
f48e0249 763 for (i = 0; i < 2; i++) {
78bcc55a
BV		 764 if (probe_group == &devc->analog_groups[i]) {
765 for (j = 0; j < ARRAY_SIZE(coupling); j++) {
766 if (!strcmp(tmp_str, coupling[j])) {
f48e0249
ML		 767 g_free(devc->coupling[i]);
768 devc->coupling[i] = g_strdup(coupling[j]);
769 return set_cfg(sdi, ":CHAN%d:COUP %s", i + 1,
770 devc->coupling[i]);
771 }
772 }
773 return SR_ERR_ARG;
e0b7d23c
ML		 774 }
775 }
f48e0249 776 return SR_ERR_NA;
babab622
ML		 777 case SR_CONF_DATA_SOURCE:
778 tmp_str = g_variant_get_string(data, NULL);
779 if (!strcmp(tmp_str, "Live"))
780 devc->data_source = DATA_SOURCE_LIVE;
781 else if (!strcmp(tmp_str, "Memory"))
782 devc->data_source = DATA_SOURCE_MEMORY;
470140fc 783 else if (devc->model->series >= RIGOL_DS1000Z
babab622
ML		 784 && !strcmp(tmp_str, "Segmented"))
785 devc->data_source = DATA_SOURCE_SEGMENTED;
786 else
787 return SR_ERR;
788 break;
f4816ac6 789 default:
bd6fbf62 790 ret = SR_ERR_NA;
29d957ce 791 break;
f4816ac6
ML		 792 }
793
794 return ret;
795}
796
8f996b89
ML		 797static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
798 const struct sr_probe_group *probe_group)
a1c743fc 799{
861c447b
BV		 800 GVariant *tuple, *rational[2];
801 GVariantBuilder gvb;
802 unsigned int i;
7cc1a550
ML		 803 struct dev_context *devc = NULL;
804
805 if (sdi)
806 devc = sdi->priv;
8f996b89 807
e43fdd8d 808 if (key == SR_CONF_SCAN_OPTIONS) {
ca55277c
ML		 809 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
810 hwopts, ARRAY_SIZE(hwopts), sizeof(int32_t));
e43fdd8d
BV		 811 return SR_OK;
812 } else if (key == SR_CONF_DEVICE_OPTIONS && probe_group == NULL) {
813 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
814 hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t));
815 return SR_OK;
816 }
817
818 /* Every other option requires a valid device instance. */
819 if (!sdi || !(devc = sdi->priv))
820 return SR_ERR_ARG;
821
be60a9e4
BV		 822 /* If a probe group is specified, it must be a valid one. */
823 if (probe_group) {
824 if (probe_group != &devc->analog_groups[0]
825 && probe_group != &devc->analog_groups[1]) {
826 sr_err("Invalid probe group specified.");
827 return SR_ERR;
828 }
829 }
830
e43fdd8d 831 switch (key) {
9a6517d1 832 case SR_CONF_DEVICE_OPTIONS:
be60a9e4
BV		 833 if (!probe_group) {
834 sr_err("No probe group specified.");
835 return SR_ERR_PROBE_GROUP;
836 }
e43fdd8d 837 if (probe_group == &devc->digital_group) {
f48e0249
ML		 838 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
839 NULL, 0, sizeof(int32_t));
840 return SR_OK;
841 } else {
842 for (i = 0; i < 2; i++) {
843 if (probe_group == &devc->analog_groups[i]) {
844 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
845 analog_hwcaps, ARRAY_SIZE(analog_hwcaps), sizeof(int32_t));
846 return SR_OK;
847 }
848 }
849 return SR_ERR_NA;
850 }
5f77dffc 851 break;
2a7b113d 852 case SR_CONF_COUPLING:
be60a9e4
BV		 853 if (!probe_group) {
854 sr_err("No probe group specified.");
855 return SR_ERR_PROBE_GROUP;
f48e0249 856 }
58f43369
BV		 857 *data = g_variant_new_strv(coupling, ARRAY_SIZE(coupling));
858 break;
e4f2b2ad 859 case SR_CONF_VDIV:
7cc1a550
ML		 860 if (!devc)
861 /* Can't know this until we have the exact model. */
862 return SR_ERR_ARG;
be60a9e4
BV		 863 if (!probe_group) {
864 sr_err("No probe group specified.");
865 return SR_ERR_PROBE_GROUP;
861c447b 866 }
58f43369 867 g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
0709197d 868 for (i = 0; i < NUM_VDIV; i++) {
bafd4890
ML		 869 rational[0] = g_variant_new_uint64(devc->vdivs[i][0]);
870 rational[1] = g_variant_new_uint64(devc->vdivs[i][1]);
58f43369
BV		 871 tuple = g_variant_new_tuple(rational, 2);
872 g_variant_builder_add_value(&gvb, tuple);
873 }
874 *data = g_variant_builder_end(&gvb);
875 break;
41f5bd09 876 case SR_CONF_TIMEBASE:
7cc1a550
ML		 877 if (!devc)
878 /* Can't know this until we have the exact model. */
879 return SR_ERR_ARG;
a31b2ccb
AJ		 880 if (devc->num_timebases <= 0)
881 return SR_ERR_NA;
861c447b 882 g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
bafd4890
ML		 883 for (i = 0; i < devc->num_timebases; i++) {
884 rational[0] = g_variant_new_uint64(devc->timebases[i][0]);
885 rational[1] = g_variant_new_uint64(devc->timebases[i][1]);
861c447b
BV		 886 tuple = g_variant_new_tuple(rational, 2);
887 g_variant_builder_add_value(&gvb, tuple);
888 }
889 *data = g_variant_builder_end(&gvb);
41f5bd09 890 break;
328bafab 891 case SR_CONF_TRIGGER_SOURCE:
7cc1a550
ML		 892 if (!devc)
893 /* Can't know this until we have the exact model. */
894 return SR_ERR_ARG;
f6a0ac9f 895 *data = g_variant_new_strv(trigger_sources,
bafd4890 896 devc->model->has_digital ? ARRAY_SIZE(trigger_sources) : 4);
328bafab 897 break;
babab622
ML		 898 case SR_CONF_DATA_SOURCE:
899 if (!devc)
900 /* Can't know this until we have the exact model. */
901 return SR_ERR_ARG;
902 /* This needs tweaking by series/model! */
903 if (devc->model->series == RIGOL_DS2000)
904 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources));
905 else
906 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 1);
907 break;
a1c743fc 908 default:
bd6fbf62 909 return SR_ERR_NA;
a1c743fc
BV		 910 }
911
912 return SR_OK;
913}
914
254dd102 915static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
f4816ac6 916{
ae1bc1cc 917 struct sr_scpi_dev_inst *scpi;
29d957ce 918 struct dev_context *devc;
254dd102 919 struct sr_probe *probe;
f76c24f6 920 struct sr_datafeed_packet packet;
254dd102 921 GSList *l;
29d957ce 922
e73ffd42
BV		 923 if (sdi->status != SR_ST_ACTIVE)
924 return SR_ERR_DEV_CLOSED;
e0b7d23c 925
ae1bc1cc 926 scpi = sdi->conn;
29d957ce
UH		 927 devc = sdi->priv;
928
51b294cd
ML		 929 devc->num_frames = 0;
930
254dd102
BV		 931 for (l = sdi->probes; l; l = l->next) {
932 probe = l->data;
6bb192bc
ML		 933 sr_dbg("handling probe %s", probe->name);
934 if (probe->type == SR_PROBE_ANALOG) {
935 if (probe->enabled)
936 devc->enabled_analog_probes = g_slist_append(
937 devc->enabled_analog_probes, probe);
938 if (probe->enabled != devc->analog_channels[probe->index]) {
939 /* Enabled channel is currently disabled, or vice versa. */
6396b0a7
ML		 940 if (set_cfg(sdi, ":CHAN%d:DISP %s", probe->index + 1,
941 probe->enabled ? "ON" : "OFF") != SR_OK)
6bb192bc 942 return SR_ERR;
904fd29b 943 devc->analog_channels[probe->index] = probe->enabled;
6bb192bc
ML		 944 }
945 } else if (probe->type == SR_PROBE_LOGIC) {
04e8e01e 946 if (probe->enabled) {
6bb192bc
ML		 947 devc->enabled_digital_probes = g_slist_append(
948 devc->enabled_digital_probes, probe);
04e8e01e
ML		 949 /* Turn on LA module if currently off. */
950 if (!devc->la_enabled) {
951 if (set_cfg(sdi, ":LA:DISP ON") != SR_OK)
952 return SR_ERR;
953 devc->la_enabled = TRUE;
954 }
955 }
6bb192bc
ML		 956 if (probe->enabled != devc->digital_channels[probe->index]) {
957 /* Enabled channel is currently disabled, or vice versa. */
6396b0a7
ML		 958 if (set_cfg(sdi, ":DIG%d:TURN %s", probe->index,
959 probe->enabled ? "ON" : "OFF") != SR_OK)
6bb192bc 960 return SR_ERR;
904fd29b 961 devc->digital_channels[probe->index] = probe->enabled;
6bb192bc 962 }
254dd102
BV		 963 }
964 }
1fed20cb 965
6bb192bc 966 if (!devc->enabled_analog_probes && !devc->enabled_digital_probes)
254dd102 967 return SR_ERR;
e0b7d23c 968
04e8e01e
ML		 969 /* Turn off LA module if on and no digital probes selected. */
970 if (devc->la_enabled && !devc->enabled_digital_probes)
971 if (set_cfg(sdi, ":LA:DISP OFF") != SR_OK)
972 return SR_ERR;
973
1fed20cb 974 if (devc->data_source == DATA_SOURCE_LIVE) {
6396b0a7 975 if (set_cfg(sdi, ":RUN") != SR_OK)
1fed20cb
ML		 976 return SR_ERR;
977 } else if (devc->data_source == DATA_SOURCE_MEMORY) {
978 if (devc->model->series != RIGOL_DS2000) {
979 sr_err("Data source 'Memory' not supported for this device");
980 return SR_ERR;
981 }
982 } else if (devc->data_source == DATA_SOURCE_SEGMENTED) {
983 sr_err("Data source 'Segmented' not yet supported");
984 return SR_ERR;
985 }
986
ae1bc1cc 987 sr_scpi_source_add(scpi, G_IO_IN, 50, rigol_ds_receive, (void *)sdi);
e0b7d23c
ML		 988
989 /* Send header packet to the session bus. */
29a27196 990 std_session_send_df_header(cb_data, LOG_PREFIX);
e0b7d23c 991
821fbcad
ML		 992 if (devc->enabled_analog_probes)
993 devc->channel_entry = devc->enabled_analog_probes;
994 else
995 devc->channel_entry = devc->enabled_digital_probes;
996
5415e602 997 devc->analog_frame_size = analog_frame_size(sdi);
d22250a9 998 devc->digital_frame_size = digital_frame_size(sdi);
5415e602 999
470140fc 1000 if (devc->model->series < RIGOL_DS1000Z) {
bafd4890 1001 /* Fetch the first frame. */
677f85d0
ML		 1002 if (rigol_ds_channel_start(sdi) != SR_OK)
1003 return SR_ERR;
6bb192bc 1004 } else {
bafd4890 1005 if (devc->enabled_analog_probes) {
c2b394d5 1006 if (devc->data_source == DATA_SOURCE_MEMORY) {
babab622
ML		 1007 /* Apparently for the DS2000 the memory
1008 * depth can only be set in Running state -
1009 * this matches the behaviour of the UI. */
6396b0a7 1010 if (set_cfg(sdi, ":RUN") != SR_OK)
babab622 1011 return SR_ERR;
6396b0a7 1012 if (set_cfg(sdi, "ACQ:MDEP %d", devc->analog_frame_size) != SR_OK)
babab622 1013 return SR_ERR;
6396b0a7 1014 if (set_cfg(sdi, ":STOP") != SR_OK)
babab622 1015 return SR_ERR;
0d9f5a12 1016 }
babab622 1017 if (rigol_ds_capture_start(sdi) != SR_OK)
bafd4890
ML		 1018 return SR_ERR;
1019 }
6bb192bc 1020 }
f4816ac6 1021
f76c24f6
ML		 1022 /* Start of first frame. */
1023 packet.type = SR_DF_FRAME_BEGIN;
1024 sr_session_send(cb_data, &packet);
1025
f4816ac6
ML		 1026 return SR_OK;
1027}
1028
254dd102 1029static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
f4816ac6 1030{
29d957ce 1031 struct dev_context *devc;
ae1bc1cc 1032 struct sr_scpi_dev_inst *scpi;
b751cf7a 1033 struct sr_datafeed_packet packet;
29d957ce 1034
f4816ac6
ML		 1035 (void)cb_data;
1036
29d957ce
UH		 1037 devc = sdi->priv;
1038
f4816ac6
ML		 1039 if (sdi->status != SR_ST_ACTIVE) {
1040 sr_err("Device inactive, can't stop acquisition.");
1041 return SR_ERR;
1042 }
1043
b751cf7a
ML		 1044 /* End of last frame. */
1045 packet.type = SR_DF_END;
1046 sr_session_send(sdi, &packet);
1047
6bb192bc
ML		 1048 g_slist_free(devc->enabled_analog_probes);
1049 g_slist_free(devc->enabled_digital_probes);
1050 devc->enabled_analog_probes = NULL;
1051 devc->enabled_digital_probes = NULL;
ae1bc1cc
ML		 1052 scpi = sdi->conn;
1053 sr_scpi_source_remove(scpi);
f4816ac6
ML		 1054
1055 return SR_OK;
1056}
1057
3086efdd
ML		 1058SR_PRIV struct sr_dev_driver rigol_ds_driver_info = {
1059 .name = "rigol-ds",
1060 .longname = "Rigol DS",
f4816ac6 1061 .api_version = 1,
6078d2c9
UH		 1062 .init = init,
1063 .cleanup = cleanup,
1064 .scan = scan,
1065 .dev_list = dev_list,
3b412e3a 1066 .dev_clear = dev_clear,
d62d7ad1 1067 .config_get = config_get,
035a1078 1068 .config_set = config_set,
a1c743fc 1069 .config_list = config_list,
6078d2c9
UH		 1070 .dev_open = dev_open,
1071 .dev_close = dev_close,
254dd102
BV		 1072 .dev_acquisition_start = dev_acquisition_start,
1073 .dev_acquisition_stop = dev_acquisition_stop,
f4816ac6
ML		 1074 .priv = NULL,
1075};
Hardware access and backend lib