[libsigrok.git] / hardware / link-mso19 / protocol.h

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
 * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
 * Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef LIBSIGROK_HARDWARE_LINK_MSO19_PROTOCOL_H
#define LIBSIGROK_HARDWARE_LINK_MSO19_PROTOCOL_H

#include <stdint.h>
#include <string.h>
#include <glib.h>
#include <libudev.h>
#include "libsigrok.h"
#include "libsigrok-internal.h"

#define LOG_PREFIX "link-mso19"

#define USB_VENDOR		"3195"
#define USB_PRODUCT		"f190"

#define NUM_PROBES		(1 + 8)
#define NUM_TRIGGER_STAGES	4
#define TRIGGER_TYPE 		"01"	//the first r/f is used for the whole group
#define SERIALCOMM		"460800/8n1/flow=2"
#define SERIALCONN		"/dev/ttyUSB0"
#define CLOCK_RATE		SR_MHZ(100)
#define MIN_NUM_SAMPLES		4

#define MSO_TRIGGER_UNKNOWN	'!'
#define MSO_TRIGGER_UNKNOWN1	'1'
#define MSO_TRIGGER_UNKNOWN2	'2'
#define MSO_TRIGGER_UNKNOWN3	'3'
#define MSO_TRIGGER_WAIT	'4'
#define MSO_TRIGGER_FIRED	'5'
#define MSO_TRIGGER_DATAREADY	'6'

enum trigger_slopes {
	SLOPE_POSITIVE = 0,
	SLOPE_NEGATIVE,
};

/* Structure for the pattern generator state */
struct mso_patgen {
	/* Pattern generator clock config */
	uint16_t clock;
	/* Buffer start address */
	uint16_t start;
	/* Buffer end address */
	uint16_t end;
	/* Pattern generator config */
	uint8_t config;
	/* Samples buffer */
	uint8_t buffer[1024];
	/* Input/output configuration for the samples buffer (?) */
	uint8_t io[1024];
	/* Number of loops for the pattern generator */
	uint8_t loops;
	/* Bit enable mask for the I/O lines */
	uint8_t mask;
};

/* Data structure for the protocol trigger state */
struct mso_prototrig {
	/* Word match buffer */
	uint8_t word[4];
	/* Masks for the wordmatch buffer */
	uint8_t mask[4];
	/* SPI mode 0, 1, 2, 3. Set to 0 for I2C */
	uint8_t spimode;
};

/* Private, per-device-instance driver context. */
struct dev_context {
	/* info */
	uint8_t hwmodel;
	uint8_t hwrev;
	struct sr_serial_dev_inst *serial;
//      uint8_t num_sample_rates;
	/* calibration */
	double vbit;
	uint16_t dac_offset;
	uint16_t offset_range;
	uint64_t limit_samples;
	uint64_t num_samples;
	/* register cache */
	uint8_t ctlbase1;
	uint8_t ctlbase2;
	/* state */
	uint8_t la_threshold;
	uint64_t cur_rate;
	uint8_t dso_probe_attn;
	int8_t use_trigger;
	uint8_t trigger_chan;
	uint8_t trigger_slope;
	uint8_t trigger_outsrc;
	uint8_t trigger_state;
	uint8_t trigger_holdoff[2];
	uint8_t la_trigger;
	uint8_t la_trigger_mask;
	double dso_trigger_voltage;
	uint16_t dso_trigger_width;
	struct mso_prototrig protocol_trigger;
	void *cb_data;
	uint16_t buffer_n;
	char buffer[4096];
};

SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct,
			     struct dev_context *ctx);
SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial,
			      uint8_t * info);
SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi);
SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val);
SR_PRIV int mso_configure_rate(const struct sr_dev_inst *sdi, uint32_t rate);
SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data);
SR_PRIV int mso_configure_trigger(const struct sr_dev_inst *sdi);
SR_PRIV int mso_configure_threshold_level(const struct sr_dev_inst *sdi);
SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi);
SR_PRIV int mso_arm(const struct sr_dev_inst *sdi);
SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi);
SR_PRIV int mso_dac_out(const struct sr_dev_inst *sdi, uint16_t val);
SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context *devc);
SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi);
SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state);

SR_PRIV int mso_configure_channels(const struct sr_dev_inst *sdi);
SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi);

/* bank agnostic registers */
#define REG_CTL2		15

/* bank 0 registers */
#define REG_BUFFER		1
#define REG_TRIGGER		2
#define REG_CLKRATE1		9
#define REG_CLKRATE2		10
#define REG_DAC1		12
#define REG_DAC2		13
/* possibly bank agnostic: */
#define REG_CTL1		14

/* bank 2 registers (SPI/I2C protocol trigger) */
#define REG_PT_WORD(x)		(x)
#define REG_PT_MASK(x)		(x + 4)
#define REG_PT_SPIMODE		8

/* bits - REG_CTL1 */
#define BIT_CTL1_RESETFSM	(1 << 0)
#define BIT_CTL1_ARM		(1 << 1)
#define BIT_CTL1_ADC_UNKNOWN4	(1 << 4)	/* adc enable? */
#define BIT_CTL1_RESETADC	(1 << 6)
#define BIT_CTL1_LED		(1 << 7)

/* bits - REG_CTL2 */
#define BITS_CTL2_BANK(x)	(x & 0x3)
#define BIT_CTL2_SLOWMODE	(1 << 5)

struct rate_map {
	uint32_t rate;
	uint16_t val;
	uint8_t slowmode;
};

static const struct rate_map rate_map[] = {
	{ SR_MHZ(200), 0x0205, 0 },
	{ SR_MHZ(100), 0x0105, 0 },
	{ SR_MHZ(50),  0x0005, 0 },
	{ SR_MHZ(20),  0x0303, 0 },
	{ SR_MHZ(10),  0x0308, 0 },
	{ SR_MHZ(5),   0x030c, 0 },
	{ SR_MHZ(2),   0x0330, 0 },
	{ SR_MHZ(1),   0x0362, 0 },
	{ SR_KHZ(500), 0x03c6, 0 },
	{ SR_KHZ(200), 0x07f2, 0 },
	{ SR_KHZ(100), 0x0fe6, 0 },
	{ SR_KHZ(50),  0x1fce, 0 },
	{ SR_KHZ(20),  0x4f86, 0 },
	{ SR_KHZ(10),  0x9f0e, 0 },
	{ SR_KHZ(5),   0x03c7, 0x20 },
	{ SR_KHZ(2),   0x07f3, 0x20 },
	{ SR_KHZ(1),   0x0fe7, 0x20 },
	{ SR_HZ(500),  0x1fcf, 0x20 },
	{ SR_HZ(200),  0x4f87, 0x20 },
	{ SR_HZ(100),  0x9f0f, 0x20 },
};

/* FIXME: Determine corresponding voltages */
static const uint16_t la_threshold_map[] = {
	0x8600,
	0x8770,
	0x88ff,
	0x8c70,
	0x8eff,
	0x8fff,
};

#endif
Commit	Line	Data
df92e5cf	1	/*
50985c20	2	* This file is part of the libsigrok project.
df92e5cf	3	*
f48cef78 UH	4	* Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
	5	* Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
	6	* Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com>
df92e5cf	7	*
	8	* This program is free software: you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation, either version 3 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#ifndef LIBSIGROK_HARDWARE_LINK_MSO19_PROTOCOL_H
	23	#define LIBSIGROK_HARDWARE_LINK_MSO19_PROTOCOL_H
	24
df92e5cf	25	#include <stdint.h>
	26	#include <string.h>
	27	#include <glib.h>
753d722f	28	#include <libudev.h>
df92e5cf	29	#include "libsigrok.h"
	30	#include "libsigrok-internal.h"
	31
b95dd761	32	#define LOG_PREFIX "link-mso19"
df92e5cf	33
00b44ccb UH	34	#define USB_VENDOR "3195"
	35	#define USB_PRODUCT "f190"
	36
365f04d6	37	#define NUM_PROBES (1 + 8)
00b44ccb	38	#define NUM_TRIGGER_STAGES 4
c50277a6	39	#define TRIGGER_TYPE "01" //the first r/f is used for the whole group
00b44ccb UH	40	#define SERIALCOMM "460800/8n1/flow=2"
	41	#define SERIALCONN "/dev/ttyUSB0"
	42	#define CLOCK_RATE SR_MHZ(100)
	43	#define MIN_NUM_SAMPLES 4
df92e5cf	44
df92e5cf	45	#define MSO_TRIGGER_UNKNOWN '!'
	46	#define MSO_TRIGGER_UNKNOWN1 '1'
	47	#define MSO_TRIGGER_UNKNOWN2 '2'
	48	#define MSO_TRIGGER_UNKNOWN3 '3'
	49	#define MSO_TRIGGER_WAIT '4'
	50	#define MSO_TRIGGER_FIRED '5'
	51	#define MSO_TRIGGER_DATAREADY '6'
	52
087a9161	53	enum trigger_slopes {
00b44ccb UH	54	SLOPE_POSITIVE = 0,
00b44ccb UH	55	SLOPE_NEGATIVE,
087a9161	56	};
087a9161	57
df92e5cf	58	/* Structure for the pattern generator state */
	59	struct mso_patgen {
	60	/* Pattern generator clock config */
	61	uint16_t clock;
	62	/* Buffer start address */
	63	uint16_t start;
	64	/* Buffer end address */
	65	uint16_t end;
	66	/* Pattern generator config */
	67	uint8_t config;
	68	/* Samples buffer */
	69	uint8_t buffer[1024];
00b44ccb	70	/* Input/output configuration for the samples buffer (?) */
df92e5cf	71	uint8_t io[1024];
	72	/* Number of loops for the pattern generator */
	73	uint8_t loops;
	74	/* Bit enable mask for the I/O lines */
	75	uint8_t mask;
	76	};
	77
	78	/* Data structure for the protocol trigger state */
	79	struct mso_prototrig {
	80	/* Word match buffer */
	81	uint8_t word[4];
	82	/* Masks for the wordmatch buffer */
	83	uint8_t mask[4];
	84	/* SPI mode 0, 1, 2, 3. Set to 0 for I2C */
	85	uint8_t spimode;
	86	};
	87
	88	/* Private, per-device-instance driver context. */
	89	struct dev_context {
	90	/* info */
	91	uint8_t hwmodel;
	92	uint8_t hwrev;
	93	struct sr_serial_dev_inst *serial;
00b44ccb	94	// uint8_t num_sample_rates;
df92e5cf	95	/* calibration */
	96	double vbit;
	97	uint16_t dac_offset;
	98	uint16_t offset_range;
00b44ccb UH	99	uint64_t limit_samples;
00b44ccb UH	100	uint64_t num_samples;
df92e5cf	101	/* register cache */
	102	uint8_t ctlbase1;
	103	uint8_t ctlbase2;
	104	/* state */
	105	uint8_t la_threshold;
	106	uint64_t cur_rate;
	107	uint8_t dso_probe_attn;
00b44ccb	108	int8_t use_trigger;
df92e5cf	109	uint8_t trigger_chan;
	110	uint8_t trigger_slope;
	111	uint8_t trigger_outsrc;
	112	uint8_t trigger_state;
087a9161	113	uint8_t trigger_holdoff[2];
df92e5cf	114	uint8_t la_trigger;
	115	uint8_t la_trigger_mask;
	116	double dso_trigger_voltage;
	117	uint16_t dso_trigger_width;
	118	struct mso_prototrig protocol_trigger;
3e9b7f9c	119	void *cb_data;
df92e5cf	120	uint16_t buffer_n;
	121	char buffer[4096];
	122	};
	123
	124	SR_PRIV int mso_parse_serial(const char iSerial, const char iProduct,
00b44ccb UH	125	struct dev_context *ctx);
	126	SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial,
	127	uint8_t * info);
df92e5cf	128	SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi);
df92e5cf	129	SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val);
753d722f	130	SR_PRIV int mso_configure_rate(const struct sr_dev_inst *sdi, uint32_t rate);
df92e5cf	131	SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data);
753d722f UH	132	SR_PRIV int mso_configure_trigger(const struct sr_dev_inst *sdi);
753d722f UH	133	SR_PRIV int mso_configure_threshold_level(const struct sr_dev_inst *sdi);
4b719338	134	SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi);
753d722f	135	SR_PRIV int mso_arm(const struct sr_dev_inst *sdi);
4b719338	136	SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi);
753d722f	137	SR_PRIV int mso_dac_out(const struct sr_dev_inst *sdi, uint16_t val);
4b719338	138	SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context *devc);
4db2aaff	139	SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi);
4db2aaff	140	SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state);
4b719338	141
ba7dd8bb	142	SR_PRIV int mso_configure_channels(const struct sr_dev_inst *sdi);
df92e5cf	143	SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi);
df92e5cf	144
df92e5cf	145	/* bank agnostic registers */
	146	#define REG_CTL2 15
	147
	148	/* bank 0 registers */
	149	#define REG_BUFFER 1
	150	#define REG_TRIGGER 2
	151	#define REG_CLKRATE1 9
	152	#define REG_CLKRATE2 10
	153	#define REG_DAC1 12
	154	#define REG_DAC2 13
	155	/* possibly bank agnostic: */
	156	#define REG_CTL1 14
	157
	158	/* bank 2 registers (SPI/I2C protocol trigger) */
00b44ccb UH	159	#define REG_PT_WORD(x) (x)
	160	#define REG_PT_MASK(x) (x + 4)
	161	#define REG_PT_SPIMODE 8
df92e5cf	162
df92e5cf	163	/* bits - REG_CTL1 */
00b44ccb UH	164	#define BIT_CTL1_RESETFSM (1 << 0)
	165	#define BIT_CTL1_ARM (1 << 1)
	166	#define BIT_CTL1_ADC_UNKNOWN4 (1 << 4) /* adc enable? */
	167	#define BIT_CTL1_RESETADC (1 << 6)
	168	#define BIT_CTL1_LED (1 << 7)
df92e5cf	169
df92e5cf	170	/* bits - REG_CTL2 */
00b44ccb UH	171	#define BITS_CTL2_BANK(x) (x & 0x3)
00b44ccb UH	172	#define BIT_CTL2_SLOWMODE (1 << 5)
df92e5cf	173
	174	struct rate_map {
	175	uint32_t rate;
	176	uint16_t val;
	177	uint8_t slowmode;
	178	};
	179
753d722f	180	static const struct rate_map rate_map[] = {
00b44ccb UH	181	{ SR_MHZ(200), 0x0205, 0 },
	182	{ SR_MHZ(100), 0x0105, 0 },
	183	{ SR_MHZ(50), 0x0005, 0 },
	184	{ SR_MHZ(20), 0x0303, 0 },
	185	{ SR_MHZ(10), 0x0308, 0 },
	186	{ SR_MHZ(5), 0x030c, 0 },
	187	{ SR_MHZ(2), 0x0330, 0 },
	188	{ SR_MHZ(1), 0x0362, 0 },
	189	{ SR_KHZ(500), 0x03c6, 0 },
	190	{ SR_KHZ(200), 0x07f2, 0 },
	191	{ SR_KHZ(100), 0x0fe6, 0 },
	192	{ SR_KHZ(50), 0x1fce, 0 },
	193	{ SR_KHZ(20), 0x4f86, 0 },
	194	{ SR_KHZ(10), 0x9f0e, 0 },
	195	{ SR_KHZ(5), 0x03c7, 0x20 },
	196	{ SR_KHZ(2), 0x07f3, 0x20 },
	197	{ SR_KHZ(1), 0x0fe7, 0x20 },
	198	{ SR_HZ(500), 0x1fcf, 0x20 },
	199	{ SR_HZ(200), 0x4f87, 0x20 },
	200	{ SR_HZ(100), 0x9f0f, 0x20 },
df92e5cf	201	};
	202
	203	/* FIXME: Determine corresponding voltages */
753d722f	204	static const uint16_t la_threshold_map[] = {
df92e5cf	205	0x8600,
	206	0x8770,
	207	0x88ff,
	208	0x8c70,
	209	0x8eff,
	210	0x8fff,
	211	};
	212
df92e5cf	213	#endif