[libsigrok.git] / hardware / link-mso19 / protocol.c

/*
 * This file is part of the sigrok project.
 *
 * Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "protocol.h"
#include <arpa/inet.h>

extern SR_PRIV struct sr_dev_driver link_mso19_driver_info;
static struct sr_dev_driver *di = &link_mso19_driver_info;

SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial,
    uint16_t payload[], int n)
{
	int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
	char *p, *buf;

	ret = SR_ERR;

	if (serial->fd < 0)
		goto ret;

	if (!(buf = g_try_malloc(s))) {
		sr_err("Failed to malloc message buffer.");
		ret = SR_ERR_MALLOC;
		goto ret;
	}

	p = buf;
	memcpy(p, mso_head, sizeof(mso_head));
	p += sizeof(mso_head);

	for (i = 0; i < n; i++) {
		*(uint16_t *) p = htons(payload[i]);
		p += 2;
	}
	memcpy(p, mso_foot, sizeof(mso_foot));

	w = 0;
	while (w < s) {
		ret = serial_write(serial, buf + w, s - w);
		if (ret < 0) {
			ret = SR_ERR;
			goto free;
		}
		w += ret;
	}
	ret = SR_OK;
free:
	g_free(buf);
ret:
	return ret;
}


SR_PRIV int mso_configure_trigger(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t threshold_value = mso_calc_raw_from_mv(devc);


  threshold_value = 0x153C;
  uint8_t trigger_config = 0; 

  if (devc->trigger_slope)
    trigger_config |= 0x04; //Trigger on falling edge

	switch (devc->trigger_outsrc) {
	case 1:
		trigger_config |= 0x00; //Trigger pulse output
		break;
	case 2:
		trigger_config |= 0x08; //PWM DAC from the pattern generator buffer
		break;
	case 3:
		trigger_config |= 0x18; //White noise
		break;
	}

	switch (devc->trigger_chan) {
    case 0:
      trigger_config |= 0x00; //DSO level trigger //b00000000
      break;
    case 1:
      trigger_config |= 0x20; //DSO level trigger & width < trigger_width
      break;
    case 2:
      trigger_config |= 0x40; //DSO level trigger & width >= trigger_width 
      break;
    case 3:
      trigger_config |= 0x60; //LA combination trigger
      break;
  }

  //Last bit of trigger config reg 4 needs to be 1 for trigger enable,
  //otherwise the trigger is not enabled
  if (devc->use_trigger)
    trigger_config |= 0x80;

	uint16_t ops[18];
	ops[0] = mso_trans(3, threshold_value & 0xff);
  //The trigger_config also holds the 2 MSB bits from the threshold value
	ops[1] = mso_trans(4, trigger_config | (threshold_value >> 8) & 0x03);
	ops[2] = mso_trans(5, devc->la_trigger);
	ops[3] = mso_trans(6, devc->la_trigger_mask);
	ops[4] = mso_trans(7, devc->trigger_holdoff[0]);
	ops[5] = mso_trans(8, devc->trigger_holdoff[1]);

	ops[6] = mso_trans(11,
			devc->dso_trigger_width / SR_HZ_TO_NS(devc->cur_rate));

	/* Select the SPI/I2C trigger config bank */
	ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2)));
	/* Configure the SPI/I2C protocol trigger */
	ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
	ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
	ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
	ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
	ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
	ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
	ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
	ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
	ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
	/* Select the default config bank */
	ops[17] = mso_trans(REG_CTL2, devc->ctlbase2);

	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_configure_threshold_level(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;

	return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
}

SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
{
	uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
	struct dev_context *devc = sdi->priv;

	sr_dbg("Requesting buffer dump.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_arm(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETFSM),
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_ARM),
		mso_trans(REG_CTL1, devc->ctlbase1),
	};

	sr_dbg("Requesting trigger arm.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_CTL1, devc->ctlbase1 | 8),
		mso_trans(REG_CTL1, devc->ctlbase1),
	};

	sr_dbg("Requesting forced capture.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_dac_out(struct sr_dev_inst *sdi, uint16_t val)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_DAC1, (val >> 8) & 0xff),
		mso_trans(REG_DAC2, val & 0xff),
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETADC),
	};

	sr_dbg("Setting dac word to 0x%x.", val);
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context *devc)
{
	return (uint16_t) (0x200 -
			((devc->dso_trigger_voltage / devc->dso_probe_attn) /
			 devc->vbit));
}


SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct,
    struct dev_context *devc)
{
	unsigned int u1, u2, u3, u4, u5, u6;

  iProduct = iProduct;
  /* FIXME: This code is in the original app, but I think its
   * used only for the GUI */
  /*	if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03"))
      devc->num_sample_rates = 0x16;
      else
      devc->num_sample_rates = 0x10; */
  

	/* parse iSerial */
	if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
				&u1, &u2, &u3, &u4, &u5, &u6) != 6)
		return SR_ERR;
	devc->hwmodel = u4;
	devc->hwrev = u5;
	devc->vbit = u1 / 10000;
	if (devc->vbit == 0)
		devc->vbit = 4.19195;
	devc->dac_offset = u2;
	if (devc->dac_offset == 0)
		devc->dac_offset = 0x1ff;
	devc->offset_range = u3;
	if (devc->offset_range == 0)
		devc->offset_range = 0x17d;

	/*
	 * FIXME: There is more code on the original software to handle
	 * bigger iSerial strings, but as I can't test on my device
	 * I will not implement it yet
	 */

	return SR_OK;
}

SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[2];

	ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 | BIT_CTL1_RESETADC));
	ops[1] = mso_trans(REG_CTL1, devc->ctlbase1);
	devc->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4;

	sr_dbg("Requesting ADC reset.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[1];

	devc->ctlbase1 |= BIT_CTL1_RESETFSM;
	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);

	sr_dbg("Requesting ADC reset.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[1];

	devc->ctlbase1 &= ~BIT_CTL1_LED;
	if (state)
		devc->ctlbase1 |= BIT_CTL1_LED;
	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);

	sr_dbg("Requesting LED toggle.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi)
{
	struct sr_datafeed_packet packet;
	struct dev_context *devc;

	devc = sdi->priv;
	sr_source_remove(devc->serial->fd);

	/* Terminate session */
	packet.type = SR_DF_END;
	sr_session_send(sdi, &packet);
}

SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val)
{
	uint16_t ops[] = {
		mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
		mso_trans(REG_CLKRATE2, val & 0xff),
	};

	sr_dbg("Setting clkrate word to 0x%x.", val);
	return mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_configure_rate(struct sr_dev_inst *sdi, uint32_t rate)
{
	struct dev_context *devc = sdi->priv;
	unsigned int i;
	int ret = SR_ERR;

	for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
		if (rate_map[i].rate == rate) {
			devc->ctlbase2 = rate_map[i].slowmode;
			ret = mso_clkrate_out(devc->serial, rate_map[i].val);
			if (ret == SR_OK)
				devc->cur_rate = rate;
			return ret;
		}
	}

  if (ret != SR_OK)
		sr_err("Unsupported rate.");

	return ret;
}


SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t *info)
{
	uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
	int ret;

	sr_dbg("Requesting trigger state.");
	ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
	if (info == NULL || ret != SR_OK)
		return ret;


  uint8_t buf = 0;
	if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */
		ret = SR_ERR;
	*info = buf;

	sr_dbg("Trigger state is: 0x%x.", *info);
	return ret;
}

SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
{

	struct sr_datafeed_packet packet;
	struct sr_datafeed_logic logic;
	struct sr_dev_inst *sdi;
	GSList *l;
	int i;

	struct drv_context *drvc = di->priv;

	/* Find this device's devc struct by its fd. */
	struct dev_context *devc = NULL;
	for (l = drvc->instances; l; l = l->next) {
		sdi = l->data;
		devc = sdi->priv;
		if (devc->serial->fd == fd)
			break;
		devc = NULL;
	}
	if (!devc)
		/* Shouldn't happen. */
		return TRUE;

	(void)revents;

	uint8_t in[1024];
	size_t s = serial_read(devc->serial, in, sizeof(in));

	if (s <= 0)
		return FALSE;
  
  /* Check if we triggered, then send a command that we are ready
   * to read the data */
  if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
    devc->trigger_state = in[0];
    if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
      mso_read_buffer(sdi);
      devc->buffer_n = 0;
    } else {
      mso_check_trigger(devc->serial, NULL);
    }
    return TRUE;
  }

	/* the hardware always dumps 1024 samples, 24bits each */
	if (devc->buffer_n < 3072) {
		memcpy(devc->buffer + devc->buffer_n, in, s);
		devc->buffer_n += s;
	}
	if (devc->buffer_n < 3072)
		return TRUE;

	/* do the conversion */
	uint8_t logic_out[1024];
	double analog_out[1024];
	for (i = 0; i < 1024; i++) {
		/* FIXME: Need to do conversion to mV */
		analog_out[i] = (devc->buffer[i * 3] & 0x3f) |
			((devc->buffer[i * 3 + 1] & 0xf) << 6);
		logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) |
			((devc->buffer[i * 3 + 2] & 0x3f) << 2);
	}

	packet.type = SR_DF_LOGIC;
	packet.payload = &logic;
	logic.length = 1024;
	logic.unitsize = 1;
	logic.data = logic_out;
	sr_session_send(cb_data, &packet);

  devc->num_samples += 1024;

	// Dont bother fixing this yet, keep it "old style"
	/*
	packet.type = SR_DF_ANALOG;
	packet.length = 1024;
	packet.unitsize = sizeof(double);
	packet.payload = analog_out;
	sr_session_send(ctx->session_dev_id, &packet);
	*/

  if (devc->limit_samples && devc->num_samples >= devc->limit_samples) { 
    sr_info("Requested number of samples reached."); 
    sdi->driver->dev_acquisition_stop(sdi, cb_data); 
  } 

  return TRUE;
}

SR_PRIV int mso_configure_probes(const struct sr_dev_inst *sdi)
{
	struct dev_context *devc;
	struct sr_probe *probe;
	GSList *l;
	int probe_bit, stage, i;
	char *tc;

  
	devc = sdi->priv;

  devc->la_trigger_mask = 0xFF; //the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored).
  devc->la_trigger = 0x00;  //The value of the LA byte that generates a trigger event (in that mode).
  devc->dso_trigger_voltage = 3;
  devc->dso_probe_attn = 1;
  devc->trigger_outsrc = 0;
  devc->trigger_chan = 3; //LA combination trigger
  devc->use_trigger = FALSE;

	for (l = sdi->probes; l; l = l->next) {
		probe = (struct sr_probe *)l->data;
		if (probe->enabled == FALSE)
			continue;

		int probe_bit = 1 << (probe->index);
		if (!(probe->trigger))
			continue;

    devc->use_trigger = TRUE;
		//Configure trigger mask and value.
		for (tc = probe->trigger; *tc; tc++) {
			devc->la_trigger_mask &= ~probe_bit;
      if (*tc == '1')
        devc->la_trigger |= probe_bit;
    }
  }

	return SR_OK;
}
Commit	Line	Data
df92e5cf	1	/*
	2	* This file is part of the sigrok project.
	3	*
	4	* Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation, either version 3 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "protocol.h"
4db2aaff	21	#include <arpa/inet.h>
df92e5cf	22
	23	extern SR_PRIV struct sr_dev_driver link_mso19_driver_info;
	24	static struct sr_dev_driver *di = &link_mso19_driver_info;
	25
4db2aaff	26	SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial,
	27	uint16_t payload[], int n)
	28	{
	29	int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
	30	char p, buf;
	31
	32	ret = SR_ERR;
	33
	34	if (serial->fd < 0)
	35	goto ret;
	36
	37	if (!(buf = g_try_malloc(s))) {
	38	sr_err("Failed to malloc message buffer.");
	39	ret = SR_ERR_MALLOC;
	40	goto ret;
	41	}
	42
	43	p = buf;
	44	memcpy(p, mso_head, sizeof(mso_head));
	45	p += sizeof(mso_head);
	46
	47	for (i = 0; i < n; i++) {
	48	(uint16_t ) p = htons(payload[i]);
	49	p += 2;
	50	}
	51	memcpy(p, mso_foot, sizeof(mso_foot));
	52
	53	w = 0;
	54	while (w < s) {
	55	ret = serial_write(serial, buf + w, s - w);
	56	if (ret < 0) {
	57	ret = SR_ERR;
	58	goto free;
	59	}
	60	w += ret;
	61	}
	62	ret = SR_OK;
	63	free:
	64	g_free(buf);
	65	ret:
	66	return ret;
	67	}
	68
	69
4b719338	70	SR_PRIV int mso_configure_trigger(struct sr_dev_inst *sdi)
	71	{
	72	struct dev_context *devc = sdi->priv;
087a9161	73	uint16_t threshold_value = mso_calc_raw_from_mv(devc);
4b719338	74
4b719338	75
087a9161	76	threshold_value = 0x153C;
	77	uint8_t trigger_config = 0;
	78
	79	if (devc->trigger_slope)
	80	trigger_config \|= 0x04; //Trigger on falling edge
4b719338	81
	82	switch (devc->trigger_outsrc) {
	83	case 1:
087a9161	84	trigger_config \|= 0x00; //Trigger pulse output
4b719338	85	break;
4b719338	86	case 2:
087a9161	87	trigger_config \|= 0x08; //PWM DAC from the pattern generator buffer
4b719338	88	break;
4b719338	89	case 3:
087a9161	90	trigger_config \|= 0x18; //White noise
4b719338	91	break;
4b719338	92	}
4b719338	93
087a9161	94	switch (devc->trigger_chan) {
	95	case 0:
	96	trigger_config \|= 0x00; //DSO level trigger //b00000000
	97	break;
	98	case 1:
	99	trigger_config \|= 0x20; //DSO level trigger & width < trigger_width
	100	break;
	101	case 2:
	102	trigger_config \|= 0x40; //DSO level trigger & width >= trigger_width
	103	break;
	104	case 3:
	105	trigger_config \|= 0x60; //LA combination trigger
	106	break;
	107	}
	108
	109	//Last bit of trigger config reg 4 needs to be 1 for trigger enable,
	110	//otherwise the trigger is not enabled
	111	if (devc->use_trigger)
	112	trigger_config \|= 0x80;
	113
	114	uint16_t ops[18];
	115	ops[0] = mso_trans(3, threshold_value & 0xff);
	116	//The trigger_config also holds the 2 MSB bits from the threshold value
	117	ops[1] = mso_trans(4, trigger_config \| (threshold_value >> 8) & 0x03);
	118	ops[2] = mso_trans(5, devc->la_trigger);
	119	ops[3] = mso_trans(6, devc->la_trigger_mask);
	120	ops[4] = mso_trans(7, devc->trigger_holdoff[0]);
	121	ops[5] = mso_trans(8, devc->trigger_holdoff[1]);
	122
	123	ops[6] = mso_trans(11,
4b719338	124	devc->dso_trigger_width / SR_HZ_TO_NS(devc->cur_rate));
	125
	126	/* Select the SPI/I2C trigger config bank */
087a9161	127	ops[7] = mso_trans(REG_CTL2, (devc->ctlbase2 \| BITS_CTL2_BANK(2)));
4b719338	128	/* Configure the SPI/I2C protocol trigger */
087a9161	129	ops[8] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
	130	ops[9] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
	131	ops[10] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
	132	ops[11] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
	133	ops[12] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
	134	ops[13] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
	135	ops[14] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
	136	ops[15] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
	137	ops[16] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
4b719338	138	/* Select the default config bank */
087a9161	139	ops[17] = mso_trans(REG_CTL2, devc->ctlbase2);
4b719338	140
4db2aaff	141	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
4b719338	142	}
	143
	144	SR_PRIV int mso_configure_threshold_level(struct sr_dev_inst *sdi)
	145	{
	146	struct dev_context *devc = sdi->priv;
	147
	148	return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
	149	}
	150
	151	SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
	152	{
	153	uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
	154	struct dev_context *devc = sdi->priv;
	155
	156	sr_dbg("Requesting buffer dump.");
	157	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	158	}
	159
	160	SR_PRIV int mso_arm(struct sr_dev_inst *sdi)
	161	{
	162	struct dev_context *devc = sdi->priv;
	163	uint16_t ops[] = {
	164	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_RESETFSM),
	165	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_ARM),
	166	mso_trans(REG_CTL1, devc->ctlbase1),
	167	};
	168
	169	sr_dbg("Requesting trigger arm.");
	170	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	171	}
	172
	173	SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
	174	{
	175	struct dev_context *devc = sdi->priv;
	176	uint16_t ops[] = {
	177	mso_trans(REG_CTL1, devc->ctlbase1 \| 8),
	178	mso_trans(REG_CTL1, devc->ctlbase1),
	179	};
	180
	181	sr_dbg("Requesting forced capture.");
	182	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	183	}
	184
	185	SR_PRIV int mso_dac_out(struct sr_dev_inst *sdi, uint16_t val)
	186	{
	187	struct dev_context *devc = sdi->priv;
	188	uint16_t ops[] = {
	189	mso_trans(REG_DAC1, (val >> 8) & 0xff),
	190	mso_trans(REG_DAC2, val & 0xff),
	191	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_RESETADC),
	192	};
	193
	194	sr_dbg("Setting dac word to 0x%x.", val);
	195	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	196	}
	197
	198	SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context *devc)
	199	{
	200	return (uint16_t) (0x200 -
	201	((devc->dso_trigger_voltage / devc->dso_probe_attn) /
	202	devc->vbit));
	203	}
	204
	205
df92e5cf	206	SR_PRIV int mso_parse_serial(const char iSerial, const char iProduct,
	207	struct dev_context *devc)
	208	{
	209	unsigned int u1, u2, u3, u4, u5, u6;
	210
	211	iProduct = iProduct;
	212	/* FIXME: This code is in the original app, but I think its
	213	* used only for the GUI */
	214	/* if (strstr(iProduct, "REV_02") \|\| strstr(iProduct, "REV_03"))
	215	devc->num_sample_rates = 0x16;
	216	else
	217	devc->num_sample_rates = 0x10; */
	218
	219
	220	/* parse iSerial */
	221	if (iSerial[0] != '4' \|\| sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
	222	&u1, &u2, &u3, &u4, &u5, &u6) != 6)
	223	return SR_ERR;
	224	devc->hwmodel = u4;
	225	devc->hwrev = u5;
df92e5cf	226	devc->vbit = u1 / 10000;
	227	if (devc->vbit == 0)
	228	devc->vbit = 4.19195;
	229	devc->dac_offset = u2;
	230	if (devc->dac_offset == 0)
	231	devc->dac_offset = 0x1ff;
	232	devc->offset_range = u3;
	233	if (devc->offset_range == 0)
	234	devc->offset_range = 0x17d;
	235
	236	/*
	237	* FIXME: There is more code on the original software to handle
	238	* bigger iSerial strings, but as I can't test on my device
	239	* I will not implement it yet
	240	*/
	241
	242	return SR_OK;
	243	}
	244
4db2aaff	245	SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi)
df92e5cf	246	{
4db2aaff	247	struct dev_context *devc = sdi->priv;
4db2aaff	248	uint16_t ops[2];
df92e5cf	249
4db2aaff	250	ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 \| BIT_CTL1_RESETADC));
	251	ops[1] = mso_trans(REG_CTL1, devc->ctlbase1);
	252	devc->ctlbase1 \|= BIT_CTL1_ADC_UNKNOWN4;
df92e5cf	253
4db2aaff	254	sr_dbg("Requesting ADC reset.");
	255	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	256	}
df92e5cf	257
4db2aaff	258	SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi)
	259	{
	260	struct dev_context *devc = sdi->priv;
	261	uint16_t ops[1];
df92e5cf	262
4db2aaff	263	devc->ctlbase1 \|= BIT_CTL1_RESETFSM;
4db2aaff	264	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);
df92e5cf	265
4db2aaff	266	sr_dbg("Requesting ADC reset.");
4db2aaff	267	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
df92e5cf	268	}
df92e5cf	269
4db2aaff	270	SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state)
df92e5cf	271	{
df92e5cf	272	struct dev_context *devc = sdi->priv;
4db2aaff	273	uint16_t ops[1];
df92e5cf	274
4db2aaff	275	devc->ctlbase1 &= ~BIT_CTL1_LED;
	276	if (state)
	277	devc->ctlbase1 \|= BIT_CTL1_LED;
	278	ops[0] = mso_trans(REG_CTL1, devc->ctlbase1);
df92e5cf	279
4db2aaff	280	sr_dbg("Requesting LED toggle.");
df92e5cf	281	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
	282	}
	283
	284	SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi)
	285	{
	286	struct sr_datafeed_packet packet;
	287	struct dev_context *devc;
	288
	289	devc = sdi->priv;
	290	sr_source_remove(devc->serial->fd);
	291
	292	/* Terminate session */
	293	packet.type = SR_DF_END;
	294	sr_session_send(sdi, &packet);
	295	}
	296
	297	SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val)
	298	{
	299	uint16_t ops[] = {
	300	mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
	301	mso_trans(REG_CLKRATE2, val & 0xff),
	302	};
	303
	304	sr_dbg("Setting clkrate word to 0x%x.", val);
	305	return mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
	306	}
	307
	308	SR_PRIV int mso_configure_rate(struct sr_dev_inst *sdi, uint32_t rate)
	309	{
	310	struct dev_context *devc = sdi->priv;
	311	unsigned int i;
	312	int ret = SR_ERR;
	313
	314	for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
	315	if (rate_map[i].rate == rate) {
	316	devc->ctlbase2 = rate_map[i].slowmode;
4b719338	317	ret = mso_clkrate_out(devc->serial, rate_map[i].val);
df92e5cf	318	if (ret == SR_OK)
	319	devc->cur_rate = rate;
	320	return ret;
	321	}
	322	}
4db2aaff	323
	324	if (ret != SR_OK)
	325	sr_err("Unsupported rate.");
	326
df92e5cf	327	return ret;
	328	}
	329
	330
	331
	332
	333
	334	SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst serial, uint8_t info)
	335	{
	336	uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
	337	int ret;
	338
	339	sr_dbg("Requesting trigger state.");
	340	ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
	341	if (info == NULL \|\| ret != SR_OK)
	342	return ret;
	343
	344
	345	uint8_t buf = 0;
	346	if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */
	347	ret = SR_ERR;
	348	*info = buf;
	349
	350	sr_dbg("Trigger state is: 0x%x.", *info);
	351	return ret;
	352	}
	353
	354	SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
	355	{
	356
	357	struct sr_datafeed_packet packet;
	358	struct sr_datafeed_logic logic;
	359	struct sr_dev_inst *sdi;
df92e5cf	360	GSList *l;
4db2aaff	361	int i;
df92e5cf	362
4db2aaff	363	struct drv_context *drvc = di->priv;
df92e5cf	364
df92e5cf	365	/* Find this device's devc struct by its fd. */
4db2aaff	366	struct dev_context *devc = NULL;
df92e5cf	367	for (l = drvc->instances; l; l = l->next) {
	368	sdi = l->data;
	369	devc = sdi->priv;
	370	if (devc->serial->fd == fd)
	371	break;
	372	devc = NULL;
	373	}
	374	if (!devc)
	375	/* Shouldn't happen. */
	376	return TRUE;
	377
	378	(void)revents;
	379
	380	uint8_t in[1024];
	381	size_t s = serial_read(devc->serial, in, sizeof(in));
5a24e89c	382
df92e5cf	383	if (s <= 0)
	384	return FALSE;
	385
5a24e89c	386	/* Check if we triggered, then send a command that we are ready
5a24e89c	387	* to read the data */
df92e5cf	388	if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
	389	devc->trigger_state = in[0];
	390	if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
	391	mso_read_buffer(sdi);
	392	devc->buffer_n = 0;
	393	} else {
	394	mso_check_trigger(devc->serial, NULL);
	395	}
5a24e89c	396	return TRUE;
df92e5cf	397	}
	398
	399	/* the hardware always dumps 1024 samples, 24bits each */
	400	if (devc->buffer_n < 3072) {
	401	memcpy(devc->buffer + devc->buffer_n, in, s);
	402	devc->buffer_n += s;
	403	}
	404	if (devc->buffer_n < 3072)
5a24e89c	405	return TRUE;
df92e5cf	406
	407	/* do the conversion */
	408	uint8_t logic_out[1024];
	409	double analog_out[1024];
	410	for (i = 0; i < 1024; i++) {
	411	/* FIXME: Need to do conversion to mV */
	412	analog_out[i] = (devc->buffer[i * 3] & 0x3f) \|
	413	((devc->buffer[i * 3 + 1] & 0xf) << 6);
	414	logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) \|
	415	((devc->buffer[i * 3 + 2] & 0x3f) << 2);
	416	}
	417
	418	packet.type = SR_DF_LOGIC;
	419	packet.payload = &logic;
	420	logic.length = 1024;
	421	logic.unitsize = 1;
	422	logic.data = logic_out;
	423	sr_session_send(cb_data, &packet);
	424
eb913174	425	devc->num_samples += 1024;
eb913174	426
df92e5cf	427	// Dont bother fixing this yet, keep it "old style"
	428	/*
	429	packet.type = SR_DF_ANALOG;
	430	packet.length = 1024;
	431	packet.unitsize = sizeof(double);
	432	packet.payload = analog_out;
	433	sr_session_send(ctx->session_dev_id, &packet);
	434	*/
	435
eb913174	436	if (devc->limit_samples && devc->num_samples >= devc->limit_samples) {
	437	sr_info("Requested number of samples reached.");
	438	sdi->driver->dev_acquisition_stop(sdi, cb_data);
	439	}
5a24e89c	440
4db2aaff	441	return TRUE;
df92e5cf	442	}
5a24e89c	443
	444	SR_PRIV int mso_configure_probes(const struct sr_dev_inst *sdi)
	445	{
5a24e89c	446	struct dev_context *devc;
	447	struct sr_probe *probe;
	448	GSList *l;
	449	int probe_bit, stage, i;
	450	char *tc;
	451
087a9161	452
5a24e89c	453	devc = sdi->priv;
5a24e89c	454
087a9161	455	devc->la_trigger_mask = 0xFF; //the mask for the LA_TRIGGER (bits set to 0 matter, those set to 1 are ignored).
	456	devc->la_trigger = 0x00; //The value of the LA byte that generates a trigger event (in that mode).
	457	devc->dso_trigger_voltage = 3;
	458	devc->dso_probe_attn = 1;
	459	devc->trigger_outsrc = 0;
	460	devc->trigger_chan = 3; //LA combination trigger
	461	devc->use_trigger = FALSE;
	462
5a24e89c	463	for (l = sdi->probes; l; l = l->next) {
	464	probe = (struct sr_probe *)l->data;
	465	if (probe->enabled == FALSE)
	466	continue;
	467
087a9161	468	int probe_bit = 1 << (probe->index);
5a24e89c	469	if (!(probe->trigger))
	470	continue;
	471
087a9161	472	devc->use_trigger = TRUE;
5a24e89c	473	//Configure trigger mask and value.
5a24e89c	474	for (tc = probe->trigger; *tc; tc++) {
087a9161	475	devc->la_trigger_mask &= ~probe_bit;
	476	if (*tc == '1')
	477	devc->la_trigger \|= probe_bit;
	478	}
	479	}
5a24e89c	480
5a24e89c	481	return SR_OK;
5a24e89c	482	}
	483
	484
	485