[libsigrok.git] / hardware / link-mso19 / protocol.c

/*
 * This file is part of the sigrok project.
 *
 * Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "protocol.h"

extern SR_PRIV struct sr_dev_driver link_mso19_driver_info;
static struct sr_dev_driver *di = &link_mso19_driver_info;

SR_PRIV int mso_configure_trigger(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[16];
	uint16_t dso_trigger = mso_calc_raw_from_mv(devc);

	dso_trigger &= 0x3ff;
	if ((!devc->trigger_slope && devc->trigger_chan == 1) ||
			(devc->trigger_slope &&
			 (devc->trigger_chan == 0 ||
			  devc->trigger_chan == 2 ||
			  devc->trigger_chan == 3)))
		dso_trigger |= 0x400;

	switch (devc->trigger_chan) {
	case 1:
		dso_trigger |= 0xe000;
	case 2:
		dso_trigger |= 0x4000;
		break;
	case 3:
		dso_trigger |= 0x2000;
		break;
	case 4:
		dso_trigger |= 0xa000;
		break;
	case 5:
		dso_trigger |= 0x8000;
		break;
	default:
	case 0:
		break;
	}

	switch (devc->trigger_outsrc) {
	case 1:
		dso_trigger |= 0x800;
		break;
	case 2:
		dso_trigger |= 0x1000;
		break;
	case 3:
		dso_trigger |= 0x1800;
		break;

	}

	ops[0] = mso_trans(5, devc->la_trigger);
	ops[1] = mso_trans(6, devc->la_trigger_mask);
	ops[2] = mso_trans(3, dso_trigger & 0xff);
	ops[3] = mso_trans(4, (dso_trigger >> 8) & 0xff);
	ops[4] = mso_trans(11,
			devc->dso_trigger_width / SR_HZ_TO_NS(devc->cur_rate));

	/* Select the SPI/I2C trigger config bank */
	ops[5] = mso_trans(REG_CTL2, (devc->ctlbase2 | BITS_CTL2_BANK(2)));
	/* Configure the SPI/I2C protocol trigger */
	ops[6] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
	ops[7] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
	ops[8] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
	ops[9] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
	ops[10] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
	ops[11] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
	ops[12] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
	ops[13] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
	ops[14] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
	/* Select the default config bank */
	ops[15] = mso_trans(REG_CTL2, devc->ctlbase2);

	return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_configure_threshold_level(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;

	return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
}

SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
{
	uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
	struct dev_context *devc = sdi->priv;

	sr_dbg("Requesting buffer dump.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_arm(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETFSM),
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_ARM),
		mso_trans(REG_CTL1, devc->ctlbase1),
	};

	sr_dbg("Requesting trigger arm.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_CTL1, devc->ctlbase1 | 8),
		mso_trans(REG_CTL1, devc->ctlbase1),
	};

	sr_dbg("Requesting forced capture.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_dac_out(struct sr_dev_inst *sdi, uint16_t val)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[] = {
		mso_trans(REG_DAC1, (val >> 8) & 0xff),
		mso_trans(REG_DAC2, val & 0xff),
		mso_trans(REG_CTL1, devc->ctlbase1 | BIT_CTL1_RESETADC),
	};

	sr_dbg("Setting dac word to 0x%x.", val);
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context *devc)
{
	return (uint16_t) (0x200 -
			((devc->dso_trigger_voltage / devc->dso_probe_attn) /
			 devc->vbit));
}


SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct,
    struct dev_context *devc)
{
	unsigned int u1, u2, u3, u4, u5, u6;

  iProduct = iProduct;
  /* FIXME: This code is in the original app, but I think its
   * used only for the GUI */
  /*	if (strstr(iProduct, "REV_02") || strstr(iProduct, "REV_03"))
      devc->num_sample_rates = 0x16;
      else
      devc->num_sample_rates = 0x10; */
  

	/* parse iSerial */
	if (iSerial[0] != '4' || sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
				&u1, &u2, &u3, &u4, &u5, &u6) != 6)
		return SR_ERR;
	devc->hwmodel = u4;
	devc->hwrev = u5;
	devc->serial = u6;
	devc->vbit = u1 / 10000;
	if (devc->vbit == 0)
		devc->vbit = 4.19195;
	devc->dac_offset = u2;
	if (devc->dac_offset == 0)
		devc->dac_offset = 0x1ff;
	devc->offset_range = u3;
	if (devc->offset_range == 0)
		devc->offset_range = 0x17d;

	/*
	 * FIXME: There is more code on the original software to handle
	 * bigger iSerial strings, but as I can't test on my device
	 * I will not implement it yet
	 */

	return SR_OK;
}

SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial,
    uint16_t payload[], int n)
{
	int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
	char *p, *buf;

	ret = SR_ERR;

	if (serial->fd < 0)
		goto ret;

	if (!(buf = g_try_malloc(s))) {
		sr_err("Failed to malloc message buffer.");
		ret = SR_ERR_MALLOC;
		goto ret;
	}

	p = buf;
	memcpy(p, mso_head, sizeof(mso_head));
	p += sizeof(mso_head);

	for (i = 0; i < n; i++) {
		*(uint16_t *) p = htons(payload[i]);
		p += 2;
	}
	memcpy(p, mso_foot, sizeof(mso_foot));

	w = 0;
	while (w < s) {
		ret = serial_write(serial, buf + w, s - w);
		if (ret < 0) {
			ret = SR_ERR;
			goto free;
		}
		w += ret;
	}
	ret = SR_OK;
free:
	g_free(buf);
ret:
	return ret;
}

SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi)
{
	struct dev_context *devc = sdi->priv;
	uint16_t ops[2];

	ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 | BIT_CTL1_RESETADC));
	ops[1] = mso_trans(REG_CTL1, devc->ctlbase1);
	devc->ctlbase1 |= BIT_CTL1_ADC_UNKNOWN4;

	sr_dbg("Requesting ADC reset.");
	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi)
{
	struct sr_datafeed_packet packet;
	struct dev_context *devc;

	devc = sdi->priv;
	sr_source_remove(devc->serial->fd);

	/* Terminate session */
	packet.type = SR_DF_END;
	sr_session_send(sdi, &packet);
}

SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val)
{
	uint16_t ops[] = {
		mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
		mso_trans(REG_CLKRATE2, val & 0xff),
	};

	sr_dbg("Setting clkrate word to 0x%x.", val);
	return mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
}

SR_PRIV int mso_configure_rate(struct sr_dev_inst *sdi, uint32_t rate)
{
	struct dev_context *devc = sdi->priv;
	unsigned int i;
	int ret = SR_ERR;

	for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
		if (rate_map[i].rate == rate) {
			devc->ctlbase2 = rate_map[i].slowmode;
			ret = mso_clkrate_out(devc->serial, rate_map[i].val);
			if (ret == SR_OK)
				devc->cur_rate = rate;
			return ret;
		}
	}
	return ret;
}


SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial, uint8_t *info)
{
	uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
	int ret;

	sr_dbg("Requesting trigger state.");
	ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
	if (info == NULL || ret != SR_OK)
		return ret;


  uint8_t buf = 0;
	if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */
		ret = SR_ERR;
	*info = buf;

	sr_dbg("Trigger state is: 0x%x.", *info);
	return ret;
}

SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
{

	struct sr_datafeed_packet packet;
	struct sr_datafeed_logic logic;
	struct sr_dev_inst *sdi;
	struct drv_context *drvc;
	struct dev_context *devc;
	GSList *l;
	int num_channels, offset, i, j;
	unsigned char byte;

	drvc = di->priv;

	/* Find this device's devc struct by its fd. */
	devc = NULL;
	for (l = drvc->instances; l; l = l->next) {
		sdi = l->data;
		devc = sdi->priv;
		if (devc->serial->fd == fd)
			break;
		devc = NULL;
	}
	if (!devc)
		/* Shouldn't happen. */
		return TRUE;

	(void)revents;

	uint8_t in[1024];
	size_t s = serial_read(devc->serial, in, sizeof(in));
	if (s <= 0)
		return FALSE;
  
  /* No samples */
  if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
    devc->trigger_state = in[0];
    if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
      mso_read_buffer(sdi);
      devc->buffer_n = 0;
    } else {
      mso_check_trigger(devc->serial, NULL);
    }
    return FALSE;
  }

	/* the hardware always dumps 1024 samples, 24bits each */
	if (devc->buffer_n < 3072) {
		memcpy(devc->buffer + devc->buffer_n, in, s);
		devc->buffer_n += s;
	}
	if (devc->buffer_n < 3072)
		return FALSE;

	/* do the conversion */
	uint8_t logic_out[1024];
	double analog_out[1024];
	for (i = 0; i < 1024; i++) {
		/* FIXME: Need to do conversion to mV */
		analog_out[i] = (devc->buffer[i * 3] & 0x3f) |
			((devc->buffer[i * 3 + 1] & 0xf) << 6);
		logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) |
			((devc->buffer[i * 3 + 2] & 0x3f) << 2);
	}

	packet.type = SR_DF_LOGIC;
	packet.payload = &logic;
	logic.length = 1024;
	logic.unitsize = 1;
	logic.data = logic_out;
	sr_session_send(cb_data, &packet);

	// Dont bother fixing this yet, keep it "old style"
	/*
	packet.type = SR_DF_ANALOG;
	packet.length = 1024;
	packet.unitsize = sizeof(double);
	packet.payload = analog_out;
	sr_session_send(ctx->session_dev_id, &packet);
	*/

	packet.type = SR_DF_END;
	sr_session_send(devc->session_dev_id, &packet);

}
Commit	Line	Data
df92e5cf	1	/*
	2	* This file is part of the sigrok project.
	3	*
	4	* Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation, either version 3 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "protocol.h"
	21
	22	extern SR_PRIV struct sr_dev_driver link_mso19_driver_info;
	23	static struct sr_dev_driver *di = &link_mso19_driver_info;
	24
4b719338	25	SR_PRIV int mso_configure_trigger(struct sr_dev_inst *sdi)
	26	{
	27	struct dev_context *devc = sdi->priv;
	28	uint16_t ops[16];
	29	uint16_t dso_trigger = mso_calc_raw_from_mv(devc);
	30
	31	dso_trigger &= 0x3ff;
	32	if ((!devc->trigger_slope && devc->trigger_chan == 1) \|\|
	33	(devc->trigger_slope &&
	34	(devc->trigger_chan == 0 \|\|
	35	devc->trigger_chan == 2 \|\|
	36	devc->trigger_chan == 3)))
	37	dso_trigger \|= 0x400;
	38
	39	switch (devc->trigger_chan) {
	40	case 1:
	41	dso_trigger \|= 0xe000;
	42	case 2:
	43	dso_trigger \|= 0x4000;
	44	break;
	45	case 3:
	46	dso_trigger \|= 0x2000;
	47	break;
	48	case 4:
	49	dso_trigger \|= 0xa000;
	50	break;
	51	case 5:
	52	dso_trigger \|= 0x8000;
	53	break;
	54	default:
	55	case 0:
	56	break;
	57	}
	58
	59	switch (devc->trigger_outsrc) {
	60	case 1:
	61	dso_trigger \|= 0x800;
	62	break;
	63	case 2:
	64	dso_trigger \|= 0x1000;
	65	break;
	66	case 3:
	67	dso_trigger \|= 0x1800;
	68	break;
	69
	70	}
	71
	72	ops[0] = mso_trans(5, devc->la_trigger);
	73	ops[1] = mso_trans(6, devc->la_trigger_mask);
	74	ops[2] = mso_trans(3, dso_trigger & 0xff);
	75	ops[3] = mso_trans(4, (dso_trigger >> 8) & 0xff);
	76	ops[4] = mso_trans(11,
	77	devc->dso_trigger_width / SR_HZ_TO_NS(devc->cur_rate));
	78
	79	/* Select the SPI/I2C trigger config bank */
	80	ops[5] = mso_trans(REG_CTL2, (devc->ctlbase2 \| BITS_CTL2_BANK(2)));
	81	/* Configure the SPI/I2C protocol trigger */
	82	ops[6] = mso_trans(REG_PT_WORD(0), devc->protocol_trigger.word[0]);
	83	ops[7] = mso_trans(REG_PT_WORD(1), devc->protocol_trigger.word[1]);
	84	ops[8] = mso_trans(REG_PT_WORD(2), devc->protocol_trigger.word[2]);
	85	ops[9] = mso_trans(REG_PT_WORD(3), devc->protocol_trigger.word[3]);
	86	ops[10] = mso_trans(REG_PT_MASK(0), devc->protocol_trigger.mask[0]);
	87	ops[11] = mso_trans(REG_PT_MASK(1), devc->protocol_trigger.mask[1]);
	88	ops[12] = mso_trans(REG_PT_MASK(2), devc->protocol_trigger.mask[2]);
89	ops[13] = mso_trans(REG_PT_MASK(3), devc->protocol_trigger.mask[3]);
90	ops[14] = mso_trans(REG_PT_SPIMODE, devc->protocol_trigger.spimode);
91	/* Select the default config bank */
92	ops[15] = mso_trans(REG_CTL2, devc->ctlbase2);
93
94	return mso_send_control_message(sdi, ARRAY_AND_SIZE(ops));
95	}
96
97	SR_PRIV int mso_configure_threshold_level(struct sr_dev_inst *sdi)
98	{
99	struct dev_context *devc = sdi->priv;
100
101	return mso_dac_out(sdi, la_threshold_map[devc->la_threshold]);
102	}
103
104	SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi)
105	{
106	uint16_t ops[] = { mso_trans(REG_BUFFER, 0) };
107	struct dev_context *devc = sdi->priv;
108
109	sr_dbg("Requesting buffer dump.");
110	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
111	}
112
113	SR_PRIV int mso_arm(struct sr_dev_inst *sdi)
114	{
115	struct dev_context *devc = sdi->priv;
116	uint16_t ops[] = {
117	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_RESETFSM),
118	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_ARM),
119	mso_trans(REG_CTL1, devc->ctlbase1),
120	};
121
122	sr_dbg("Requesting trigger arm.");
123	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
124	}
125
126	SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi)
127	{
128	struct dev_context *devc = sdi->priv;
129	uint16_t ops[] = {
130	mso_trans(REG_CTL1, devc->ctlbase1 \| 8),
131	mso_trans(REG_CTL1, devc->ctlbase1),
132	};
133
134	sr_dbg("Requesting forced capture.");
135	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
136	}
137
138	SR_PRIV int mso_dac_out(struct sr_dev_inst *sdi, uint16_t val)
139	{
140	struct dev_context *devc = sdi->priv;
141	uint16_t ops[] = {
142	mso_trans(REG_DAC1, (val >> 8) & 0xff),
143	mso_trans(REG_DAC2, val & 0xff),
144	mso_trans(REG_CTL1, devc->ctlbase1 \| BIT_CTL1_RESETADC),
145	};
146
147	sr_dbg("Setting dac word to 0x%x.", val);
148	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
149	}
150
151	SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context *devc)
152	{
153	return (uint16_t) (0x200 -
154	((devc->dso_trigger_voltage / devc->dso_probe_attn) /
155	devc->vbit));
156	}
157
158
df92e5cf	159	SR_PRIV int mso_parse_serial(const char iSerial, const char iProduct,
	160	struct dev_context *devc)
	161	{
	162	unsigned int u1, u2, u3, u4, u5, u6;
	163
	164	iProduct = iProduct;
	165	/* FIXME: This code is in the original app, but I think its
	166	* used only for the GUI */
	167	/* if (strstr(iProduct, "REV_02") \|\| strstr(iProduct, "REV_03"))
	168	devc->num_sample_rates = 0x16;
	169	else
	170	devc->num_sample_rates = 0x10; */
	171
	172
	173	/* parse iSerial */
	174	if (iSerial[0] != '4' \|\| sscanf(iSerial, "%5u%3u%3u%1u%1u%6u",
	175	&u1, &u2, &u3, &u4, &u5, &u6) != 6)
	176	return SR_ERR;
	177	devc->hwmodel = u4;
	178	devc->hwrev = u5;
	179	devc->serial = u6;
	180	devc->vbit = u1 / 10000;
	181	if (devc->vbit == 0)
	182	devc->vbit = 4.19195;
	183	devc->dac_offset = u2;
	184	if (devc->dac_offset == 0)
	185	devc->dac_offset = 0x1ff;
	186	devc->offset_range = u3;
	187	if (devc->offset_range == 0)
	188	devc->offset_range = 0x17d;
	189
	190	/*
	191	* FIXME: There is more code on the original software to handle
	192	* bigger iSerial strings, but as I can't test on my device
	193	* I will not implement it yet
	194	*/
	195
	196	return SR_OK;
	197	}
	198
	199	SR_PRIV int mso_send_control_message(struct sr_serial_dev_inst *serial,
	200	uint16_t payload[], int n)
	201	{
	202	int i, w, ret, s = n * 2 + sizeof(mso_head) + sizeof(mso_foot);
	203	char p, buf;
	204
	205	ret = SR_ERR;
	206
	207	if (serial->fd < 0)
	208	goto ret;
	209
	210	if (!(buf = g_try_malloc(s))) {
	211	sr_err("Failed to malloc message buffer.");
	212	ret = SR_ERR_MALLOC;
	213	goto ret;
	214	}
	215
	216	p = buf;
	217	memcpy(p, mso_head, sizeof(mso_head));
	218	p += sizeof(mso_head);
	219
	220	for (i = 0; i < n; i++) {
	221	(uint16_t ) p = htons(payload[i]);
	222	p += 2;
223	}
224	memcpy(p, mso_foot, sizeof(mso_foot));
225
226	w = 0;
227	while (w < s) {
228	ret = serial_write(serial, buf + w, s - w);
229	if (ret < 0) {
230	ret = SR_ERR;
231	goto free;
232	}
233	w += ret;
234	}
235	ret = SR_OK;
236	free:
237	g_free(buf);
238	ret:
239	return ret;
240	}
241
242	SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi)
243	{
244	struct dev_context *devc = sdi->priv;
245	uint16_t ops[2];
246
247	ops[0] = mso_trans(REG_CTL1, (devc->ctlbase1 \| BIT_CTL1_RESETADC));
248	ops[1] = mso_trans(REG_CTL1, devc->ctlbase1);
249	devc->ctlbase1 \|= BIT_CTL1_ADC_UNKNOWN4;
250
251	sr_dbg("Requesting ADC reset.");
252	return mso_send_control_message(devc->serial, ARRAY_AND_SIZE(ops));
253	}
254
255	SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi)
256	{
257	struct sr_datafeed_packet packet;
258	struct dev_context *devc;
259
260	devc = sdi->priv;
261	sr_source_remove(devc->serial->fd);
262
263	/* Terminate session */
264	packet.type = SR_DF_END;
265	sr_session_send(sdi, &packet);
266	}
267
268	SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val)
269	{
270	uint16_t ops[] = {
271	mso_trans(REG_CLKRATE1, (val >> 8) & 0xff),
272	mso_trans(REG_CLKRATE2, val & 0xff),
273	};
274
275	sr_dbg("Setting clkrate word to 0x%x.", val);
276	return mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
277	}
278
279	SR_PRIV int mso_configure_rate(struct sr_dev_inst *sdi, uint32_t rate)
280	{
281	struct dev_context *devc = sdi->priv;
282	unsigned int i;
283	int ret = SR_ERR;
284
285	for (i = 0; i < ARRAY_SIZE(rate_map); i++) {
286	if (rate_map[i].rate == rate) {
287	devc->ctlbase2 = rate_map[i].slowmode;
4b719338	288	ret = mso_clkrate_out(devc->serial, rate_map[i].val);
df92e5cf	289	if (ret == SR_OK)
	290	devc->cur_rate = rate;
	291	return ret;
	292	}
	293	}
	294	return ret;
	295	}
	296
	297
	298
	299
	300
	301	SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst serial, uint8_t info)
	302	{
	303	uint16_t ops[] = { mso_trans(REG_TRIGGER, 0) };
	304	int ret;
	305
	306	sr_dbg("Requesting trigger state.");
	307	ret = mso_send_control_message(serial, ARRAY_AND_SIZE(ops));
	308	if (info == NULL \|\| ret != SR_OK)
	309	return ret;
	310
	311
	312	uint8_t buf = 0;
	313	if (serial_read(serial, &buf, 1) != 1) /* FIXME: Need timeout */
	314	ret = SR_ERR;
	315	*info = buf;
	316
	317	sr_dbg("Trigger state is: 0x%x.", *info);
	318	return ret;
	319	}
	320
	321	SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data)
	322	{
	323
	324	struct sr_datafeed_packet packet;
	325	struct sr_datafeed_logic logic;
	326	struct sr_dev_inst *sdi;
	327	struct drv_context *drvc;
	328	struct dev_context *devc;
	329	GSList *l;
	330	int num_channels, offset, i, j;
	331	unsigned char byte;
	332
	333	drvc = di->priv;
	334
	335	/* Find this device's devc struct by its fd. */
	336	devc = NULL;
	337	for (l = drvc->instances; l; l = l->next) {
	338	sdi = l->data;
	339	devc = sdi->priv;
	340	if (devc->serial->fd == fd)
	341	break;
	342	devc = NULL;
	343	}
	344	if (!devc)
	345	/* Shouldn't happen. */
	346	return TRUE;
	347
	348	(void)revents;
	349
	350	uint8_t in[1024];
	351	size_t s = serial_read(devc->serial, in, sizeof(in));
	352	if (s <= 0)
353	return FALSE;
354
355	/* No samples */
356	if (devc->trigger_state != MSO_TRIGGER_DATAREADY) {
357	devc->trigger_state = in[0];
358	if (devc->trigger_state == MSO_TRIGGER_DATAREADY) {
359	mso_read_buffer(sdi);
360	devc->buffer_n = 0;
361	} else {
362	mso_check_trigger(devc->serial, NULL);
363	}
364	return FALSE;
365	}
366
367	/* the hardware always dumps 1024 samples, 24bits each */
368	if (devc->buffer_n < 3072) {
369	memcpy(devc->buffer + devc->buffer_n, in, s);
370	devc->buffer_n += s;
371	}
372	if (devc->buffer_n < 3072)
373	return FALSE;
374
375	/* do the conversion */
376	uint8_t logic_out[1024];
377	double analog_out[1024];
378	for (i = 0; i < 1024; i++) {
379	/* FIXME: Need to do conversion to mV */
380	analog_out[i] = (devc->buffer[i * 3] & 0x3f) \|
381	((devc->buffer[i * 3 + 1] & 0xf) << 6);
382	logic_out[i] = ((devc->buffer[i * 3 + 1] & 0x30) >> 4) \|
383	((devc->buffer[i * 3 + 2] & 0x3f) << 2);
384	}
385
386	packet.type = SR_DF_LOGIC;
387	packet.payload = &logic;
388	logic.length = 1024;
389	logic.unitsize = 1;
390	logic.data = logic_out;
391	sr_session_send(cb_data, &packet);
392
393	// Dont bother fixing this yet, keep it "old style"
394	/*
395	packet.type = SR_DF_ANALOG;
396	packet.length = 1024;
397	packet.unitsize = sizeof(double);
398	packet.payload = analog_out;
399	sr_session_send(ctx->session_dev_id, &packet);
400	*/
401
402	packet.type = SR_DF_END;
403	sr_session_send(devc->session_dev_id, &packet);
404
405	}