[libsigrok.git] / hardware / link-mso19 / link-mso19.h

/*
 * This file is part of the sigrok project.
 *
 * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef LINK_MSO19_H
#define LINK_MSO19_H

/* our private per-instance data */
struct mso {
	/* info */
	uint8_t hwmodel;
	uint8_t hwrev;
	uint32_t serial;
//	uint8_t num_sample_rates;
	/* calibration */
	double vbit;
	uint16_t dac_offset;
	uint16_t offset_range;
	/* register cache */
	uint8_t ctlbase;
	uint8_t slowmode;
	/* state */
	uint8_t la_threshold;
	uint64_t cur_rate;
	uint8_t dso_probe_attn;
	uint8_t trigger_chan;
	uint8_t trigger_slope;
	uint8_t trigger_spimode;
	uint8_t trigger_outsrc;
	uint8_t trigger_state;
	uint8_t la_trigger;
	uint8_t la_trigger_mask;
	double dso_trigger_voltage;
	uint16_t dso_trigger_width;
	gpointer session_id;
	uint16_t buffer_n;
	char buffer[4096];
};

/* serial protocol */
#define mso_trans(a, v) \
	(((v) & 0x3f) | (((v) & 0xc0) << 6) | (((a) & 0xf) << 8) | \
	((~(v) & 0x20) << 1) | ((~(v) & 0x80) << 7))

const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
const char mso_foot[] = { 0x7e };

/* registers */
#define REG_BUFFER		1
#define REG_TRIGGER		2
#define REG_CLKRATE1		9
#define REG_CLKRATE2		10
#define REG_DAC1		12
#define REG_DAC2		13
#define REG_CTL			14

/* bits */
#define BIT_CTL_RESETFSM	(1 << 0)
#define BIT_CTL_ARM		(1 << 1)
#define BIT_CTL_ADC_UNKNOWN4	(1 << 4) /* adc enable? */
#define BIT_CTL_RESETADC	(1 << 6)
#define BIT_CTL_LED		(1 << 7)

struct rate_map {
	uint32_t rate;
	uint16_t val;
	uint8_t slowmode;
};

static struct rate_map rate_map[] = {
	{ MHZ(200),	0x0205, 0	},
	{ MHZ(100),	0x0105, 0	},
	{ MHZ(50),	0x0005, 0	},
	{ MHZ(20),	0x0303, 0	},
	{ MHZ(10),	0x0308, 0	},
	{ MHZ(5),	0x030c, 0	},
	{ MHZ(2),	0x0330, 0	},
	{ MHZ(1),	0x0362, 0	},
	{ KHZ(500),	0x03c6, 0	},
	{ KHZ(200),	0x07f2, 0	},
	{ KHZ(100),	0x0fe6, 0	},
	{ KHZ(50),	0x1fce, 0	},
	{ KHZ(20),	0x4f86, 0	},
	{ KHZ(10),	0x9f0e, 0	},
	{ KHZ(5),	0x03c7, 0x20	},
	{ KHZ(2),	0x07f3, 0x20	},
	{ KHZ(1),	0x0fe7, 0x20	},
	{ 500,		0x1fcf, 0x20	},
	{ 200,		0x4f87, 0x20	},
	{ 100,		0x9f0f, 0x20	},
};

/* FIXME: Determine corresponding voltages */
uint16_t la_threshold_map[] = {
	0x8600,
	0x8770,
	0x88ff,
	0x8c70,
	0x8eff,
	0x8fff,
};

#endif
Commit	Line	Data
01cf8814 DR	1	/*
	2	* This file is part of the sigrok project.
	3	*
	4	* Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation, either version 3 of the License, or
	9	* (at your option) any later version.
8a839354 UH	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
01cf8814 DR	18	*/
	19
	20	#ifndef LINK_MSO19_H
	21	#define LINK_MSO19_H
	22
	23	/* our private per-instance data */
	24	struct mso {
	25	/* info */
	26	uint8_t hwmodel;
	27	uint8_t hwrev;
	28	uint32_t serial;
	29	// uint8_t num_sample_rates;
	30	/* calibration */
	31	double vbit;
	32	uint16_t dac_offset;
	33	uint16_t offset_range;
	34	/* register cache */
	35	uint8_t ctlbase;
	36	uint8_t slowmode;
	37	/* state */
	38	uint8_t la_threshold;
	39	uint64_t cur_rate;
	40	uint8_t dso_probe_attn;
	41	uint8_t trigger_chan;
	42	uint8_t trigger_slope;
	43	uint8_t trigger_spimode;
	44	uint8_t trigger_outsrc;
	45	uint8_t trigger_state;
	46	uint8_t la_trigger;
	47	uint8_t la_trigger_mask;
	48	double dso_trigger_voltage;
	49	uint16_t dso_trigger_width;
	50	gpointer session_id;
	51	uint16_t buffer_n;
	52	char buffer[4096];
	53	};
	54
	55	/* serial protocol */
	56	#define mso_trans(a, v) \
	57	(((v) & 0x3f) \| (((v) & 0xc0) << 6) \| (((a) & 0xf) << 8) \| \
	58	((~(v) & 0x20) << 1) \| ((~(v) & 0x80) << 7))
	59
	60	const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
	61	const char mso_foot[] = { 0x7e };
	62
	63	/* registers */
	64	#define REG_BUFFER 1
	65	#define REG_TRIGGER 2
	66	#define REG_CLKRATE1 9
	67	#define REG_CLKRATE2 10
	68	#define REG_DAC1 12
	69	#define REG_DAC2 13
	70	#define REG_CTL 14
	71
	72	/* bits */
	73	#define BIT_CTL_RESETFSM (1 << 0)
	74	#define BIT_CTL_ARM (1 << 1)
	75	#define BIT_CTL_ADC_UNKNOWN4 (1 << 4) /* adc enable? */
	76	#define BIT_CTL_RESETADC (1 << 6)
	77	#define BIT_CTL_LED (1 << 7)
	78
	79	struct rate_map {
	80	uint32_t rate;
	81	uint16_t val;
82	uint8_t slowmode;
83	};
84
85	static struct rate_map rate_map[] = {
86	{ MHZ(200), 0x0205, 0 },
87	{ MHZ(100), 0x0105, 0 },
88	{ MHZ(50), 0x0005, 0 },
89	{ MHZ(20), 0x0303, 0 },
90	{ MHZ(10), 0x0308, 0 },
91	{ MHZ(5), 0x030c, 0 },
92	{ MHZ(2), 0x0330, 0 },
93	{ MHZ(1), 0x0362, 0 },
94	{ KHZ(500), 0x03c6, 0 },
95	{ KHZ(200), 0x07f2, 0 },
96	{ KHZ(100), 0x0fe6, 0 },
97	{ KHZ(50), 0x1fce, 0 },
98	{ KHZ(20), 0x4f86, 0 },
99	{ KHZ(10), 0x9f0e, 0 },
100	{ KHZ(5), 0x03c7, 0x20 },
101	{ KHZ(2), 0x07f3, 0x20 },
102	{ KHZ(1), 0x0fe7, 0x20 },
103	{ 500, 0x1fcf, 0x20 },
104	{ 200, 0x4f87, 0x20 },
105	{ 100, 0x9f0f, 0x20 },
106	};
107
108	/* FIXME: Determine corresponding voltages */
109	uint16_t la_threshold_map[] = {
110	0x8600,
111	0x8770,
112	0x88ff,
113	0x8c70,
114	0x8eff,
115	0x8fff,
116	};
01cf8814	117
8a839354	118	#endif