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01cf8814 DR |
1 | /* |
2 | * This file is part of the sigrok project. | |
3 | * | |
4 | * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com> | |
80aa5f23 | 5 | * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt> |
01cf8814 DR |
6 | * |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation, either version 3 of the License, or | |
10 | * (at your option) any later version. | |
8a839354 UH |
11 | * |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
01cf8814 DR |
19 | */ |
20 | ||
c2bd92ec UH |
21 | #ifndef SIGROK_LINK_MSO19_H |
22 | #define SIGROK_LINK_MSO19_H | |
01cf8814 | 23 | |
80aa5f23 RC |
24 | /* Structure for the pattern generator state */ |
25 | struct mso_patgen { | |
26 | /* Pattern generator clock config */ | |
27 | uint16_t clock; | |
28 | /* Buffer start address */ | |
29 | uint16_t start; | |
30 | /* Buffer end address */ | |
31 | uint16_t end; | |
32 | /* Pattern generator config */ | |
33 | uint8_t config; | |
34 | /* Samples buffer */ | |
35 | uint8_t buffer[1024]; | |
36 | /* Input/output configuration for the samples buffer (?)*/ | |
37 | uint8_t io[1024]; | |
38 | /* Number of loops for the pattern generator */ | |
39 | uint8_t loops; | |
40 | /* Bit enable mask for the I/O lines */ | |
41 | uint8_t mask; | |
42 | }; | |
43 | ||
44 | /* Data structure for the protocol trigger state */ | |
45 | struct mso_prototrig { | |
46 | /* Word match buffer */ | |
47 | uint8_t word[4]; | |
48 | /* Masks for the wordmatch buffer */ | |
49 | uint8_t mask[4]; | |
50 | /* SPI mode 0, 1, 2, 3. Set to 0 for I2C */ | |
51 | uint8_t spimode; | |
52 | }; | |
53 | ||
01cf8814 DR |
54 | /* our private per-instance data */ |
55 | struct mso { | |
56 | /* info */ | |
57 | uint8_t hwmodel; | |
58 | uint8_t hwrev; | |
59 | uint32_t serial; | |
60 | // uint8_t num_sample_rates; | |
61 | /* calibration */ | |
62 | double vbit; | |
63 | uint16_t dac_offset; | |
64 | uint16_t offset_range; | |
65 | /* register cache */ | |
66 | uint8_t ctlbase; | |
67 | uint8_t slowmode; | |
68 | /* state */ | |
69 | uint8_t la_threshold; | |
70 | uint64_t cur_rate; | |
71 | uint8_t dso_probe_attn; | |
72 | uint8_t trigger_chan; | |
73 | uint8_t trigger_slope; | |
74 | uint8_t trigger_spimode; | |
75 | uint8_t trigger_outsrc; | |
76 | uint8_t trigger_state; | |
77 | uint8_t la_trigger; | |
78 | uint8_t la_trigger_mask; | |
79 | double dso_trigger_voltage; | |
80 | uint16_t dso_trigger_width; | |
81 | gpointer session_id; | |
82 | uint16_t buffer_n; | |
83 | char buffer[4096]; | |
84 | }; | |
85 | ||
86 | /* serial protocol */ | |
87 | #define mso_trans(a, v) \ | |
88 | (((v) & 0x3f) | (((v) & 0xc0) << 6) | (((a) & 0xf) << 8) | \ | |
89 | ((~(v) & 0x20) << 1) | ((~(v) & 0x80) << 7)) | |
90 | ||
91 | const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e }; | |
92 | const char mso_foot[] = { 0x7e }; | |
93 | ||
94 | /* registers */ | |
95 | #define REG_BUFFER 1 | |
96 | #define REG_TRIGGER 2 | |
97 | #define REG_CLKRATE1 9 | |
98 | #define REG_CLKRATE2 10 | |
99 | #define REG_DAC1 12 | |
100 | #define REG_DAC2 13 | |
101 | #define REG_CTL 14 | |
102 | ||
103 | /* bits */ | |
104 | #define BIT_CTL_RESETFSM (1 << 0) | |
105 | #define BIT_CTL_ARM (1 << 1) | |
106 | #define BIT_CTL_ADC_UNKNOWN4 (1 << 4) /* adc enable? */ | |
107 | #define BIT_CTL_RESETADC (1 << 6) | |
108 | #define BIT_CTL_LED (1 << 7) | |
109 | ||
110 | struct rate_map { | |
111 | uint32_t rate; | |
112 | uint16_t val; | |
113 | uint8_t slowmode; | |
114 | }; | |
115 | ||
116 | static struct rate_map rate_map[] = { | |
59df0c77 UH |
117 | { SR_MHZ(200), 0x0205, 0 }, |
118 | { SR_MHZ(100), 0x0105, 0 }, | |
119 | { SR_MHZ(50), 0x0005, 0 }, | |
120 | { SR_MHZ(20), 0x0303, 0 }, | |
121 | { SR_MHZ(10), 0x0308, 0 }, | |
122 | { SR_MHZ(5), 0x030c, 0 }, | |
123 | { SR_MHZ(2), 0x0330, 0 }, | |
124 | { SR_MHZ(1), 0x0362, 0 }, | |
125 | { SR_KHZ(500), 0x03c6, 0 }, | |
126 | { SR_KHZ(200), 0x07f2, 0 }, | |
127 | { SR_KHZ(100), 0x0fe6, 0 }, | |
128 | { SR_KHZ(50), 0x1fce, 0 }, | |
129 | { SR_KHZ(20), 0x4f86, 0 }, | |
130 | { SR_KHZ(10), 0x9f0e, 0 }, | |
131 | { SR_KHZ(5), 0x03c7, 0x20 }, | |
132 | { SR_KHZ(2), 0x07f3, 0x20 }, | |
133 | { SR_KHZ(1), 0x0fe7, 0x20 }, | |
01cf8814 DR |
134 | { 500, 0x1fcf, 0x20 }, |
135 | { 200, 0x4f87, 0x20 }, | |
136 | { 100, 0x9f0f, 0x20 }, | |
137 | }; | |
138 | ||
139 | /* FIXME: Determine corresponding voltages */ | |
140 | uint16_t la_threshold_map[] = { | |
141 | 0x8600, | |
142 | 0x8770, | |
143 | 0x88ff, | |
144 | 0x8c70, | |
145 | 0x8eff, | |
146 | 0x8fff, | |
147 | }; | |
01cf8814 | 148 | |
8a839354 | 149 | #endif |