[libsigrok.git] / hardware / hantek-dso / dso.h

/*
 * This file is part of the sigrok project.
 *
 * Copyright (C) 2012 Bert Vermeulen <bert@biot.com>
 * With protocol information from the hantekdso project,
 * Copyright (C) 2008 Oleg Khudyakov <prcoder@gmail.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef LIBSIGROK_HARDWARE_HANTEK_DSO_H
#define LIBSIGROK_HARDWARE_HANTEK_DSO_H

#define USB_INTERFACE          0
#define USB_CONFIGURATION      1
#define DSO_EP_IN              0x86
#define DSO_EP_OUT             0x02

/* FX2 renumeration delay in ms */
#define MAX_RENUM_DELAY        3000

#define MAX_CAPTURE_EMPTY      3

#define DEFAULT_VOLTAGE            VOLTAGE_2V
#define DEFAULT_FRAMESIZE          FRAMESIZE_SMALL
#define DEFAULT_TIMEBASE           TIME_400us
#define DEFAULT_TRIGGER_SOURCE     TRIGGER_CH1
#define DEFAULT_COUPLING           COUPLING_AC
#define DEFAULT_HORIZ_TRIGGERPOS   0.5
#define DEFAULT_VERT_OFFSET        0.5
#define DEFAULT_VERT_TRIGGERPOS    0.0

#define MAX_VERT_TRIGGER           0xfe

/* Hantek DSO-specific protocol values */
#define EEPROM_CHANNEL_OFFSETS     0x08

#define FRAMESIZE_SMALL        10240
#define FRAMESIZE_LARGE        32768


enum control_requests {
	CTRL_READ_EEPROM = 0xa2,
	CTRL_GETSPEED = 0xb2,
	CTRL_BEGINCOMMAND = 0xb3,
	CTRL_SETOFFSET = 0xb4,
	CTRL_SETRELAYS = 0xb5
};

enum dso_commands {
	CMD_SET_FILTERS = 0,
	CMD_SET_TRIGGER_SAMPLERATE,
	CMD_FORCE_TRIGGER,
	CMD_CAPTURE_START,
	CMD_ENABLE_TRIGGER,
	CMD_GET_CHANNELDATA,
	CMD_GET_CAPTURESTATE,
	CMD_SET_VOLTAGE,
	cmdSetLogicalData,
	cmdGetLogicalData
};

enum voltages {
	VOLTAGE_5V = 0,
	VOLTAGE_2V,
	VOLTAGE_1V,
	VOLTAGE_500mV,
	VOLTAGE_200mV,
	VOLTAGE_100mV,
	VOLTAGE_50mV,
	VOLTAGE_20mV,
	VOLTAGE_10mV
};

enum couplings {
	COUPLING_AC = 0,
	COUPLING_DC,
	COUPLING_OFF
};

enum time_bases {
	TIME_10us = 0,
	TIME_20us,
	TIME_40us,
	TIME_100us,
	TIME_200us,
	TIME_400us,
	TIME_1ms,
	TIME_2ms,
	TIME_4ms,
	TIME_10ms,
	TIME_20ms,
	TIME_40ms,
	TIME_100ms,
	TIME_200ms,
	TIME_400ms
};

enum trigger_slopes {
	SLOPE_POSITIVE = 0,
	SLOPE_NEGATIVE
};

enum trigger_sources {
	TRIGGER_CH2 = 0,
	TRIGGER_CH1,
	TRIGGER_EXT,
};

enum capturestates {
	CAPTURE_EMPTY = 0,
	CAPTURE_FILLING = 1,
	CAPTURE_READY_8BIT = 2,
	CAPTURE_READY_9BIT = 7,
	CAPTURE_TIMEOUT = 127,
	CAPTURE_UNKNOWN = 255
};

enum triggermodes {
	TRIGGERMODE_AUTO,
	TRIGGERMODE_NORMAL,
	TRIGGERMODE_SINGLE
};

enum states {
	IDLE,
	NEW_CAPTURE,
	CAPTURE,
	FETCH_DATA
};

struct dso_profile {
	/* VID/PID after cold boot */
	uint16_t orig_vid;
	uint16_t orig_pid;
	/* VID/PID after firmware upload */
	uint16_t fw_vid;
	uint16_t fw_pid;
	char *vendor;
	char *model;
	char *model_version;
	int num_probes;
	char *firmware;
};

struct context {
	struct dso_profile *profile;
	struct sr_usb_dev_inst *usb;
	void *cb_data;
	uint64_t limit_frames;
	uint64_t num_frames;
	/* We can't keep track of an FX2-based device after upgrading
	 * the firmware (it re-enumerates into a different device address
	 * after the upgrade) this is like a global lock. No device will open
	 * until a proper delay after the last device was upgraded.
	 */
	GTimeVal fw_updated;
	int epin_maxpacketsize;
	int capture_empty_count;
	int current_transfer;
	int dev_state;

	int timebase;
	gboolean ch1_enabled;
	gboolean ch2_enabled;
	int voltage_ch1;
	int voltage_ch2;
	int coupling_ch1;
	int coupling_ch2;
	// voltage offset (vertical position)
	float voffset_ch1;
	float voffset_ch2;
	float voffset_trigger;
	uint16_t channel_levels[2][9][2];
	int framesize;
	gboolean filter_ch1;
	gboolean filter_ch2;
	gboolean filter_trigger;
	int triggerslope;
	int triggersource;
	float triggerposition;
	int triggermode;
};

SR_PRIV int dso_open(int dev_index);
SR_PRIV void dso_close(struct sr_dev_inst *sdi);
SR_PRIV int dso_enable_trigger(struct context *ctx);
SR_PRIV int dso_force_trigger(struct context *ctx);
SR_PRIV int dso_init(struct context *ctx);
SR_PRIV uint8_t dso_get_capturestate(struct context *ctx);
SR_PRIV uint8_t dso_capture_start(struct context *ctx);
SR_PRIV int dso_get_channeldata(struct context *ctx, libusb_transfer_cb_fn cb);

#endif
Commit	Line	Data
3b533202 BV	1	/*
	2	* This file is part of the sigrok project.
	3	*
	4	* Copyright (C) 2012 Bert Vermeulen <bert@biot.com>
	5	* With protocol information from the hantekdso project,
	6	* Copyright (C) 2008 Oleg Khudyakov <prcoder@gmail.com>
	7	*
	8	* This program is free software: you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation, either version 3 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#ifndef LIBSIGROK_HARDWARE_HANTEK_DSO_H
	23	#define LIBSIGROK_HARDWARE_HANTEK_DSO_H
	24
	25	#define USB_INTERFACE 0
	26	#define USB_CONFIGURATION 1
	27	#define DSO_EP_IN 0x86
	28	#define DSO_EP_OUT 0x02
	29
	30	/* FX2 renumeration delay in ms */
	31	#define MAX_RENUM_DELAY 3000
	32
	33	#define MAX_CAPTURE_EMPTY 3
	34
	35	#define DEFAULT_VOLTAGE VOLTAGE_2V
	36	#define DEFAULT_FRAMESIZE FRAMESIZE_SMALL
bc79e906	37	#define DEFAULT_TIMEBASE TIME_400us
3b533202 BV	38	#define DEFAULT_TRIGGER_SOURCE TRIGGER_CH1
3b533202 BV	39	#define DEFAULT_COUPLING COUPLING_AC
bc79e906	40	#define DEFAULT_HORIZ_TRIGGERPOS 0.5
3b533202 BV	41	#define DEFAULT_VERT_OFFSET 0.5
	42	#define DEFAULT_VERT_TRIGGERPOS 0.0
	43
	44	#define MAX_VERT_TRIGGER 0xfe
	45
	46	/* Hantek DSO-specific protocol values */
	47	#define EEPROM_CHANNEL_OFFSETS 0x08
	48
	49	#define FRAMESIZE_SMALL 10240
	50	#define FRAMESIZE_LARGE 32768
	51
	52
	53	enum control_requests {
	54	CTRL_READ_EEPROM = 0xa2,
	55	CTRL_GETSPEED = 0xb2,
	56	CTRL_BEGINCOMMAND = 0xb3,
	57	CTRL_SETOFFSET = 0xb4,
	58	CTRL_SETRELAYS = 0xb5
	59	};
	60
	61	enum dso_commands {
	62	CMD_SET_FILTERS = 0,
	63	CMD_SET_TRIGGER_SAMPLERATE,
	64	CMD_FORCE_TRIGGER,
	65	CMD_CAPTURE_START,
	66	CMD_ENABLE_TRIGGER,
	67	CMD_GET_CHANNELDATA,
	68	CMD_GET_CAPTURESTATE,
	69	CMD_SET_VOLTAGE,
	70	cmdSetLogicalData,
	71	cmdGetLogicalData
	72	};
	73
	74	enum voltages {
	75	VOLTAGE_5V = 0,
	76	VOLTAGE_2V,
	77	VOLTAGE_1V,
	78	VOLTAGE_500mV,
	79	VOLTAGE_200mV,
	80	VOLTAGE_100mV,
	81	VOLTAGE_50mV,
	82	VOLTAGE_20mV,
	83	VOLTAGE_10mV
	84	};
	85
	86	enum couplings {
	87	COUPLING_AC = 0,
	88	COUPLING_DC,
	89	COUPLING_OFF
	90	};
	91
	92	enum time_bases {
	93	TIME_10us = 0,
	94	TIME_20us,
	95	TIME_40us,
	96	TIME_100us,
	97	TIME_200us,
	98	TIME_400us,
	99	TIME_1ms,
	100	TIME_2ms,
	101	TIME_4ms,
	102	TIME_10ms,
	103	TIME_20ms,
	104	TIME_40ms,
105	TIME_100ms,
106	TIME_200ms,
107	TIME_400ms
108	};
109
110	enum trigger_slopes {
111	SLOPE_POSITIVE = 0,
112	SLOPE_NEGATIVE
113	};
114
115	enum trigger_sources {
116	TRIGGER_CH2 = 0,
117	TRIGGER_CH1,
3b533202	118	TRIGGER_EXT,
3b533202 BV	119	};
3b533202 BV	120
3b533202 BV	121	enum capturestates {
	122	CAPTURE_EMPTY = 0,
	123	CAPTURE_FILLING = 1,
	124	CAPTURE_READY_8BIT = 2,
	125	CAPTURE_READY_9BIT = 7,
	126	CAPTURE_TIMEOUT = 127,
	127	CAPTURE_UNKNOWN = 255
	128	};
	129
	130	enum triggermodes {
	131	TRIGGERMODE_AUTO,
	132	TRIGGERMODE_NORMAL,
	133	TRIGGERMODE_SINGLE
	134	};
	135
	136	enum states {
	137	IDLE,
	138	NEW_CAPTURE,
	139	CAPTURE,
	140	FETCH_DATA
	141	};
	142
	143	struct dso_profile {
	144	/* VID/PID after cold boot */
	145	uint16_t orig_vid;
	146	uint16_t orig_pid;
	147	/* VID/PID after firmware upload */
	148	uint16_t fw_vid;
	149	uint16_t fw_pid;
	150	char *vendor;
	151	char *model;
	152	char *model_version;
	153	int num_probes;
	154	char *firmware;
	155	};
	156
	157	struct context {
	158	struct dso_profile *profile;
	159	struct sr_usb_dev_inst *usb;
	160	void *cb_data;
ae88b97b BV	161	uint64_t limit_frames;
ae88b97b BV	162	uint64_t num_frames;
3b533202 BV	163	/* We can't keep track of an FX2-based device after upgrading
	164	* the firmware (it re-enumerates into a different device address
	165	* after the upgrade) this is like a global lock. No device will open
	166	* until a proper delay after the last device was upgraded.
	167	*/
	168	GTimeVal fw_updated;
	169	int epin_maxpacketsize;
	170	int capture_empty_count;
	171	int current_transfer;
	172	int dev_state;
	173
	174	int timebase;
	175	gboolean ch1_enabled;
	176	gboolean ch2_enabled;
	177	int voltage_ch1;
	178	int voltage_ch2;
	179	int coupling_ch1;
	180	int coupling_ch2;
	181	// voltage offset (vertical position)
	182	float voffset_ch1;
	183	float voffset_ch2;
	184	float voffset_trigger;
	185	uint16_t channel_levels[2][9][2];
3b533202 BV	186	int framesize;
	187	gboolean filter_ch1;
	188	gboolean filter_ch2;
	189	gboolean filter_trigger;
	190	int triggerslope;
	191	int triggersource;
bc79e906	192	float triggerposition;
3b533202 BV	193	int triggermode;
	194	};
	195
	196	SR_PRIV int dso_open(int dev_index);
	197	SR_PRIV void dso_close(struct sr_dev_inst *sdi);
	198	SR_PRIV int dso_enable_trigger(struct context *ctx);
	199	SR_PRIV int dso_force_trigger(struct context *ctx);
	200	SR_PRIV int dso_init(struct context *ctx);
	201	SR_PRIV uint8_t dso_get_capturestate(struct context *ctx);
	202	SR_PRIV uint8_t dso_capture_start(struct context *ctx);
	203	SR_PRIV int dso_get_channeldata(struct context *ctx, libusb_transfer_cb_fn cb);
	204
	205	#endif