[libsigrok.git] / hardware / asix-sigma / asix-sigma.h

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>,
 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_ASIX_SIGMA_H
#define LIBSIGROK_HARDWARE_ASIX_SIGMA_ASIX_SIGMA_H

#define LOG_PREFIX "asix-sigma"

enum sigma_write_register {
	WRITE_CLOCK_SELECT	= 0,
	WRITE_TRIGGER_SELECT0	= 1,
	WRITE_TRIGGER_SELECT1	= 2,
	WRITE_MODE		= 3,
	WRITE_MEMROW		= 4,
	WRITE_POST_TRIGGER	= 5,
	WRITE_TRIGGER_OPTION	= 6,
	WRITE_PIN_VIEW		= 7,

	WRITE_TEST		= 15,
};

enum sigma_read_register {
	READ_ID			= 0,
	READ_TRIGGER_POS_LOW	= 1,
	READ_TRIGGER_POS_HIGH	= 2,
	READ_TRIGGER_POS_UP	= 3,
	READ_STOP_POS_LOW	= 4,
	READ_STOP_POS_HIGH	= 5,
	READ_STOP_POS_UP	= 6,
	READ_MODE		= 7,
	READ_PIN_CHANGE_LOW	= 8,
	READ_PIN_CHANGE_HIGH	= 9,
	READ_BLOCK_LAST_TS_LOW	= 10,
	READ_BLOCK_LAST_TS_HIGH	= 11,
	READ_PIN_VIEW		= 12,

	READ_TEST		= 15,
};

#define REG_ADDR_LOW		(0 << 4)
#define REG_ADDR_HIGH		(1 << 4)
#define REG_DATA_LOW		(2 << 4)
#define REG_DATA_HIGH_WRITE	(3 << 4)
#define REG_READ_ADDR		(4 << 4)
#define REG_DRAM_WAIT_ACK	(5 << 4)

/* Bit (1 << 4) can be low or high (double buffer / cache) */
#define REG_DRAM_BLOCK		(6 << 4)
#define REG_DRAM_BLOCK_BEGIN	(8 << 4)
#define REG_DRAM_BLOCK_DATA	(10 << 4)

#define LEDSEL0			6
#define LEDSEL1			7

#define NEXT_REG		1

#define EVENTS_PER_CLUSTER	7

#define CHUNK_SIZE		1024

struct clockselect_50 {
	uint8_t async;
	uint8_t fraction;
	uint16_t disabled_channels;
};

/* The effect of all these are still a bit unclear. */
struct triggerinout {
	uint8_t trgout_resistor_enable : 1;
	uint8_t trgout_resistor_pullup : 1;
	uint8_t reserved1 : 1;
	uint8_t trgout_bytrigger : 1;
	uint8_t trgout_byevent : 1;
	uint8_t trgout_bytriggerin : 1;
	uint8_t reserved2 : 2;

	/* Should be set same as the first two */
	uint8_t trgout_resistor_enable2 : 1;
	uint8_t trgout_resistor_pullup2 : 1;

	uint8_t reserved3 : 1;
	uint8_t trgout_long : 1;
	uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */
	uint8_t trgin_negate : 1;
	uint8_t trgout_enable : 1;
	uint8_t trgin_enable : 1;
};

struct triggerlut {
	/* The actual LUTs. */
	uint16_t m0d[4], m1d[4], m2d[4];
	uint16_t m3, m3s, m4;

	/* Paramters should be sent as a single register write. */
	struct {
		uint8_t selc : 2;
		uint8_t selpresc : 6;

		uint8_t selinc : 2;
		uint8_t selres : 2;
		uint8_t sela : 2;
		uint8_t selb : 2;

		uint16_t cmpb;
		uint16_t cmpa;
	} params;
};

/* Trigger configuration */
struct sigma_trigger {
	/* Only two channels can be used in mask. */
	uint16_t risingmask;
	uint16_t fallingmask;

	/* Simple trigger support (<= 50 MHz). */
	uint16_t simplemask;
	uint16_t simplevalue;

	/* TODO: Advanced trigger support (boolean expressions). */
};

/* Events for trigger operation. */
enum triggerop {
	OP_LEVEL = 1,
	OP_NOT,
	OP_RISE,
	OP_FALL,
	OP_RISEFALL,
	OP_NOTRISE,
	OP_NOTFALL,
	OP_NOTRISEFALL,
};

/* Logical functions for trigger operation. */
enum triggerfunc {
	FUNC_AND = 1,
	FUNC_NAND,
	FUNC_OR,
	FUNC_NOR,
	FUNC_XOR,
	FUNC_NXOR,
};

struct sigma_state {
	enum {
		SIGMA_UNINITIALIZED = 0,
		SIGMA_IDLE,
		SIGMA_CAPTURE,
		SIGMA_DOWNLOAD,
	} state;

	uint32_t stoppos, triggerpos;
	uint16_t lastts;
	uint16_t lastsample;

	int triggerchunk;
	int chunks_downloaded;
};

/* Private, per-device-instance driver context. */
struct dev_context {
	struct ftdi_context ftdic;
	uint64_t cur_samplerate;
	uint64_t period_ps;
	uint64_t limit_msec;
	struct timeval start_tv;
	int cur_firmware;
	int num_channels;
	int samples_per_event;
	int capture_ratio;
	struct sigma_trigger trigger;
	int use_triggers;
	struct sigma_state state;
	void *cb_data;
};

#endif
Commit	Line	Data
204b1629	1	/*
50985c20	2	* This file is part of the libsigrok project.
204b1629 UH	3	*
	4	* Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>,
	5	* Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
	6	* Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
	7	*
	8	* This program is free software: you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation, either version 3 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
0f8522bf UH	22	#ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_ASIX_SIGMA_H
0f8522bf UH	23	#define LIBSIGROK_HARDWARE_ASIX_SIGMA_ASIX_SIGMA_H
28a35d8a	24
3544f848	25	#define LOG_PREFIX "asix-sigma"
47f4f073	26
fefa1800	27	enum sigma_write_register {
28a35d8a HE	28	WRITE_CLOCK_SELECT = 0,
	29	WRITE_TRIGGER_SELECT0 = 1,
	30	WRITE_TRIGGER_SELECT1 = 2,
	31	WRITE_MODE = 3,
	32	WRITE_MEMROW = 4,
	33	WRITE_POST_TRIGGER = 5,
	34	WRITE_TRIGGER_OPTION = 6,
	35	WRITE_PIN_VIEW = 7,
	36
fefa1800	37	WRITE_TEST = 15,
28a35d8a HE	38	};
28a35d8a HE	39
fefa1800	40	enum sigma_read_register {
28a35d8a HE	41	READ_ID = 0,
	42	READ_TRIGGER_POS_LOW = 1,
	43	READ_TRIGGER_POS_HIGH = 2,
	44	READ_TRIGGER_POS_UP = 3,
	45	READ_STOP_POS_LOW = 4,
	46	READ_STOP_POS_HIGH = 5,
	47	READ_STOP_POS_UP = 6,
	48	READ_MODE = 7,
	49	READ_PIN_CHANGE_LOW = 8,
	50	READ_PIN_CHANGE_HIGH = 9,
	51	READ_BLOCK_LAST_TS_LOW = 10,
	52	READ_BLOCK_LAST_TS_HIGH = 11,
	53	READ_PIN_VIEW = 12,
	54
fefa1800	55	READ_TEST = 15,
28a35d8a HE	56	};
	57
	58	#define REG_ADDR_LOW (0 << 4)
	59	#define REG_ADDR_HIGH (1 << 4)
	60	#define REG_DATA_LOW (2 << 4)
	61	#define REG_DATA_HIGH_WRITE (3 << 4)
	62	#define REG_READ_ADDR (4 << 4)
	63	#define REG_DRAM_WAIT_ACK (5 << 4)
	64
	65	/* Bit (1 << 4) can be low or high (double buffer / cache) */
	66	#define REG_DRAM_BLOCK (6 << 4)
	67	#define REG_DRAM_BLOCK_BEGIN (8 << 4)
	68	#define REG_DRAM_BLOCK_DATA (10 << 4)
	69
57bbf56b HE	70	#define LEDSEL0 6
	71	#define LEDSEL1 7
	72
28a35d8a HE	73	#define NEXT_REG 1
	74
	75	#define EVENTS_PER_CLUSTER 7
	76
	77	#define CHUNK_SIZE 1024
	78
edca2c5c HE	79	struct clockselect_50 {
	80	uint8_t async;
	81	uint8_t fraction;
ba7dd8bb	82	uint16_t disabled_channels;
edca2c5c HE	83	};
edca2c5c HE	84
57bbf56b HE	85	/* The effect of all these are still a bit unclear. */
	86	struct triggerinout {
	87	uint8_t trgout_resistor_enable : 1;
	88	uint8_t trgout_resistor_pullup : 1;
	89	uint8_t reserved1 : 1;
	90	uint8_t trgout_bytrigger : 1;
	91	uint8_t trgout_byevent : 1;
	92	uint8_t trgout_bytriggerin : 1;
	93	uint8_t reserved2 : 2;
	94
	95	/* Should be set same as the first two */
	96	uint8_t trgout_resistor_enable2 : 1;
	97	uint8_t trgout_resistor_pullup2 : 1;
	98
	99	uint8_t reserved3 : 1;
	100	uint8_t trgout_long : 1;
	101	uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */
	102	uint8_t trgin_negate : 1;
	103	uint8_t trgout_enable : 1;
	104	uint8_t trgin_enable : 1;
	105	};
	106
ee492173 HE	107	struct triggerlut {
	108	/* The actual LUTs. */
	109	uint16_t m0d[4], m1d[4], m2d[4];
	110	uint16_t m3, m3s, m4;
	111
	112	/* Paramters should be sent as a single register write. */
	113	struct {
	114	uint8_t selc : 2;
	115	uint8_t selpresc : 6;
	116
	117	uint8_t selinc : 2;
	118	uint8_t selres : 2;
	119	uint8_t sela : 2;
	120	uint8_t selb : 2;
	121
	122	uint16_t cmpb;
	123	uint16_t cmpa;
	124	} params;
	125	};
	126
c53d793f HE	127	/* Trigger configuration */
c53d793f HE	128	struct sigma_trigger {
ba7dd8bb	129	/* Only two channels can be used in mask. */
a42aec7f HE	130	uint16_t risingmask;
a42aec7f HE	131	uint16_t fallingmask;
c53d793f HE	132
	133	/* Simple trigger support (<= 50 MHz). */
	134	uint16_t simplemask;
	135	uint16_t simplevalue;
	136
c53d793f HE	137	/* TODO: Advanced trigger support (boolean expressions). */
	138	};
	139
	140	/* Events for trigger operation. */
	141	enum triggerop {
	142	OP_LEVEL = 1,
	143	OP_NOT,
	144	OP_RISE,
	145	OP_FALL,
	146	OP_RISEFALL,
	147	OP_NOTRISE,
	148	OP_NOTFALL,
	149	OP_NOTRISEFALL,
	150	};
	151
	152	/* Logical functions for trigger operation. */
	153	enum triggerfunc {
	154	FUNC_AND = 1,
	155	FUNC_NAND,
	156	FUNC_OR,
	157	FUNC_NOR,
	158	FUNC_XOR,
	159	FUNC_NXOR,
	160	};
	161
6aac7737 HE	162	struct sigma_state {
	163	enum {
	164	SIGMA_UNINITIALIZED = 0,
	165	SIGMA_IDLE,
	166	SIGMA_CAPTURE,
	167	SIGMA_DOWNLOAD,
	168	} state;
	169
	170	uint32_t stoppos, triggerpos;
	171	uint16_t lastts;
	172	uint16_t lastsample;
	173
	174	int triggerchunk;
	175	int chunks_downloaded;
	176	};
	177
ea9cfed7	178	/* Private, per-device-instance driver context. */
0e1357e8	179	struct dev_context {
99965709 HE	180	struct ftdi_context ftdic;
99965709 HE	181	uint64_t cur_samplerate;
9c939c51	182	uint64_t period_ps;
94ba4bd6	183	uint64_t limit_msec;
99965709 HE	184	struct timeval start_tv;
99965709 HE	185	int cur_firmware;
ba7dd8bb	186	int num_channels;
99965709 HE	187	int samples_per_event;
	188	int capture_ratio;
	189	struct sigma_trigger trigger;
5b5ea7c6	190	int use_triggers;
99965709	191	struct sigma_state state;
3e9b7f9c	192	void *cb_data;
99965709 HE	193	};
99965709 HE	194
204b1629	195	#endif