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204b1629 1/*
50985c20 2 * This file is part of the libsigrok project.
204b1629
UH
3 *
4 * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
0f8522bf
UH
22#ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_ASIX_SIGMA_H
23#define LIBSIGROK_HARDWARE_ASIX_SIGMA_ASIX_SIGMA_H
28a35d8a 24
3544f848 25#define LOG_PREFIX "asix-sigma"
47f4f073 26
fefa1800 27enum sigma_write_register {
28a35d8a
HE
28 WRITE_CLOCK_SELECT = 0,
29 WRITE_TRIGGER_SELECT0 = 1,
30 WRITE_TRIGGER_SELECT1 = 2,
31 WRITE_MODE = 3,
32 WRITE_MEMROW = 4,
33 WRITE_POST_TRIGGER = 5,
34 WRITE_TRIGGER_OPTION = 6,
35 WRITE_PIN_VIEW = 7,
36
fefa1800 37 WRITE_TEST = 15,
28a35d8a
HE
38};
39
fefa1800 40enum sigma_read_register {
28a35d8a
HE
41 READ_ID = 0,
42 READ_TRIGGER_POS_LOW = 1,
43 READ_TRIGGER_POS_HIGH = 2,
44 READ_TRIGGER_POS_UP = 3,
45 READ_STOP_POS_LOW = 4,
46 READ_STOP_POS_HIGH = 5,
47 READ_STOP_POS_UP = 6,
48 READ_MODE = 7,
49 READ_PIN_CHANGE_LOW = 8,
50 READ_PIN_CHANGE_HIGH = 9,
51 READ_BLOCK_LAST_TS_LOW = 10,
52 READ_BLOCK_LAST_TS_HIGH = 11,
53 READ_PIN_VIEW = 12,
54
fefa1800 55 READ_TEST = 15,
28a35d8a
HE
56};
57
1c2736f9
MV
58#define REG_ADDR_LOW (0x0 << 4)
59#define REG_ADDR_HIGH (0x1 << 4)
60#define REG_DATA_LOW (0x2 << 4)
61#define REG_DATA_HIGH_WRITE (0x3 << 4)
62#define REG_READ_ADDR (0x4 << 4)
63#define REG_DRAM_WAIT_ACK (0x5 << 4)
28a35d8a
HE
64
65/* Bit (1 << 4) can be low or high (double buffer / cache) */
1c2736f9
MV
66#define REG_DRAM_BLOCK (0x6 << 4)
67#define REG_DRAM_BLOCK_BEGIN (0x8 << 4)
68#define REG_DRAM_BLOCK_DATA (0xa << 4)
28a35d8a 69
57bbf56b
HE
70#define LEDSEL0 6
71#define LEDSEL1 7
72
28a35d8a
HE
73#define NEXT_REG 1
74
75#define EVENTS_PER_CLUSTER 7
76
77#define CHUNK_SIZE 1024
78
fd830beb
MV
79/*
80 * The entire ASIX Sigma DRAM is an array of struct sigma_dram_line[1024];
81 */
82
83/* One "DRAM cluster" contains a timestamp and 7 samples, 16b total. */
84struct sigma_dram_cluster {
85 uint8_t timestamp_lo;
86 uint8_t timestamp_hi;
87 struct {
88 uint8_t sample_hi;
89 uint8_t sample_lo;
90 } samples[7];
91};
92
93/* One "DRAM line" contains 64 "DRAM clusters", 1024b total. */
94struct sigma_dram_line {
95 struct sigma_dram_cluster cluster[64];
96};
97
edca2c5c
HE
98struct clockselect_50 {
99 uint8_t async;
100 uint8_t fraction;
ba7dd8bb 101 uint16_t disabled_channels;
edca2c5c
HE
102};
103
57bbf56b
HE
104/* The effect of all these are still a bit unclear. */
105struct triggerinout {
106 uint8_t trgout_resistor_enable : 1;
107 uint8_t trgout_resistor_pullup : 1;
108 uint8_t reserved1 : 1;
109 uint8_t trgout_bytrigger : 1;
110 uint8_t trgout_byevent : 1;
111 uint8_t trgout_bytriggerin : 1;
112 uint8_t reserved2 : 2;
113
114 /* Should be set same as the first two */
115 uint8_t trgout_resistor_enable2 : 1;
116 uint8_t trgout_resistor_pullup2 : 1;
117
118 uint8_t reserved3 : 1;
119 uint8_t trgout_long : 1;
120 uint8_t trgout_pin : 1; /* Use 1k resistor. Pullup? */
121 uint8_t trgin_negate : 1;
122 uint8_t trgout_enable : 1;
123 uint8_t trgin_enable : 1;
124};
125
ee492173
HE
126struct triggerlut {
127 /* The actual LUTs. */
128 uint16_t m0d[4], m1d[4], m2d[4];
129 uint16_t m3, m3s, m4;
130
131 /* Paramters should be sent as a single register write. */
132 struct {
133 uint8_t selc : 2;
134 uint8_t selpresc : 6;
135
136 uint8_t selinc : 2;
137 uint8_t selres : 2;
138 uint8_t sela : 2;
139 uint8_t selb : 2;
140
141 uint16_t cmpb;
142 uint16_t cmpa;
143 } params;
144};
145
c53d793f
HE
146/* Trigger configuration */
147struct sigma_trigger {
ba7dd8bb 148 /* Only two channels can be used in mask. */
a42aec7f
HE
149 uint16_t risingmask;
150 uint16_t fallingmask;
c53d793f
HE
151
152 /* Simple trigger support (<= 50 MHz). */
153 uint16_t simplemask;
154 uint16_t simplevalue;
155
c53d793f
HE
156 /* TODO: Advanced trigger support (boolean expressions). */
157};
158
159/* Events for trigger operation. */
160enum triggerop {
161 OP_LEVEL = 1,
162 OP_NOT,
163 OP_RISE,
164 OP_FALL,
165 OP_RISEFALL,
166 OP_NOTRISE,
167 OP_NOTFALL,
168 OP_NOTRISEFALL,
169};
170
171/* Logical functions for trigger operation. */
172enum triggerfunc {
173 FUNC_AND = 1,
174 FUNC_NAND,
175 FUNC_OR,
176 FUNC_NOR,
177 FUNC_XOR,
178 FUNC_NXOR,
179};
180
6aac7737
HE
181struct sigma_state {
182 enum {
183 SIGMA_UNINITIALIZED = 0,
184 SIGMA_IDLE,
185 SIGMA_CAPTURE,
186 SIGMA_DOWNLOAD,
187 } state;
188
6aac7737
HE
189 uint16_t lastts;
190 uint16_t lastsample;
6aac7737
HE
191};
192
ea9cfed7 193/* Private, per-device-instance driver context. */
0e1357e8 194struct dev_context {
99965709
HE
195 struct ftdi_context ftdic;
196 uint64_t cur_samplerate;
9c939c51 197 uint64_t period_ps;
94ba4bd6 198 uint64_t limit_msec;
99965709
HE
199 struct timeval start_tv;
200 int cur_firmware;
ba7dd8bb 201 int num_channels;
5fc01191 202 int cur_channels;
99965709
HE
203 int samples_per_event;
204 int capture_ratio;
205 struct sigma_trigger trigger;
5b5ea7c6 206 int use_triggers;
99965709 207 struct sigma_state state;
3e9b7f9c 208 void *cb_data;
99965709
HE
209};
210
204b1629 211#endif