Phrase communication buffer sizes in terms of FPGA register width,
instead of totalling the sizes of different bitfield width. Comment
where buffers are shared among different accesses, for awareness
during maintenance.
Introduce an "unknown register at offset 0x30" such that REG_TRIGGER
access can follow the pattern of determining the FPGA register's width.
#define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */
#define REG_BULK 0x08 /* Write start addr, byte count to download samples. */
#define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */
#define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */
#define REG_BULK 0x08 /* Write start addr, byte count to download samples. */
#define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */
-#define REG_TRIGGER 0x20 /* write level and edge trigger config. */
+#define REG_TRIGGER 0x20 /* Write level and edge trigger config. */
+#define REG_UNKNOWN_30 0x30
#define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */
#define REG_PWM1 0x70 /* Write config for user PWM1. */
#define REG_PWM2 0x78 /* Write config for user PWM2. */
#define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */
#define REG_PWM1 0x70 /* Write config for user PWM1. */
#define REG_PWM2 0x78 /* Write config for user PWM2. */
static int check_fpga_bitstream(const struct sr_dev_inst *sdi)
{
uint8_t init_rsp;
static int check_fpga_bitstream(const struct sr_dev_inst *sdi)
{
uint8_t init_rsp;
+ uint8_t buff[REG_PWM_EN - REG_RUN]; /* Larger of REG_RUN, REG_PWM_EN. */
int ret;
uint16_t run_state;
uint8_t pwm_en;
size_t read_len;
int ret;
uint16_t run_state;
uint8_t pwm_en;
size_t read_len;
- uint8_t buff[sizeof(run_state)];
const uint8_t *rdptr;
sr_dbg("Checking operation of the FPGA bitstream.");
const uint8_t *rdptr;
sr_dbg("Checking operation of the FPGA bitstream.");
{
int ret;
uint16_t duty_R79, duty_R56;
{
int ret;
uint16_t duty_R79, duty_R56;
- uint8_t buf[2 * sizeof(uint16_t)];
+ uint8_t buf[REG_PWM1 - REG_THRESHOLD]; /* Width of REG_THRESHOLD. */
uint8_t *wrptr;
/* Clamp threshold setting to valid range for LA2016. */
uint8_t *wrptr;
/* Clamp threshold setting to valid range for LA2016. */
struct sr_trigger_match *match;
uint16_t ch_mask;
int ret;
struct sr_trigger_match *match;
uint16_t ch_mask;
int ret;
- uint8_t buf[4 * sizeof(uint32_t)];
+ uint8_t buf[REG_UNKNOWN_30 - REG_TRIGGER]; /* Width of REG_TRIGGER. */
uint8_t *wrptr;
devc = sdi->priv;
uint8_t *wrptr;
devc = sdi->priv;
- uint8_t buff[sizeof(state)];
+ uint8_t buff[REG_PWM_EN - REG_RUN]; /* Width of REG_RUN. */
const uint8_t *rdptr;
const char *label;
const uint8_t *rdptr;
const char *label;
{
struct dev_context *devc;
int ret;
{
struct dev_context *devc;
int ret;
- uint8_t buf[3 * sizeof(uint32_t)];
+ uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */
const uint8_t *rdptr;
devc = sdi->priv;
const uint8_t *rdptr;
devc = sdi->priv;
struct dev_context *devc;
struct sr_usb_dev_inst *usb;
int ret;
struct dev_context *devc;
struct sr_usb_dev_inst *usb;
int ret;
- uint8_t wrbuf[2 * sizeof(uint32_t)];
+ uint8_t wrbuf[REG_SAMPLING - REG_BULK]; /* Width of REG_BULK. */
uint8_t *wrptr;
uint32_t to_read;
uint8_t *buffer;
uint8_t *wrptr;
uint32_t to_read;
uint8_t *buffer;
gboolean show_message)
{
struct dev_context *devc;
gboolean show_message)
{
struct dev_context *devc;
+ uint8_t buf[8]; /* Larger size of manuf date and device type magic. */
size_t rdoff, rdlen;
const uint8_t *rdptr;
uint8_t date_yy, date_mm;
size_t rdoff, rdlen;
const uint8_t *rdptr;
uint8_t date_yy, date_mm;