chromium-twinkie: add analog VBUS channels

[libsigrok.git] / src / output / csv.c

diff --git a/src/output/csv.c b/src/output/csv.c
index f3e6e335e73907bc4927ddbee755d0bfadbb5a1d..2be4db372f67101ae3241ede4d7d4c2e9ba3b27c 100644 (file)
--- a/src/output/csv.c
+++ b/src/output/csv.c
@@ -260,7 +260,7 @@ static GString *gen_header(const struct sr_output *o,
                g_string_append_printf(header, "%s Channels (%d/%d):",
                        ctx->comment, ctx->num_analog_channels +
                        ctx->num_logic_channels, num_channels);
-               for (i = 0, l = o->sdi->channels; l; l = l->next, i++) {
+               for (l = o->sdi->channels; l; l = l->next) {
                        ch = l->data;
                        if (ch->enabled)
                                g_string_append_printf(header, " %s,", ch->name);
@@ -380,7 +380,7 @@ static void process_logic(struct context *ctx,
                if (ctx->channels[j].ch->type == SR_CHANNEL_LOGIC) {
                        for (i = 0; i < num_samples; i++) {
                                sample = logic->data + i * logic->unitsize;
-                               idx = ctx->channels[ch].ch->index;
+                               idx = ctx->channels[j].ch->index;
                                if (ctx->label_do && !ctx->label_names)
                                        ctx->channels[j].label = "logic";
                                ctx->logic_samples[i * ctx->num_logic_channels + ch] = sample[idx / 8] & (1 << (idx % 8));
@@ -608,6 +608,7 @@ static int cleanup(struct sr_output *o)
                g_free((gpointer)ctx->frame);
                g_free((gpointer)ctx->comment);
                g_free((gpointer)ctx->gnuplot);
+               g_free((gpointer)ctx->value);
                g_free(ctx->previous_sample);
                g_free(ctx->channels);
                g_free(o->priv);