regvals[0].reg = REG_DIV_BYPASS;
regvals[0].val = 1;
- regvals[1].reg = REG_MEM_CTRL2;
- regvals[1].val = 2;
+ regvals[1].reg = REG_MEM_CTRL;
+ regvals[1].val = MEM_CTRL_CLR_IDX;
- regvals[2].reg = REG_MEM_CTRL4;
+ regvals[2].reg = REG_MEM_START;
regvals[2].val = 4;
devc->reg_write_pos = 0;
sr_dbg("%zu words in capture buffer.", acq->mem_addr_fill);
- if (acq->mem_addr_fill > 0 && sdi->status == SR_ST_ACTIVE)
+ if (acq->mem_addr_fill > 0 && !devc->cancel_requested)
issue_read_start(sdi);
else
issue_read_end(sdi);
regvals = devc->reg_write_seq;
- regvals[0].reg = REG_CMD_CTRL2;
- regvals[0].val = 10;
+ regvals[0].reg = REG_LONG_ADDR;
+ regvals[0].val = LREG_CAP_CTRL;
- regvals[1].reg = REG_CMD_CTRL3;
+ regvals[1].reg = REG_LONG_LOW;
regvals[1].val = 0;
- regvals[2].reg = REG_CMD_CTRL4;
+ regvals[2].reg = REG_LONG_HIGH;
regvals[2].val = 0;
- regvals[3].reg = REG_CMD_CTRL1;
+ regvals[3].reg = REG_LONG_STROBE;
regvals[3].val = 0;
regvals[4].reg = REG_DIV_BYPASS;
return;
}
- /* TODO: Find out the actual bit width of these fields as stored
- * in the FPGA. These fields are definitely less than 64 bit wide
- * internally, and the unused bits occasionally even contain garbage.
- */
mem_fill = LWLA_TO_UINT32(acq->xfer_buf_in[0]);
- duration = LWLA_TO_UINT32(acq->xfer_buf_in[4]);
- flags = LWLA_TO_UINT32(acq->xfer_buf_in[8]) & STATUS_FLAG_MASK;
+ duration = LWLA_TO_UINT32(acq->xfer_buf_in[4])
+ | ((uint64_t)LWLA_TO_UINT32(acq->xfer_buf_in[5]) << 32);
+ flags = LWLA_TO_UINT32(acq->xfer_buf_in[8]) & STATUS_FLAG_MASK;
/* The LWLA1034 runs at 125 MHz if the clock divider is bypassed.
* However, the time base used for the duration is apparently not
lwla_free_acquisition_state(devc->acquisition);
devc->acquisition = NULL;
-
- sdi->status = SR_ST_ACTIVE;
+ devc->cancel_requested = FALSE;
}
/* USB output transfer completion callback.
submit_transfer(devc, devc->acquisition->xfer_in);
break;
case STATE_STOP_CAPTURE:
- if (sdi->status == SR_ST_ACTIVE)
+ if (!devc->cancel_requested)
request_capture_length(sdi);
else
end_acquisition(sdi);
*/
SR_PRIV int lwla_init_device(const struct sr_dev_inst *sdi)
{
+ uint64_t value;
struct dev_context *devc;
int ret;
- uint32_t value;
devc = sdi->priv;
devc->cur_clock_config = CONF_CLOCK_NONE;
ret = lwla_set_clock_config(sdi);
-
- if (ret != SR_OK)
- return ret;
-
- ret = lwla_write_reg(sdi->conn, REG_CMD_CTRL2, 100);
if (ret != SR_OK)
return ret;
- ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL1, &value);
+ ret = lwla_read_long_reg(sdi->conn, LREG_TEST_ID, &value);
if (ret != SR_OK)
return ret;
- sr_dbg("Received test word 0x%08X back.", value);
- if (value != 0x12345678)
- return SR_ERR;
- ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL4, &value);
+ /* Ignore the value returned by the first read */
+ ret = lwla_read_long_reg(sdi->conn, LREG_TEST_ID, &value);
if (ret != SR_OK)
return ret;
- sr_dbg("Received test word 0x%08X back.", value);
- if (value != 0x12345678)
- return SR_ERR;
- ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL3, &value);
- if (ret != SR_OK)
- return ret;
- sr_dbg("Received test word 0x%08X back.", value);
- if (value != 0x87654321)
+ if (value != UINT64_C(0x1234567887654321)) {
+ sr_err("Received invalid test word 0x%016" PRIX64 ".", value);
return SR_ERR;
-
- return ret;
+ }
+ return SR_OK;
}
/* Select the LWLA clock configuration. If the clock source changed from
SR_PRIV int lwla_set_clock_config(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
+ struct drv_context *drvc;
int ret;
enum clock_config choice;
devc = sdi->priv;
+ drvc = sdi->driver->context;
if (sdi->status == SR_ST_INACTIVE)
choice = CONF_CLOCK_NONE;
if (choice != devc->cur_clock_config) {
devc->cur_clock_config = CONF_CLOCK_NONE;
- ret = lwla_send_bitstream(sdi->conn, bitstream_map[choice]);
+ ret = lwla_send_bitstream(drvc->sr_ctx, sdi->conn,
+ bitstream_map[choice]);
if (ret == SR_OK)
devc->cur_clock_config = choice;
return ret;
sr_info("External clock, rising edge.");
}
- regvals[0].reg = REG_MEM_CTRL2;
- regvals[0].val = 2;
-
- regvals[1].reg = REG_MEM_CTRL2;
- regvals[1].val = 1;
+ regvals[0].reg = REG_MEM_CTRL;
+ regvals[0].val = MEM_CTRL_CLR_IDX;
- regvals[2].reg = REG_CMD_CTRL2;
- regvals[2].val = 10;
+ regvals[1].reg = REG_MEM_CTRL;
+ regvals[1].val = MEM_CTRL_WRITE;
- regvals[3].reg = REG_CMD_CTRL3;
- regvals[3].val = 0x74;
+ regvals[2].reg = REG_LONG_ADDR;
+ regvals[2].val = LREG_CAP_CTRL;
- regvals[4].reg = REG_CMD_CTRL4;
+ regvals[3].reg = REG_LONG_LOW;
+ regvals[3].val = CAP_CTRL_CLR_TIMEBASE | CAP_CTRL_FLUSH_FIFO
+ | CAP_CTRL_CLR_FIFOFULL | CAP_CTRL_CLR_COUNTER;
+ regvals[4].reg = REG_LONG_HIGH;
regvals[4].val = 0;
- regvals[5].reg = REG_CMD_CTRL1;
+ regvals[5].reg = REG_LONG_STROBE;
regvals[5].val = 0;
regvals[6].reg = REG_DIV_BYPASS;
regvals = devc->reg_write_seq;
- regvals[0].reg = REG_CMD_CTRL2;
- regvals[0].val = 10;
+ regvals[0].reg = REG_LONG_ADDR;
+ regvals[0].val = LREG_CAP_CTRL;
- regvals[1].reg = REG_CMD_CTRL3;
- regvals[1].val = 1;
+ regvals[1].reg = REG_LONG_LOW;
+ regvals[1].val = CAP_CTRL_TRG_EN;
- regvals[2].reg = REG_CMD_CTRL4;
+ regvals[2].reg = REG_LONG_HIGH;
regvals[2].val = 0;
- regvals[3].reg = REG_CMD_CTRL1;
+ regvals[3].reg = REG_LONG_STROBE;
regvals[3].val = 0;
devc->reg_write_pos = 0;
/* If no event flags are set the timeout must have expired. */
if (revents == 0 && devc->state == STATE_STATUS_WAIT) {
- if (sdi->status == SR_ST_STOPPING)
+ if (devc->cancel_requested)
issue_stop_capture(sdi);
else
request_capture_status(sdi);
projects / libsigrok.git / blobdiff