switch (devc->cfg_trigger_slope) {
case EDGE_POSITIVE:
trigger_mask |= (uint64_t)1 << 35;
- break;
+ break;
case EDGE_NEGATIVE:
trigger_mask |= (uint64_t)1 << 34;
- break;
+ break;
}
command[19] = LWLA_WORD_0(trigger_mask);
command[25] = LWLA_WORD_2(memory_limit);
command[26] = LWLA_WORD_3(memory_limit);
- /* Fill remaining 64-bit words with zeroes. */
- memset(&command[27], 0, 16 * sizeof(uint16_t));
+ /* Fill remaining words with zeroes. */
+ memset(&command[27], 0, sizeof(command) - 27 * sizeof(command[0]));
return lwla_send_command(sdi->conn, command, ARRAY_SIZE(command));
}
sr_dbg("%zu words in capture buffer.", acq->mem_addr_fill);
- if (acq->mem_addr_fill > 0 && sdi->status == SR_ST_ACTIVE)
+ if (acq->mem_addr_fill > 0 && !devc->cancel_requested)
issue_read_start(sdi);
else
issue_read_end(sdi);
regvals = devc->reg_write_seq;
- regvals[0].reg = REG_CMD_CTRL2;
+ regvals[0].reg = REG_LONG_ADDR;
regvals[0].val = 10;
- regvals[1].reg = REG_CMD_CTRL3;
+ regvals[1].reg = REG_LONG_LOW;
regvals[1].val = 0;
- regvals[2].reg = REG_CMD_CTRL4;
+ regvals[2].reg = REG_LONG_HIGH;
regvals[2].val = 0;
- regvals[3].reg = REG_CMD_CTRL1;
+ regvals[3].reg = REG_LONG_STROBE;
regvals[3].val = 0;
regvals[4].reg = REG_DIV_BYPASS;
lwla_free_acquisition_state(devc->acquisition);
devc->acquisition = NULL;
-
- sdi->status = SR_ST_ACTIVE;
+ devc->cancel_requested = FALSE;
}
/* USB output transfer completion callback.
submit_transfer(devc, devc->acquisition->xfer_in);
break;
case STATE_STOP_CAPTURE:
- if (sdi->status == SR_ST_ACTIVE)
+ if (!devc->cancel_requested)
request_capture_length(sdi);
else
end_acquisition(sdi);
if (ret != SR_OK)
return ret;
- ret = lwla_write_reg(sdi->conn, REG_CMD_CTRL2, 100);
+ ret = lwla_write_reg(sdi->conn, REG_LONG_ADDR, 100);
if (ret != SR_OK)
return ret;
- ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL1, &value);
+ ret = lwla_read_reg(sdi->conn, REG_LONG_STROBE, &value);
if (ret != SR_OK)
return ret;
sr_dbg("Received test word 0x%08X back.", value);
if (value != 0x12345678)
return SR_ERR;
- ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL4, &value);
+ ret = lwla_read_reg(sdi->conn, REG_LONG_HIGH, &value);
if (ret != SR_OK)
return ret;
sr_dbg("Received test word 0x%08X back.", value);
if (value != 0x12345678)
return SR_ERR;
- ret = lwla_read_reg(sdi->conn, REG_CMD_CTRL3, &value);
+ ret = lwla_read_reg(sdi->conn, REG_LONG_LOW, &value);
if (ret != SR_OK)
return ret;
sr_dbg("Received test word 0x%08X back.", value);
return ret;
}
-SR_PRIV int lwla_convert_trigger(const struct sr_dev_inst *sdi)
-{
- struct dev_context *devc;
- struct sr_trigger *trigger;
- struct sr_trigger_stage *stage;
- struct sr_trigger_match *match;
- const GSList *l, *m;
- uint64_t channel_index;
-
- devc = sdi->priv;
-
- devc->trigger_mask = 0;
- devc->trigger_values = 0;
- devc->trigger_edge_mask = 0;
-
- if (!(trigger = sr_session_trigger_get(sdi->session)))
- return SR_OK;
-
- if (g_slist_length(trigger->stages) > 1) {
- sr_err("This device only supports 1 trigger stage.");
- return SR_ERR;
- }
-
- for (l = trigger->stages; l; l = l->next) {
- stage = l->data;
- for (m = stage->matches; m; m = m->next) {
- match = m->data;
- if (!match->channel->enabled)
- /* Ignore disabled channels with a trigger. */
- continue;
- channel_index = (uint64_t)1 << match->channel->index;
- devc->trigger_mask |= channel_index;
- switch (match->match) {
- case SR_TRIGGER_ONE:
- devc->trigger_values |= channel_index;
- break;
- case SR_TRIGGER_RISING:
- devc->trigger_values |= channel_index;
- /* Fall through for edge mask. */
- case SR_TRIGGER_FALLING:
- devc->trigger_edge_mask |= channel_index;
- break;
- }
- }
- }
-
- return SR_OK;
-}
-
/* Select the LWLA clock configuration. If the clock source changed from
* the previous setting, this will download a new bitstream to the FPGA.
*/
SR_PRIV int lwla_set_clock_config(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
+ struct drv_context *drvc;
int ret;
enum clock_config choice;
devc = sdi->priv;
+ drvc = sdi->driver->context;
if (sdi->status == SR_ST_INACTIVE)
choice = CONF_CLOCK_NONE;
if (choice != devc->cur_clock_config) {
devc->cur_clock_config = CONF_CLOCK_NONE;
- ret = lwla_send_bitstream(sdi->conn, bitstream_map[choice]);
+ ret = lwla_send_bitstream(drvc->sr_ctx, sdi->conn,
+ bitstream_map[choice]);
if (ret == SR_OK)
devc->cur_clock_config = choice;
return ret;
regvals[1].reg = REG_MEM_CTRL2;
regvals[1].val = 1;
- regvals[2].reg = REG_CMD_CTRL2;
+ regvals[2].reg = REG_LONG_ADDR;
regvals[2].val = 10;
- regvals[3].reg = REG_CMD_CTRL3;
+ regvals[3].reg = REG_LONG_LOW;
regvals[3].val = 0x74;
- regvals[4].reg = REG_CMD_CTRL4;
+ regvals[4].reg = REG_LONG_HIGH;
regvals[4].val = 0;
- regvals[5].reg = REG_CMD_CTRL1;
+ regvals[5].reg = REG_LONG_STROBE;
regvals[5].val = 0;
regvals[6].reg = REG_DIV_BYPASS;
regvals = devc->reg_write_seq;
- regvals[0].reg = REG_CMD_CTRL2;
+ regvals[0].reg = REG_LONG_ADDR;
regvals[0].val = 10;
- regvals[1].reg = REG_CMD_CTRL3;
+ regvals[1].reg = REG_LONG_LOW;
regvals[1].val = 1;
- regvals[2].reg = REG_CMD_CTRL4;
+ regvals[2].reg = REG_LONG_HIGH;
regvals[2].val = 0;
- regvals[3].reg = REG_CMD_CTRL1;
+ regvals[3].reg = REG_LONG_STROBE;
regvals[3].val = 0;
devc->reg_write_pos = 0;
/* If no event flags are set the timeout must have expired. */
if (revents == 0 && devc->state == STATE_STATUS_WAIT) {
- if (sdi->status == SR_ST_STOPPING)
+ if (devc->cancel_requested)
issue_stop_capture(sdi);
else
request_capture_status(sdi);
projects / libsigrok.git / blobdiff