* alignment is guaranteed.
*/
out_p = (uint32_t *)&acq->out_packet[acq->out_index * UNIT_SIZE];
- in_p = &acq->xfer_buf_in[acq->in_index];
+ in_p = &acq->xfer_buf_in[acq->in_index];
/*
* Transfer two samples at a time, taking care to swap the 16-bit
* halves of each input word but keeping the samples themselves in
{
uint32_t *in_p;
uint16_t *out_p;
- unsigned int words_left;
- unsigned int max_samples, run_samples;
- unsigned int wi, ri;
+ unsigned int words_left, max_samples, run_samples, wi, ri;
uint32_t word;
uint16_t sample;
acq->samples_done += run_samples;
if (run_samples == max_samples)
- break; /* packet full or sample limit reached */
+ break; /* Packet full or sample limit reached. */
if (wi >= words_left)
- break; /* done with current transfer */
+ break; /* Done with current transfer. */
word = GUINT32_FROM_LE(in_p[wi]);
acq->sample = word >> 16;
acq->run_len = (word & 0xFFFF) + 1;
}
+
acq->in_index += wi;
acq->mem_addr_done += wi;
}
struct dev_context *devc;
struct sr_usb_dev_inst *usb;
unsigned int i;
- int xfer_len;
- int ret;
+ int xfer_len, ret;
uint16_t command[5];
unsigned char reply[512];
devc = sdi->priv;
- usb = sdi->conn;
+ usb = sdi->conn;
command[0] = LWLA_WORD(CMD_READ_MEM32);
command[1] = LWLA_WORD_0(start);
xfer_len);
return SR_ERR;
}
+
return SR_OK;
}
{
struct dev_context *devc;
struct drv_context *drvc;
- int config;
- int ret;
+ int config, ret;
devc = sdi->priv;
drvc = sdi->driver->context;
if (sdi->status == SR_ST_INACTIVE)
- return SR_OK; /* the LWLA1016 has no off state */
+ return SR_OK; /* The LWLA1016 has no off state. */
config = (devc->cfg_rle) ? FPGA_100_TS : FPGA_100;
if (config == devc->active_fpga_config)
- return SR_OK; /* no change */
+ return SR_OK; /* No change. */
ret = lwla_send_bitstream(drvc->sr_ctx, sdi->conn,
bitstream_map[config]);
};
uint32_t value;
int ret;
-
const unsigned int test_count = 24;
- ret = lwla_read_reg(sdi->conn, REG_TEST_ID, &value);
- if (ret != SR_OK)
- return ret;
+ lwla_read_reg(sdi->conn, REG_TEST_ID, &value);
/* Ignore the value returned by the first read. */
ret = lwla_read_reg(sdi->conn, REG_TEST_ID, &value);
ret = test_read_memory(sdi, 0, test_count);
if (ret != SR_OK)
return ret;
+
/*
* Issue another read request or the device will stall, for whatever
* reason. This happens both with and without the short transfer quirk.
int ret;
devc = sdi->priv;
- usb = sdi->conn;
+ usb = sdi->conn;
ret = lwla_write_reg(usb, REG_CHAN_MASK, devc->channel_mask);
if (ret != SR_OK)
unsigned int chunk_len, count;
devc = sdi->priv;
- acq = devc->acquisition;
+ acq = devc->acquisition;
acq->xfer_out->length = 0;
acq->reg_seq_pos = 0;
int expect_len;
devc = sdi->priv;
- acq = devc->acquisition;
+ acq = devc->acquisition;
switch (devc->state) {
case STATE_STATUS_REQUEST: