saleae-logic16: Clearer error message.

[libsigrok.git] / src / hardware / saleae-logic16 / protocol.c

diff --git a/src/hardware/saleae-logic16/protocol.c b/src/hardware/saleae-logic16/protocol.c
index ac0316d4bd2bb86118a76e6b4951fccc09b59137..d60bf3e7a50aa20c4236b072aaf864a743adc698 100644 (file)
--- a/src/hardware/saleae-logic16/protocol.c
+++ b/src/hardware/saleae-logic16/protocol.c
@@ -470,7 +470,7 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
        reg1 &= ~0x20;
 
        if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x08) {
-               sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x08.", reg1);
+               sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x08.", reg1);
                return SR_ERR;
        }
 
@@ -499,7 +499,7 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
                return ret;
 
        if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x48) {
-               sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x48. "
+               sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x48. "
                       "Proceeding anyway.", reg1);
        }
 
@@ -507,7 +507,7 @@ SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi,
                return ret;
 
        if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg10 != clock_select) {
-               sr_dbg("Invalid state at acquisition setup: 0x%02x != 0x%02x.",
+               sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x.",
                       reg10, clock_select);
                return SR_ERR;
        }
@@ -713,6 +713,7 @@ SR_PRIV void logic16_receive_transfer(struct libusb_transfer *transfer)
        struct dev_context *devc;
        size_t new_samples, num_samples;
        int trigger_offset;
+       int pre_trigger_samples;
 
        sdi = transfer->user_data;
        devc = sdi->priv;
@@ -785,8 +786,9 @@ SR_PRIV void logic16_receive_transfer(struct libusb_transfer *transfer)
                        devc->sent_samples += new_samples;
                } else {
                        trigger_offset = soft_trigger_logic_check(devc->stl,
-                                       devc->convbuffer, new_samples * 2, NULL);
+                                       devc->convbuffer, new_samples * 2, &pre_trigger_samples);
                        if (trigger_offset > -1) {
+                               devc->sent_samples += pre_trigger_samples;
                                packet.type = SR_DF_LOGIC;
                                packet.payload = &logic;
                                num_samples = new_samples - trigger_offset;