openbench-logic-sniffer: fix acquisition restart with trigger enabled

[libsigrok.git] / src / hardware / openbench-logic-sniffer / api.c

diff --git a/src/hardware/openbench-logic-sniffer/api.c b/src/hardware/openbench-logic-sniffer/api.c
index 1e22c5b82f97970c9a83e00c36419d47071ad583..5e74a5236e745b56de2bfde26e3baa8ebebf212f 100644 (file)
--- a/src/hardware/openbench-logic-sniffer/api.c
+++ b/src/hardware/openbench-logic-sniffer/api.c
@@ -126,14 +126,7 @@ static GSList *scan(struct sr_dev_driver *di, GSList *options)
        if (serial_open(serial, SERIAL_RDWR) != SR_OK)
                return NULL;
 
-       ret = SR_OK;
-       for (i = 0; i < 5; i++) {
-               if ((ret = send_shortcommand(serial, CMD_RESET)) != SR_OK) {
-                       sr_err("Port %s is not writable.", conn);
-                       break;
-               }
-       }
-       if (ret != SR_OK) {
+       if (ols_send_reset(serial) != SR_OK) {
                serial_close(serial);
                sr_err("Could not use port %s. Quitting.", conn);
                return NULL;
@@ -480,6 +473,14 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi)
                return SR_ERR;
        }
        if (devc->num_stages > 0) {
+               /*
+                * According to http://mygizmos.org/ols/Logic-Sniffer-FPGA-Spec.pdf
+                * reset command must be send prior each arm command
+                */
+               sr_dbg("Send reset command before trigger configure");
+               if (ols_send_reset(serial) != SR_OK)
+                       return SR_ERR;
+
                delaycount = readcount * (1 - devc->capture_ratio / 100.0);
                devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages;
                for (i = 0; i <= devc->num_stages; i++) {