* The device expects some zero padding to follow the content of the
* file which contains the FPGA bitstream. Specify the chunk size here.
*/
-#define LA2016_EP2_PADDING 2048
+#define LA2016_EP2_PADDING 4096
/*
* Whether the logic input threshold voltage is a config item of the
uint64_t fw_uploaded; /* Timestamp of most recent FW upload. */
uint8_t identify_magic, identify_magic2;
const struct kingst_model *model;
+ char **channel_names_logic;
struct sr_channel_group *cg_logic, *cg_pwm;
/* User specified parameters. */